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11 views

a-single-error-correction-double-burst-error-detection-code.pdf

Uploaded by

Baranidharan P S
Copyright
© © All Rights Reserved
Available Formats
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A single error correction double burst

error detection code - Signals, Systems


& Computers, 2003 The Thrity-Seventh
Asilomar Conference on
Lance Bodnar Viasat Inc

2004

Structured summary

Snapshot

An improved error indicating system capable of correcting single


errors and detecting multiple adjacent bit burst errors is discussed,
using the minimum number of redundant bits possible.

Key findings
 The error correction code developed in this study can correct single bit errors and
detect double bit burst errors using a small number of additional bits, and can be
realized with just the available parity bit locations in the physical memory.
 The Gilert-Varshamov bound states that there exists a linear code Cover a field of q
elements, having length n, at most 111 parity checks, and a minimum distance of at least
d provided the following bound is met Consider a system with a processor word size of
48-bits wide, stored in three 18-bit wide RAM chips, giving a total of 54-bits of storage
per RAM address
 Because an error correction code isn't obviously available, most system designers resort
to using the redundant bits m just as simple parity bits
 The syndromes for single bit errors will contain a one in the i" bit corresponding to the
corrected code word as the i" column of H
 This allows the detection of two bit burst errors and correction of any single bit errors

Objectives
The objective of this study is to develop an error correction code that can correct single bit
errors and detect double bit burst errors, while minimizing the number of redundant bits
required.
Methods
The error correction code is created by constructing its parity check matrix H, and the code
is generated by using a k-m row by k column generator matrix G that satisfies c = iG.

Results
The error correction code developed in this study can correct single bit errors and detect
double bit burst errors, and can be implemented using a small number of additional bits.

Conclusions
The error correction code developed in this study provides a significant improvement in
data storage robustness and correctness in critical system environments, and can be
implemented using a small number of additional bits.

Analysis

Research comparison

Counterpoint to earlier claims


However, the number of redundant bits needed to implement modem FECs can be relatively
large, driving the number of memory elements needed to support it, and thus increase the
actual physical memory space susceptible to SEU. Our patented error correction code [3]
soives these two competing objectives, by not needing a large number of bits for FEC, and
by keeping the number memory parts small

Limitations
The error correction code developed in this study has limitations in terms of the number of
redundant bits required, and the physical constraints of the system.

Future work
Future work includes automating the code generation process to search out a set of possible
candidate codes, and generalizing the method to different size information vectors and
number of additional bits needed.

Practical applications
The error correction code developed in this study has practical applications in critical
system environments, such as high flying aircraft, where data storage robustness and
correctness are crucial.

Abstract
Our patented error correction code [3] soives these two competing objectives, by not
needing a large number of bits for FEC, and by keeping the number memory parts small. It
does this by concentrating on single bit and adjacent double bit errors that are by far the
most common types of SEU errors. This reduces the constraint on the number of redundant
bits needed to implement the error correction and detection code. In many instances this
new code may be realized with just the available parity bit locations in the physical
memory. A significant savings in memory parts, while obtaining the needed data protection.

Bibliography
1. Inc, L. B. V.. (2004). A single error correction double burst error detection code - Signals,
Systems & Computers, 2003 The Thrity-Seventh Asilomar Conference on.

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