MOS Capacitances

Dynamic Behavior

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Dynamic Behavior of MOS Transistor
G

CGS CGD

S D

CSB CGB CDB

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 The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+

Cross section

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 Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

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Gate Capacitance

CG C
WLC ox WLC ox CG C
2WLC ox
CG CS 3
WLC ox C G CS = CG CD WLC ox
CGC B
2 2 CGCD

VG S 0 VDS /( VG S-VT) 1

Capacitance as a function of VGS Capacitance as a function of the

(with VDS = 0) degree of saturation

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 Measuring the Gate Cap

3 102 16
10

V GS 9

Gate Capacitance (F)

8
I 7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2
V GS (V)

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 Diffusion Capacitance
Channel-stop implant
N A1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A

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Junction Capacitance

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Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

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 Capacitances in 0.25 mm CMOS
process

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The Sub-
Sub-Micron MOS Transistor
 Threshold Variations
 Subthreshold Conduction
 Parasitic Resistances

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 Threshold Variations

VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS ) (for low L)

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 Sub--Threshold Conduction
Sub
-2
10 The Slope Factor
Linear qVGS
CD
I D ~ I 0e , n  1
-4 nkT
10
Cox
-6
10 Quadratic
S is DVGS for ID2/ID1 =10
ID (A)

-8
10

-10 Exponential
10

-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

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 Sub--Threshold ID vs VGS
Sub
qVGS
 qV
 DS 
I D  I 0e nkT 1  e kT 
 
 

VDS from 0 to 0.5V

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 Sub--Threshold ID vs VDS
Sub
qVGS
 qV
 DS 
I D  I 0e nkT 1  e kT 1    VDS 
 
 

VGS from 0 to 0.3V

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 Summary of MOSFET Operating
Regions
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence

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 Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain

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 Latch--up
Latch

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 Future Perspectives

25 nm FINFET MOS transistor

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