Lecture 1

Introduction to Physical Design (Part I)

VLSI Physical Design Fundamentals Course

Phil Hoang
Tresemi
Agenda

▪ Introduction
▪ Course Overview
▪ Course Objectives and Outcomes
▪ Learning Methodology
▪ Introduction to Physical Design, Part I

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Introduction

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Course Overview

▪ Objectives: Upon completing this course, participants will:

− Master VLSI Physical Design Principles: Learn about floorplanning, power grid creation, placement, clock tree
synthesis, and routing.
− Develop Skills in Physical Design Optimization: Cultivate the ability to analyze and optimize performance,
power, area, reliability, manufacturability, and time to market aspects of IC designs.
− Gain Hands-On Experience: Work with Cadence’s Innovus tool for physical design and analysis.
▪ Prerequisites:
− Proficiency in English: A strong command of the English language is essential for effective engagement with
course materials, lectures, and discussions.
− Foundational Understanding of Digital Logic Design: Participants should have a foundational grasp of digital
logic design, including concepts such as Boolean algebra, logic gates, and sequential and combinational circuits.
− Basic Knowledge of Very Large-Scale Integration (VLSI) Concepts: Participants are expected to possess
fundamental knowledge of VLSI concepts. This includes an understanding of electronic devices (transistors,
diodes, resistors, capacitors, inductors), transistor-level logic and circuit design, semiconductor fabrication
processes, and basic IC architecture.
− Familiarity with the Linux Operating System and Scripting Languages: Participants should have practical
experience with the Linux operating system and a basic understanding of scripting languages (e.g., Perl/Python
and TCL). This knowledge is beneficial for using EDA tools and automating physical design tasks.

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Syllabus

▪ Link to Syllabus

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Course Overview (2)

+ Tại Hà Nội:
▪ Course Format: • Địa chỉ: Tầng 6, Trung
tâm Đổi mới sáng tạo
− Lectures: Quốc gia NIC Hà Nội,
• Online via Zoom (Zoom ngõ 7 Tôn Thất Thuyết,
Information) Cầu Giấy, Hà Nội.
+ Tại TP. Hồ Chí Minh:
• Thời gian: Thứ 4 (13h30
• Tuesdays & Fridays, 9am-11am • Địa chỉ: Trường Đại học
- 17h30) và Thứ 7
Công nghệ Thông tin,
− Labs: (08h00 -12h00).
Đại học Quốc Gia
TP.HCM, Khu phố 6,
• In-person at NIC, DUT, or UIT
+ Tại Đà Nẵng: P.Linh Trung, Tp.Thủ
• Specific schedules are • Địa chỉ: Trường Đại học Đức, Tp.Hồ Chí Minh.
managed by the local teams Bách Khoa, Đại học Đà • Thời gian: Thứ 5 (08h00
Nẵng, 54 Nguyễn Lương - 12h00 và 13h30 -
Bằng, P. Hòa Khánh 17h30).
Bắc, Q. Liên Chiểu, TP.
Đà Nẵng.
• Thời gian: Thứ 3 (13h30
- 17h30) và Thứ 7
(13h30 - 17h30).

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Learning Methodology
Online Lectures via Zoom PD1 Zoom Information
Online Google Classroom
In-person Labs working on Cloud
Technology Integration

Increased Interaction
Assessment & Feedback

Seminars & Workshops

Google
Lectures + Labs Labs
Classroom
Mentorship
Pre-class Activities that
reinforce and Post-class
materials, videos,
apply the pre- materials, guided
or readings to
class learning practice lab
review before
2 sessions that
coming to class Group reinforce and
discussions, apply all learning
problem-solving Teachers are Facilitators Government, Academia, Industry
exercises Group Learnings,
Blended Course Group Projects,
Delivery Mode Hands-on Instructors are from Tresemi/USA, The course is organized by NIC, collaborating with
Group Q/As
projects currently working for FPT, Tresemi, and Cadence, with the support of DUT
PD1 Google Classroom other interactive Self Evaluation Skyworks, Silicon Labs, MediaTek, and and UIT | Students are from all regions of Vietnam |
Information tasks facilitated NXP TAs, Mentors are engineers, currently working for
by the instructors synchronous At least 25 years in the industry FPT, HCL, Qorvo, CoAsia, etc., or professors
Biographies teaching in universities in all regions
asynchronous synchronous asynchronous Flexibility
Images retrieved from Implementing a Flipped Classroom in Medical Education (Horneffer, 2020)

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What is Physical Design?

Market Research iPhone 15 Pro

Product
Development
Process
ASIC A17 Pro

System Testing

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ASIC Development Flow
(How a chip is built - simplified)
What does the chip do?
Market Research Marketing Requirement Document (MRD) How fast does it need to operate?
Specs

How much power will it consume?

How big will it be?
Chip Specification Product Requirement Document (PRD)
How much will it cost?
Front-End Design

Architectural Design Does the chip have all the required

Architectural Level functionalities?
Micro-architecture Design Is the design adequate for meeting
Register-Transfer
performance goals?
Level (RTL)
RTL Design

Does the chip meet all the required

Back-End Design

Logic Synthesis Gate Level performance specifications?

Circuit Design Transistor Level

Physical Design Physical Level Levels of Abstraction

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 Primary Goals of Physical Design

The primary goals of physical design encompass optimizing integrated circuits for superior
performance, minimizing power consumption, and efficient chip area utilization.

Reliability and
▪ PPA Optimization: finding the right Robustness:
balance among these 3 factors to PPARMP − Ensure proper functionality
achieve an optimal design for a under all operating
specific application or use case: More Powerful conditions and
− Performance environmental factors.
• Enhance overall processing Manufacturability:
capabilities. Longer Battery Life
• Meeting timing constraints. − Optimize the design for
manufacturability to improve
− Power Better Thermal the yield of the
• Minimize power consumption for manufacturing process.
extended battery life, reduced energy
costs, and effective thermal Less Expensive
Productivity:
management. − Achieve rapid closure of all
− Area design goals, contributing to
• Minimize chip area to enhance cost the successful delivery of
efficiency in mass production. high-quality ICs.

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IC Design History

1963 1971 - Intel 4004

• First Microprocessor
First MOS FET
• 10um process (10,000 nm)
• 2,300 transistors
• 750 KHz
• Busicom 141-PF Calculator

https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/

2023 - Apple A17 PRO

• 3nm process
• 19B transistors
• 3.78 GHz
• Apple iPhone 15

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Challenges

Complexity
System-on-Chip
System-in-Package Reliability, A17 Pro
Billions of Transistors Robustness Die Shot
< 3nm

Ultra High Speed Manufacturability,

Yield

Ultra Low Power

Productivity

Noise, Crosstalk

https://twitter.com/Frederic_Orange/status/1711432628908253520/photo/1

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Trends

2nm, 1nm, 3D

> 200B
Transistors https://spectrum.ieee.org/the-future-of-transistors

Monolithic

> 1T
Transistors
SiP Source: TSMC

Backside
Power

Disaggregated SoC SiP (chiplets)

3D IC (monolithic)
Backside Power – Source: Intel

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ASIC Design Principles

Addressing the VLSI

Challenges

Hierarchy

Regularity

Modularity

Locality

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Hierarchy

Hierarchy
▪ ‘Divide and conquer”
− Divide a system into modules,
Regularity
then repeating this process on
each module until the
Modularity
complexity of the submodules is
at an appropriately
Locality
comprehensible level of detail.
▪ Benefits:
− Modules can be designed and
verified in parallel.
− Modules can be reused in
multiple chips.

Radio Chip Hierarchy Example (CMOS VLSI Design – Weste-Harris)

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Regularity

Hierarchy
▪ Divide the design hierarchy
into a set of similar building
Regularity blocks.
▪ Regularity can exist at all
Modularity
hierarchical levels
− Standard cells: fixed-height,
Locality
variable-length logic gates
− Parameterized RAMs, ROMs
− Reusable modules (multipliers,
cores, etc.)
▪ Benefits:
− Reduce number of
subcomponents to design,
optimize, and verify.
− Components can be reused
Radio Chip Hierarchy Example (CMOS VLSI Design – Weste-Harris)
within the chip.

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Modularity

Hierarchy ▪ Break complex systems

into smaller, well-defined,
Regularity
and independent modules.
− Well-defined Functions
Modularity

− Well-defined Interfaces
Locality − Independence
− Ease of Design and
Maintenance
− Scalability and Reusability

An embedded SRAM module example

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Locality

▪ Organize and structure a design in a way that

emphasizes the proximity or closeness of
Hierarchy

Regularity
related components or operations.
− Spatial Locality: place related components close to
each other.
Modularity
− Temporal Locality: related operations or signals need
to be temporally close to meet timing requirements.
− Functional Locality: modules are designed with a
Locality

clear and specific function, and related functions or

operations should be grouped together within a
module.
A locality
− Communication Locality: organize the flow of data example, the
and control signals to minimize long-distance floorplan is
modified so
communication between components. that “Bus” is
− Power Locality: power-hungry components or regions shorter
should be located and managed for minimum power
dissipation.

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Design Abstraction
Divide-and-Conquer:
• Break the IC design problem down into levels of abstraction Abstraction
and address them in steps and in parallel by multiple
resources.
• A design are represented at various levels (Abstractions) A very effective means of dealing with design complexity:
from different angles (Domains) • Creating a model at a higher level of abstraction
• Abstraction = representation without details involves replacing detail at the lower level with
simplifications.

▪ Domains:
− Behavioral
− Structural
− Physical
▪ Levels of Abstraction
− Architectural
− Register-Transfer-Level (RTL)
− Logic
− Circuit

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Abstraction Levels

Abstraction
Levels

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Design Abstraction – Another View

Boolean Algebra
Behavioral
Binary Data • Boolean algebra and
Model
binary numbers serve
as powerful tools for
modeling the behavior
Functional of a system.
Model • They can be used to
craft sophisticated
circuits tailored to
implement precise
RTL Netlist Transistors as switches tasks or functions within
a network.

Gate-level
Binary Program
Netlist
0/1
True/False
010111001
Circuit

Low Voltage = Logic 0

Devices High Voltage = Logic 1

A transistor uses an
electric field to control
Physics the flow of current in a
semiconductor

Boolean Algebra

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Back-End Design Flow
Back-End

Logic Synthesis Gate-Level Netist

Does the chip meet all the
Design

required performance
Physical Design Physical Layout specifications?

DIVIDE & CONQUER

Logic Synthesis Physical Design

Does the Gate-level Design meet all the

Does the Final Design meet all the required
required performance specifications with
performance specifications?
estimated parasitics?

To the
Fab

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Terminologies

BACK-END DESIGN
DIGITAL IMPLEMENTATION

Logic Synthesis

Circuit Design
▪ Back-End Design = Digital Implementation =
PHYSICAL DESIGN Logic Synthesis + Physical Design
▪ Physical Design = Place & Route + Parasitic
Place & Route

Parasitic Extraction
Extraction + Sign-off

Sign-off

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Place and Route (P&R) Flow
• Read and check Import DB • Inputs are valid
Gate Level
Import quality of inputs • Constraints are complete
Netlist
• Design is routable
• Define Boundaries • IR drop is below limits
Cell Abstracts • Set up placement • Timing closure is feasible
areas for different
Floorplanning Floorplan DB
types of components
Timing • Create the Power • Design is routable
Constraints Distribution Structures • No timing violations
• Power consumption is minimized
Physical
Constraints
Placement • Place all components Placement DB • Clock trees are optimized
for timing and power
Inputs
Clock Tree Synthesis • Build the clock trees CTS DB • Design is free of design
rule errors
Routing • Route all signals Route DB • No timing violations
• IR drop is below limits
• Power is within budget
Gate Level Netlist • Design is reliable
• Design is manufacturable
Layout
Export • Write outputs
• Design is ready for
QoR Reports FAB
verification and then
Steps Outputs on to Manufacturing

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Pre-Class Materials

▪ Building a Chip
▪ The Chip Design Flow

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References

▪ CMOS VLSI Design – Weste-Harris ▪ asic back-end - https://usebackend.wordpress.com

▪ Digital Integrated Circuits – Jan Rabaey ▪ System-on-Chip Design – Anand Raghunathan
▪ 2011 Lecture Notes - David Money Harris ▪ Physical Design Flow – Mohammad Kakoee
▪ Digital VLSI Design – Adam Teman ▪ Team VLSI Blog – “teamvlsi.com”
▪ Principles of VLSI Design – Jim Plusquellic ▪ Cadence Online Support Site and YouTube Videos
▪ Digital Integrated Circuits – YuZhuo Fu ▪ Reliability of segmented edge seal ring for RF devices
- J. Gambino, et al.
▪ VLSI Back-End Adventure, ASIC Blog – “SoC
Physical Design” ▪ A Reliable I/O Ring For A Reliable SoC – Abdelliah
Bakhali
▪ VLSI Physical Design For Fresher –
“physicaldesign4u.com” ▪ Apply Wire bonding PBGA or Flip Chip PBGA? -
Fiona Zhang
▪ VLSI Begin… Blog - “vlsibegin.blogspot.com”
▪ Floorplan Strategies for Macro Dominating Blocks –
▪ SoC Physical Design – “physicaldesign- Team VLSI
asic.blogspot.com”
▪ Floorplan Guidelines for Sub-Micron Technology
▪ VLSI Expert – “vlsiexpert.com” Node for Networking Chips - Dhaval S. Shukla
▪ ASIC-System on Chip-VLSI Design – “asic- ▪ Internet search and many more…
soc.blogspot.com”
▪ From Logic to Layout – Rob Rutenbar

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About Tresemi

OUR MISSION

Founded in March 2024, Tresemi stands as a vibrant non-profit organization

headquartered in the United States, propelled by a clear mission: to foster the
next generation of leaders in the semiconductor industry and empower the
existing workforce. Our steadfast commitment to advancing the
semiconductor sector's workforce is reflected in our dedication to
educational, scientific, and charitable initiatives. What sets us apart is our
distinctive all-volunteer workforce—a community bound by a shared vision.

www.tresemi.org

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