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1 FSMDesignWithVerilog

electronic system level design course

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3 views18 pages

1 FSMDesignWithVerilog

electronic system level design course

Uploaded by

studentwelfare.cb2024
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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STATE MACHINE DESIGN

STATE MACHINES
(Sequential + Combinational )

❖ So far we have discussed only combinational and sequential


circuits in isolation.

❖ Combinational circuit modeling processes are sensitive to the


inputs, being activated when there is an event on an input signal.

❖ Sequential circuits retain information stored in internal devices


such as flip-flops and latches.

❖ The values stored in these devices are called the state of the
circuit.

❖ The values of the output signals can now be computed as


functions of their internal state and values of the input
signals.
STATE MACHINES
(Sequential + Combinational )

❖ The values of the state variables may also change as a function of


the input signals.

❖ These state variables are usually updated at discrete points in time


determined by a periodic signal (e.g. a clock).

❖ With a finite number of storage elements, the number of unique


States is finite.

❖ Such circuits are called FSMs (Finite State Machines).

(Concepts of Mealy/Moore machines.


Next state and output logic)
STATE MACHINES

Inputs Next
Next State Output
State Present State
State Memory Logic
Logic

Clock Input

Clocked Synchronous Moore state Machine


(The output depends only on present state)
STATE MACHINES

Next Outputs
Inputs Next State Output
State Present State
State Memory Logic
Logic

Clock Input

Clocked Synchronous Mealy state Machine


(The output depends on present state and input )
VERILOG DESIGN OF A MOORE STATE MACHINE
2 Bit Counter counting from 00 to 11
Rising
edge of
Clk
Reset

CNT0 CNT1 CNT2 CNT3

Rising Rising
edge of edge of
Rising
Clk Clk
edge of
Clk
// --------------------------------------------
//
// S T A T E M A C H I N E DESIGN OF A 2 BIT COUNTER
//
// --------------------------------------------
module state_machine(clk,reset,d_out);

parameter CNT0 = 2'b00;


parameter CNT1 = 2'b01;
parameter CNT2 = 2'b11;
parameter CNT3 = 2'b10;

input clk;
input reset;
output [1:0] d_out;
reg [1:0] current_state, next_state;

// State Transition at clock edge


always @ (posedge clock)
begin
if (reset == 1'b1)
current_state <= CNT 0; // Also can write <= 2'b00; but not good
else
current_state <= next_state;
end
// Next State and Output Logic

always @ (current_state)
begin

case (current_state)
CNT0:
next_state = CNT1; //
d_out = 1'b0; // What kind of a machine is this: Mealy or moore?

CNT1:
next_state = CNT2;
d_out = 2'b01;

CNT2:
next_state = CNT3;
d_out = 2'b10;

CNT3:
next_state = CNT0;
d_out = 2'b11;

endcase // Always check: Any latches? Any priority implied ?

end
endmodule
// --------------------------------------------
//
// Questions:
//
// --------------------------------------------

How will the counter Synthesize? What will it depend on?


Generally it is synthesized using D flip flops .
Check if your synthesized result match with your paper design.

Now! Let us try to design a 2 bit Up-down counter.

So what are the changes required ?

1) Extra input ( ‘mode’ = 0 => up, mode = 1 => down count)

2) Next state logic affected by this mode input. Need to check this
value before deciding next state

3) Draw the next state logic on paper and verify with the
Synthesized design
State Machine Design
Example: A Traffic Light Controller

TIMER2 TIMER3

RESET
(asynchronous)

TIMER1 TIMER2
RED GREEN YELLOW

R='1' Y='1'
TIMER1 G='1'

TIMER3
One Hot Encoding

• Uses n flip flops to represent state machine with n


states. Only one bit is ‘hot’ (‘1’) at a time.

• The previous example of the counter is NOT one hot


coding. The synthesizer would have used 2 bits to
represent 4 states (00,01,10,11). This is called
sequential encoding.

• To design the same counter using One hot encoding, we


require 4 bits to represent 4 states (0001, 0010, 0100,
1000) .
One Hot Encoding

• Decoding the state = extremely simple (just finding out which bit =
‘1’)
• Changing states = simply changing new flip flop to ‘1’ and old one to
‘0’;
• Advantages :
– Logic gates required for decoding state information and
changing state is minimal.
Disadvantages:
- Uses more flip flops/ registers.

USAGE: This is used when the implementation device has more


registers to use and little combinational logic between registers.
Typical used when system is to be implemented in to an FPGA.
One hot encoding Vs. Default Coding

parameter CNT0 = 4'b0001; parameter CNT0 = 2'b00;


parameter CNT1 = 4'b0010; parameter CNT1 = 2'b01;
parameter CNT2 = 4'b0100; parameter CNT2 = 2'b11;
parameter CNT3 = 4'b1000; parameter CNT3 = 2'b10;
REMEMBER

it is Very Important to Know

what your design is made up of.


What is in the inside of your Chip
KNOWLEDGE OF THE DAY

What do they have?

THESE ARE CHIPS They have ALU in them


THESE ARE ALSO They Also have ALU in
CHIPS them
For more detailed analysis of binary encoding, one hot encoding of
FSMs and for input synchronization to avoid metastability,
please refer

http://www.eetimes.com/document.asp?doc_id=1206481

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