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Lab report 4

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6 views

Lab report 4

Uploaded by

madnir99
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Layout Design of Inverter :

DRC and LVS Check

18 / 11/ 24

04
EE-20-A

Muhammad Raza Madni 210401034


Nafaye Bin Faisal 210401030
Arsalan Haider 210401027
Lab # 04
Objectives:
• To implement NOT gate schematic and Layout in Virtuoso.
• To perform DRC and LVS check on inverter.
Equipment:
• Laptop
• VMware Software
• Cadence virtuoso tool
Introduction :
In this section of the document, we will walk through how to physically layout the
final cell which is NOT Gate in our case. We will then check to make sure that the layout
confirms to all of the manufacturer’s rules (DRC), and finally we will make sure that the
layout yields a netlist which is equivalent to the netlist produced by the schematic editor
(LVS).
Layout:
By now, you should know how to enter a schematic, how to produce a corresponding
symbol for the cell, and finally how to simulate your design to make sure it functions
correctly. The next step in the process of making an integrated circuit (IC) is to perform the
physical layout of the cell. What is the layout? A layout is basically a drawing of the masks
from which your design will be fabricated. Therefore, layout is as critical as specifying the
parameters of your devices because it determines whether you will have a working design or
a flop! There are two approaches to doing layout: manual and automated. Manual layout
usually enables the designer to pack one’s devices in a smaller area compared to the
automated process, but it is much more tedious. The automated process, on the other hand, is
done using standard cells and usually takes more real estate, but it is much faster. In this
tutorial, you will learn how to perform MANUAL LAYOUTS ONLY and, specifically, the
layout of a simple inverter will be described. You will then be asked to lay out other cells for
which you have already completed the schematic entry process. You should know that for the
purposes of this course, you are primarily required to know how to create manual layouts,
although the Cadence tools can support either manual or automated layouts. In fact, later in
the semester we will experiment with the standard cell approach to layout. Before we start
the layout of our inverter, one needs to understand the importance of design rules. Design
rules give designers guidelines for generating layouts. They dictate the spacings between
wells, sizes of contacts, minimum spacing between a poly and a metal layer, and many other
similar things. Design rules are essential to any successful layout, since they account for the
various allowances that need to be given during actual fabrication and to account for the
sizes and the steps involved in generating masks for the final layout. Note that layout is very
much process-dependent since every process has a different fixed number of available masks
for layout and fabrication.
Lab Task
Layout Design of Inverter:
• Design schematic of inverter using NMOS and PMOS in Cadence virtuoso schematic
editor.
• Attach Input and Output Pins as shown in the below schematic

• Set VDD and VSS state to high and low.

• For an error-free schematic, that has only PDK elements and IO pins, open virtuoso
schematic editor. In the schematic editor window go to Layout XL>. A “Startup
Option” window will open. For ‘Layout’ select Create New and for ‘Configuration’
select Automatic and press OK. A “New File” window will open. Make sure that the
cell name corresponds to your schematic name, and the view is set to be layout, and
press OK.
• In this step you will be generating the layout of sub-cells used in building your cell. In
the case of an inverter, the generated sub-cells are 1 NMOS, 1 PMOS, and 4 IO pins.
You can instantiate these sub-cells like what you did before in the schematic editor.
Another way is to ask for virtuoso’s assistance in generating the sub-cells. In the
layout editor, go to Generate -> All from Source>. The “Generate Layout” window
will open.
Procedure:
1. Press “ Shift+f”, select mosfet and press Q.
2. Select parameter->bodytie type ->Detached, select “Top Tap” for pmos and “Bottom
Tap” for nmos, as shown

3. Connect the wires as shown.


4. Make sure to connect wires properly
5. Now, go to Assura-> Run DRC-> technology= gpdk090.
6. If no error occurs, then proceed to the following step.

7. Now, go to Assura-> Run LVS-> technology= gpdk090.


8. If no error occurs, then your layout is ready.

Observations:
In this lab we learned to design a layout for CMOS inverter. While designing this layout we
must be very careful with the wiring to make sure to connect them properly if there is slight
difference in connection it will give error.

…the end!

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