ANIL SINGH ECE DEPARTMENT.

MICROPROCESSOR & MICROCONTROLLER

UNIT-IV
8051 MICROCONTROLLERS Comparisons of Microcontroller and
1 INTRODUCTION: Microprocessor:
• The 8051 is an 8-bit microcontroller with 8 Microprocessor Microcontroller
bit data bus and 16-bit address bus. A microprocessor is a A microcontroller is a
general-purpose device dedicated chip which is also
• The 16-bit address bus can address a 64K which is called a CPU called single chip computer.
(216) byte code memory space and a A microprocessor does not A microcontroller includes
separate 64K byte of data memory space. contain on chip I/O Ports, RAM, ROM, serial and
• The 8051 has 4K on-chip read only code Timers, Memories etc. parallel interface, timers,
interrupt circuitry (in
memory and 128 bytes of internal Random
addition to CPU) in a single
Access Memory (RAM) chip
• Besides internal RAM, the 8051 has various Microprocessors are most Microcontrollers are used in
Special Function Registers (SFR) such as commonly used as the CPU small, minimum component
the Accumulator, the B register, and many in microcomputer systems designs performing control-
oriented applications.
other control registers.
Microprocessor instructions Microcontroller instructions
• 34 8-bit general purpose registers in total. are mainly nibble or byte are both bit addressable as
• The ALU performs one 8-bit operation at a addressable. well as byte addressable.
time. Microprocessor based Microprocessor based
• Two 16 bit /Counter timers system design is complex system design is complex
and expensive and expensive
• 3 internal interrupts (one serial), 2 The Instruction set of The instruction set of a
external interrupts. microprocessors is complex Microcontroller is very
• Four 8-bit I/O ports with large number of simple with a smaller
• Some 8051 chips come with UART for instructions. number of instructions. For,
ex: PIC microcontrollers
serial communication and ADC for analog
have only 35 instructions.
to digital Conversion A microprocessor has zero A microcontroller has no
SELECTION OF MICROCONTROLLERS: status flag. zero flag
The three criteria in choosing microcontrollers Microcontroller
are as follows
1. Microcontroller must perform the required task
efficiently & cost effectively i.e.
• Speed
• Amount of RAM & ROM on chip
• Power consumption
• The number of input pins & the timer on
the chip
• Cost per unit Microprocessor
• Easy to upgrade
• Packaging (The number of pins & the
packaging format. This determines the
required space & assembly layout.)
2. Availability of assembler, debuggers, complier,
emulator, technical support and expertise both in-
house and outside.
3. Microcontroller availability in needed
quantities both now and in the future.

BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

1
 ANIL SINGH ECE DEPARTMENT.
PIN DIAGRAM OF 8051 i.e. addresses A8-A15 will appear on this port.
Even though memory with capacity of 64Kb is not
used, which means that not all eight port bits are
used for its addressing, the rest of them are not
available as inputs/outputs.
Pin 29: PSEN’- Program Store Enable. If external
ROM is used for storing program, then a logic
zero(0) appears on it every time the
microcontroller reads a byte from memory.
Pin 30: ALE – Address latch enable
1 – Address on AD 0 to AD 7
0 – Data on AD 0 to AD 7
Pin 31: EA’ – it indicates the presence of external
memory
Pin 32-39: Port 0 Similar to P2.
Pin 40: VCC → +5V power supply.
RISC AND CISC CPU ARCHITECTURES
• Microcontrollers with small instruction set
are called reduced instruction set
computer (RISC) machines and those with
Pin out Description: complex instruction set are called complex
Pins 1-8: Port 1 Each of these pins can be instruction set computer (CISC).
configured as an input or an output. • Intel 8051 is an example of CISC machine
Pin 9: RST A logic one on this pin disables the whereas microchip PIC 18F87X is an
microcontroller and clears the contents of most example of RISC machine.
registers. In other words, the positive voltage on RISC CISC
this pin resets the microcontroller. By applying Instruction takes one or Instruction takes
logic zero to this pin, the program starts execution two cycles multiple cycles
from the beginning. Only load/store In additions to load and
Pins10-17: Port 3 Similar to port 1, each of these instructions are used to store instructions,
pins can serve as general input or output. Besides, access memory memory access is
all of them have alternative functions: possible with other
Pin10: RXD Serial asynchronous communication instructions also.
input or Serial synchronous communication Instructions executed Instructions executed
output. by hardware by the micro program
Pin11: TXD Serial asynchronous communication Fixed format Variable format
output or Serial synchronous communication instruction instructions
clock output Few addressing modes Many addressing modes
Pin 12: INT0 Interrupt 0 inputs. Few instructions Complex instruction set
Pin 13: INT1 Interrupt 1 input. Most of the have Single register bank
Pin 14: T0 Counter 0 clock input. multiple register banks
Pin 15: T1 Counter 1 clock input. Highly pipelined Less pipelined
Pin 16: WR Write to external (additional) RAM. Complexity is in the Complexity in the
Pin 17: RD Read from external RAM. compiler microprogram
Pin 18, 19: XTAL2/XTALI is for oscillator input FUNCTIONAL BLOCK DIAGRAM OF 8051
Pin 20: GND-Ground. MICROCONTROLLER
Pin 21-28: Port 2- If there is no intention to use • The Intel 8051 contains two separate
external memory then these port pins are buses for both program and data. So, it has
configured as general inputs/outputs. In case two distinctive memory spaces of 64K x 8
external memory is used, the higher address byte, size for both program and data.
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

2
 ANIL SINGH ECE DEPARTMENT.

• It is based on an 8-bit central processing

unit with an 8-bit accumulator and
another 8-bit B register as main
processing blocks.
• Other portions of the architecture include
few 8 bit and 16bit registers and 8-bit Accumulator
memory locations. • The accumulator register (ACC or A) act as
• It has some amount of data RAM built in an operand register, in case of some
the device for internal processing. This instructions.
area is used for stack operations and • This may either be implicit or specified in
temporary storage of data. the instruction.
• 8051 is supported with on-chip peripheral • The ACC register has been allotted on
functions like I/O ports, Timers/ Counters, address in the on-chip special function
Serial communication port. register bank
• The CPU is the brain of the Program status word (PSW)
microcontrollers expected task reading This set of flags contains the status information
user's programs and executing the as per and is considered as one of the special function
instructions stored there in. registers.
• Its primary elements are an Accumulator D7 D6 D5 D4 D3 D2 D1 D0
(AC), Stack Pointer (SP) Program Counter PSW.7 PSW.7 PSW.7 PSW.7 PSW.7 PSW.7 PSW.7 PSW.7
(PC), Program Status Word (PSW), Data CY AC FO RS1 RS0 OV --- P
Pointer (DTPR) and few more 8-bit PSW.0 : CY: Carry Flag
register. PSW.1 : --- : User Definable Flag
PSW.2 : OV: Overflow Flag
ARITHMETIC OF 8051 PSW.3 : RS0: Register Bank Select Bit 0
LOGIC UNIT (ALU) PSW.4 : RS1: Register Bank Select Bit 1
• The arithmetic / logic unit performs the The bits PSW.3 and PSW.4 are denoted as RS0 and
computing functions; it includes the RS1. These bits are used to select the bank register
accumulator, temporary register, of the RAM location.
arithmetic and logic circuits. RS1 RS0 Register bank Address
• The temporary register is used to hold 0 0 0 00H - 07H
data during an arithmetic / logic 0 1 1 08H - OFH
operation. 1 0 2 10H - 17H
• result is stored in the accumulator register. 1 1 3 18H - 1FH
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

3
 ANIL SINGH ECE DEPARTMENT.
PSW.5 : FO: Flag 0 available for general purpose • The serial data buffer is identified as SBUF and
PSW.6 : AC: Auxiliary Carry Flag is one of the special function registers
PSW.7 : CY: Carry Flag Timer register
• These two 16-bit register can be accessed as the
Stack pointer (SP) lower and upper bytes.
• This 8-bit register is incremented before the • For examples, TL0 represents the lower byte of
data is stored onto the stack using PUSH or CALL the timing register 0, while TH0 represents the
instructions. upper byte of the timing register 0.
• This register contains 8-bit stack top address. • Similarly, TL1 and TH1 represent lower and
The stack may be defined anywhere in the on-chip higher byte of the timing register 1.
128-byte RAM. After reset, the SP register is • All these registers an be accessed using the four
initialized to 07. addresses allotted to them which lie in the special
• After each write two stack operation, the 8-bit function register (SFR) address range, i.e.,80Hto
contents of the operand are stored onto the stack, FF.
after incrementing the SP register by 1. Control register
• Thus, if SP contains 07H, the forthcoming PUSH • The special function register IP, IE, TMOD,
operation will store the date at address 08H in the TCON, SCON and PCON contain control and status
internal RAM. information for interrupts, Timer / Counters and
• The SP content will be incremented to 08.the serial port.
8051 stack is not a top-down data structure, like • All of the registers have been allotted addresses
other Intel processors. in the special function register bank of 8051.
• This register has also been allotted on address in Timing and control unit
the especial function register bank. • This unit derives all the necessary timing and
Data pointer (DTPR) control signals recovered for the internal
• This 16-bit register contains a higher byte operation of the circuit.
(DPH) and the lower byte (DPL) of a 16-bit • It also derives control signals recovered for
external data RAM address. controlling the system bus.
• It is accessed as a 16-bit register or two 8-bit Oscillator
registers as specified above. It has been allotted to This circuit generates the basic timing clock
two address in the special function register bank, signal for the operation of the circuit using crystal
for its two bytes DPH and DPL. oscillator
Port 0 to 3 laches and drives Instruction register
• This four latches and driver pairs are allotted to This register decodes the Opcode of an instruction
each of the four on-chip I/O ports. to be executed and gives information to the timing
• These latches have been allotted address in the and control unit to generate necessary signal for
especial function register bank. the execution of the instruction.
• Using the allotted addresses, the users can EPROM and Program Address Register
communicate with these ports. These are This block provides an on-chip EPROM and a
identified as P0, P1 and P3. mechanism to internally address it. (Note that
Serial data buffer EPROM is not available in all versions of 8051).
• The serial data buffer internally contains two RAM and RAM
independent registers. Address Register These blocks provide internal
• One of them is a transmit buffer which is 128 bytes of RAM and a mechanism to address it
necessarily a parallel–in serial–out (PISO) internally.
register. SFR (Special Function Register) Register Bank
• The other is called receive buffer which is a • This is a set of special function registers, which
serial–in parallel–out (SIPO) register. can be addressed using their respective addresses
• Loading a byte to the transmit buffer initiates which lie in the range 80H to FFH.
serial transmission of that byte.

BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

4
 ANIL SINGH ECE DEPARTMENT.
• Finally, the interrupt, serial port and timer 3. Direct Addressing Mode
units’ control and perform their specific function • In the direct addressing mode, all 128
under the control of the timing and control unit. bytes of internal RAM and the SFRs may be
addressed directly using the single-byte
ADDRESSING MODES OF 8051 addressing need to each RAM location and
The addressing Modes are the ways of accessing each SFR.
data in register or in memory or be provided as an • Internal RAM uses address from 00H to
immediate value. The 8051 mnemonics are 7FH to address each byte. The SFR
written with the destination address named first. addresses exist from 80H to FFH.
followed by the source address. The following ▪ MOV R3, 62H R3 ← Data of Address 62H
addressing modes are used to access data: ▪ MOV 6FH, A 6FH(On Address) ← A
1. Immediate addressing mode 4. Register Indirect Addressing Mode
2. Register addressing mode • In this mode a register is used as a pointer to
3. Direct addressing mode the data. If the data is inside the CPU, only
4. Register indirect addressing mode registers R0 and Rl are used for this purpose.
5. Indexed addressing mode. • When R0 and Rl hold the addresses of RAM
1. Immediate Addressing Mode locations they must be preceded by the "@"
• When a source operand is a constant sign.
rather than a variable, then the constant Examples:
can be embedded into the instruction itself. ▪ MOV @ R1, A:
• This kind of instructions takes two bytes Move contents of A into RAM
location whose address is
and first one specifies the Opcode and held by R1.
second byte gives the required constant. ▪ MOV B, @ R0:
• The operand comes immediately after the Move contents of RAM
Opcode. The mnemonic for immediate data location whose address is
is the pound sign (#). held by R0 into B
• This addressing mode can be used to load 5. Indexed Addressing Mode
information into any of the registers • Only the program memory can be accessed by
including DPTR register. this mode. This mode is intended for reading
Examples: lookup tables in the program memory.
▪ MOV A, # 18H A ← 18H • A 16-bit base registers (DPTR or PC) points to
▪ MOV A, # 64H A ← 64H the base of the lookup tables and accumulator
▪ MOV DPTR, # 2040H DPL ← 40H carries the constant indicating table entry
DPH ← 20H number. The adder
2. Register Addressing Mode • ess of the exact location of the table is formed
• Register addressing accesses the eight by adding the accumulator data to the base
working registers (R0 - R7) of the selected pointer.
register bank. Example:
• The least significant three bits of the ▪ MOVC A, @A+ DPTR:
instruction opcode indicate which register The contents of A are added to the
is to be used for the operation. DPTR to form the 16-bit address
of the needed data. 'C' means
• One of the four banks of registers is to be code.
predefined in the PSW before using INTERRUPTS
register addressing instruction.
An interrupt is an internal or external event that
• ACC, B and DPTR can also be addressed in interrupts the microcontroller to inform it that a
this mode. device needs its service. Whenever any device
Examples: needs its service, the device notifies the
▪ MOV A, R3 A ← R3
microcontroller by sending it as interrupt signal.
▪ MOV R0, A R0 ← A
Upon receiving an interrupt signal, the
▪ ADD A, R0 A ← A+ R0
microcontroller interrupts whatever it is doing
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

5
 ANIL SINGH ECE DEPARTMENT.
and serves the device. The program which is • The flag is cleared to 0 when the resulting
associated with the interrupt is called interrupt interrupt generates a program call to the
Service Routine (ISR). The microcontroller can appropriate timer subroutine in memory.
serve many devices based on the priority assigned 2.External interrupts
to it. • The external hardware interrupts INT0
Execution of an Interrupt andINT1 are located on pins P3.2 and
In order to use any interrupt, the following steps P3.3.
must be taken. • Inputs on these pins can set the interrupt
1. It finishes the instruction it is executing flags IE0 and IE1 in the TCON register to 1
and saves the address of the next by level triggering or edge-triggering.
instruction (PC) on the stack.
2. It also saves the current status of all the
interrupts internally.
3. It jumps to a fixed location in memory
called the interrupt vector or table that
holds the address of the Interrupt Service
Routine (ISR).
4. The microcontroller gets the address of the
ISR from the interrupt vector table and
jumps to it. It starts to execute the
interrupt service subroutine until it
reaches the last instruction of the
subroutine which is RET 1.
5. Upon executing RET 1 instruction, the
microcontroller returns to the place where
3. Serial Port Interrupt
it was interrupted. First it gets the
program counter (PC) address from the • In SCON, if RI = l, a data byte is received If
stack by popping the top two byes of the TI = 1, a data byte has been transmitted.
stack into the PC. Then it starts to execute • These are ORed together to provide a
from that address. single interrupt to the processor.
Interrupts PIN in 8051 • The interrupt bit in the IE register is used
Five interrupts are provided in the 805l. to both send and receive data.
• Three of these a regenerated by internal • If IE.4 [ES- Enable serial port interrupt] is
operations: Timer Flag 1 & 0, and the enabled, when RI or TI is raised and
serial port interrupt (RI or TI). 8051gets interrupted and jumps to
• Two interrupts are triggered by external memory address location 0023H to execute
signals provided by circuitry that is the ISR.
connected to pin INT0’ and INT1’ (port • The Fig.6.Showsthe serial interrupt is
pins P3.2 and P3.3) invoke by TI or RI flags.
Types PIN Interrupt Vector
Address
Internal TF0 Timer flag 0 interrupt 000𝐵𝐻
TF1 Timer flag 1 interrupt 001𝐵𝐻
RI/TI Serial port interrupt 0023𝐻 INTERRUPT CONTROL
External INT’0 External interrupt 0 0003𝐻 All interrupt functions are under the control of
INT’1 External interrupt 1 0013𝐻 the program. The programmer is able to alter
1.Timer flag interrupts control bits in the:
• When a timer / counter overflows, the • Interrupt Enable Register (IE)
corresponding timer flag TF0 or TFI • Interrupt Priority Register (IP) and
(location: 000B H or 001B H) is set to l. • Timer Control Register (TCON).

BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

6
 ANIL SINGH ECE DEPARTMENT.
Interrupt Enable Register (IE) 7 6 5 4 3 2 1 0
• The IE register holds the programmable PS PT1 PX1 PT0 PX0
bits that can enable or disable all the
interrupts.
• Bit D7 of the IE register (EA) must be set PX0- External Interrupt 0 priority level (IE0)
high to allow the rest of the register to PT0- Timer 0 Interrupt priority level (TF0)
take effect. PX1- External Interrupt 1 priority level (IE1)
PT1- Timer 1 Interrupt priority level (TF1)
• If EA = l, interrupts are enabled and will be
PS --Serial port Interrupt priority level (RI/T)
responded to if their corresponding bits in
IE are high.
• If EA = 0, no interrupt will be responded to, MEMORY ORGANISATION:
even if the associated bit in the EI register • The 8051 has a separate memory space for
is high. programs (Code) and data.
D7 D6 D5 D4 D3 D2 D1 D0 • Program memory stores the programs to
EA ES ET1 EX1 ET0 EX0 be executed, while data memory stores the
data like intermediate results, variable and
constants required for the execution of the
EA: Enable interrupts bits. program
• Set to 1 to permit individual interrupts to
be enabled by their enable bits.
• Cleared to 0 by program to disable all
interrupts.
ES: Enable serial port interrupt.
• Set to 1 to enable by program.
• Cleared to 0 to disable serial port
interrupt.
ET1: Enable/ disable the Timer 1 overflow
interrupt.
EX1: Enable external interrupt 1
• Set to 1 by program to enable INT1’
interrupt.
External Program (Code) Memory
• Cleared to 0 to disable INT1’ interrupt.
• The executable program is stored in this
ET0: Enable / disable the Timer 0 overflow
code memory.
interrupt.
EX0: Enable/ disable the external interrupt 0. • The code memory size is limited to
64KBytes (in a standard 8051).
• Set to 1 by program to enable INT0’
interrupt. • The code memory is read-only in normal
operation and is programmed under
• Cleared to 0 to disable INT0’ interrupt.
special conditions. e.g. it is a PROM or a
Interrupt Priority Register (IP)
Flash RAM type of memory.
• Interrupt priority (IP) register determines
External RAM Data Memory
the interrupt priority.
This is read-write memory and is available for
• Bits in IP registers set to 1 give the
storage of data. Up to 64KBytes of external RAM
accompanying interrupt a high priority; a
data memory is supported (in a standard 8051).
0 assigns a low priority.
Internal Memory
• Interrupts with a high priority can The 8051’s on-chip memory consists of 256
interrupt another interrupt with a lower memory bytes organized as follows: The first 128
priority and the lower priority continues bytes of internal memory is organized as shown in
after the higher is finished. figure, and is referred to as Internal RAM, or IRAM
• If two interrupts with the same priority
occur at the same time, then they have the
following ranking:
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

7
 ANIL SINGH ECE DEPARTMENT.

SFR Registers
• The SFR registers are located within the
Internal Memory in the address range 80h
to FFh, as shown in figure 3.
Register Banks: 00h to 1Fh • Each SFR has a very specific function.
• The 8051 uses 8 general-purpose registers • Each SFR has an address (within the range
R0 through R7 (R0, R1, R2, R3, R4, R5, R6, 80h to FFh) and a name which reflects the
and R7). purpose of the SFR.
• These registers are used in instructions • Although 128 byes of the SFR address
such as: space is defined only 21 SFR registers are
defined in the standard 8051.
• ADD A, R2 ; adds the value contained in R2
to the accumulator • Note some of the SFR registers are bit
Bit Addressable RAM: 20h to 2Fh addressable. SFRs are accessed just like
normal Internal RAM locations.
• The 8051 supports a special feature which
allows access to bit variables.
• This is where individual memory bits in
Internal RAM can be set or cleared.
• In all there are 128 bits numbered 00h to
7Fh.
• A bit variable can be set with a command
such as SETB and cleared with a command
such as CLR.
General Purpose RAM: 30h to 7Fh
• These 80 bytes of Internal RAM memory
are available for general-purpose data
storage.
• Access to this area of memory is fast
compared to access to the main memory
and special instructions with single byte
operands are used.
• However, these 80 bytes are used by the
system stack and in practice little space is
left for general storage.
• The general-purpose RAM can be accessed
using direct or indirect addressing modes.
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

8
 ANIL SINGH ECE DEPARTMENT.
Timer/Counters
• The 8051 has two 16-bit timer/counters.
These two timer/counters can be
programmed independently.
• There is a bit in the TMOD SFR that
specifies whether it is a timer or a counter.
• If this bit is set, the timer/counter will
work as a counter; and
• if this bit is reset, the timer/counter will
work as a timer. Case 1: TR0 = 1 (high)
• Gate = 0 (low)
TIMER MODE INT0= 0 (low)
• When a timer/counter is functioning as a Case 2 : TRO = 1 (high)
timer, the timer register (TH 1 and/or TL1 INTO = 1 (high)
for Timer 1 or TH0 and/or TL0 for Timer Gate = 1 (high)
0) is incremented after every machine Mode 0 for both the timer/counters is the same,
cycle. the only thing to do is to change TR0 to TR1, INT0’
• That is, it will be working at 1/12th of the to INTl’, and Gate bit for Timer 0 to Gate bit for
oscillator frequency because each machine Timer 1.
cycle has got 12 oscillator periods. Mode 1:
• As an example, after starting the spin This mode (Figure) is similar to mode 0, except
motor in a washing machine, the next that in this, 16 bits, that is, full TL0 and TH0 for
operation, i.e. the motor shut down, is Timer 0 (or TLl andTH1 for Timer 1) are used for
performed after a fixed time interval. counting. So, the interrupt flag will be set only
Function of Timer Modes: when the 16 bits go from all 1s to all 0s.
These timers can function in four different modes,
namely:
i) Mode 0,
ii) Mode 2,
iii) Mode 1,
iv) Mode 3.
• These modes are achieved by setting
certain bits in the TMOD-register.
• Mode 0 to mode 2 are common for both the
timers but not mode 3
Mode 2:
Mode 0:
• In this mode, the timer register is 8 bits
• In this mode, TL0and TH0 for Timer 0 (or
wide. TL0 for Timer 0 (or TLl for Timer 1)
TLl and THl for Timer 1) are used as a 13-
is used for this purpose (Figure).
bit register,
• This mode is also called the auto-reload
• i.e. all the 8 bits of the TL0 or TLl are
mode as the timer generates an interrupt
utilized and the five lower most bits of the
on overflow and after generating the
TH0 or THl are used for counting purposes.
interrupt, will also reload the present
• As the count rolls over from all 1s in the value from TH0 into TL0. This present
register to all 0s, the interrupt flag is set. value can be put in the TH0 through
• This timer interrupt flag is a bit, namely software.
TF0 (for Timer 0) in the TCON, which is a • The interrupt flag is set when TL0 goes
special function register. from all 1s to all 0s. After generating an
• From Figure, it is clear that if C/T = 0, then interrupt, it also reloads the TL0 with the
the register is incremented after every
machine cycle.
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

9
 ANIL SINGH ECE DEPARTMENT.
value from TH0 (80H in this case) and then M1 M0 MODE Deception
starts counting again. 13- Bit Counter
0 0 0
0 1 1 16- Bit Counter
1 0 2 8- Bit Counter with autoload
1 1 3 Slip timer 0 into two 8- Bit Counter or
to stop timer
•If C/T = 1, the timers function as counters
to count the negative transitions' at T0 or
T1 pins,
Mode 3: • If C/T= 0, the timers function as timers,
that is, they basically count the number of
machine cycles.
• Gate = 0 means that the timer is
controlled by TR1 or TR0 only, irrespective
of INT0’ or INT1’.
• Gate = 1 means that the timer control will
depend on INT0’or INT1’ and also on TR0
or TR1 bits.
2. TCON: Timer Control Register
7 6 5 4 3 2 1 0
• "If the Timer 0 is put into mode 3 (Figure),
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
then it acts as two 8-bit counters (TL0 and
TH0 become two separate counters).
•
TF 1: Timer 1 overflow flag. Set by
• In this case, all the Timer 0 control bits (C
hardware when the timer/counter
/ T’, Gate, TRO, TFO and INT0’) are used by
overflows. Cleared by hardware when the
TL0 itself and TH0 register is locked into a
processor vectors to the interrupt routine.
timer function.
• TR1: Timer 1 run control bit. Set/cleared
• TH0 is counting machine cycles and has
by software to turn the timer/counter
taken over the use of TRl and TFl from
on/off.
Timer 1.
• TF0: Timer 0 overflow flag. Set by
• Therefore, TH0 will now control Timer 1
hardware when the timer/counter
interrupt. If the Timer 1 is put into mode 3,
overflows. Cleared by hardware when the
it just holds the count.
processor vectors to the interrupt routine.
• The effect is same as setting TRI = 0, hence
• TR0: Timer 0 run control bit. Set/cleared
opening the switch.
by software to turn the timer/counter
TIMER CONTROL AND STATUS on/off.
REGISTER: SPECIAL FUNCTION • IE1: Interrupt 1 edge flag. Set by hardware
REGISTER. when the external interrupt edge is
• The special function registers TMOD and Detected. Cleared when the interrupt is
TCON are used to control the processed.
timer/counter functions. • IT1: Interrupt 1 type control bit.
• When we write into these registers, the Set/cleared by software to specify the
data is latched into them and takes effect falling edge/low level triggered external
atS1P1 of the next instruction (first cycle). interrupts. When IT1 = 1 then INTl’ is
1. TMOD: Timer Mode Control Register falling edge triggered, otherwise when IT1
= 0 the INT1’ is low-level triggered.
• IE0: Interrupt 0 edge flag. Set by hardware
when the external interrupt edge is
detected. Cleared when the interrupt is
processed.
BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

10
 ANIL SINGH ECE DEPARTMENT.
• IT0: Interrupt 0 type control bit. Power Mode Control (PCON) Special
Set/cleared by software to specify the Function Register
falling edge/low level triggered external PCON Special function register is not bit
interrupts. When IT0 = 1 then INT0’ is addressable. The functions of each bit in PCON
falling edge triggered, otherwise when IT0 register are as follows
= 0 the INT0’ is low-level triggered.
7 6 5 4 3 2 1 0
SCON (Serial Control) Special Function SMOD -- -- --- GF1 GF0 PD IDL
Register. PCON.0 - (IDL) Idle mode bit.
This register SCON controls the serial data PCON.1- (PD) Power down bit. This bit is used as
communication. It is an 8-bit register and bit handshaking signal to other processors connected
addressable. The address of this register is 98H. to 8051. Set to 1 by program to enter power down
7 6 5 4 3 2 1 0 configuration for CHMOS processors.
SM0 SM1 SM2 REN TB8 RB8 TI RI PCON.2 - (GFO) General purpose user flag 0. As
per requirement of the programmer, this bit can
SCON.0 (RI)Receive interrupt flag. be either set or cleared in program.
This interrupt flag is set to 1 when SBUF receives PCON.3 - (GF1) General purpose user flag 1. As
the stop bit. RI flag should be cleared by the per requirement of the programmer, this bit can
programmer. be either set or cleared in program.
SCON.1 TI (Transmit interrupt flag). PCON.4 - 6 Not used
This flag is raised to 1 when SBUF transmits stop PCON.7 - (SMOD) Serial mode baud rate bit. Set
bit. This flag also not cleared by ISR and to be to 0 by program to use the baud rate set by timer
cleared by the programmer. 1. Set to 1 by program the timer 1 baud rate is
SCON.2 RB8(Received bit 8). doubled for mode 1,2 and 3.
This bit is not used in mode0. in mode 1 the stop I /O PORTS
bit is set this bit and in mode 2 & 3 bit 8. Each port of 8051 has bi-directional capability.
SCON.3 TB8(Transmit bit 8). Port 0 is called 'true bidirectional port' as it floats
This bit is not used in mode 0&1. In mode 2&3 this (tri-stated) when configured as input. Port-1, 2, 3
bit is set/cleared by the programmer when the bit are called 'quasi bidirectional port'.
8 is transmitted. • To communicate data with the external
SCON.4 REN (Receive Enable). world the microcontroller needs ports.
Set to 1 this bit enables the serial reception. To • The ports may support either parallel or
disable reception, set to 0. serial data transfer.
SCON.5 SM2 (Multi processor communication • It has 4 I/O ports namely, Port 0, Port 1,
bit): Port 2 & Port 3
This bit is used for multi-processor • Port 1: is exclusively for input & output
communications in mode 2 & 3. functions.
SCON.6 & SCON.7 SM0 & SM1(Serial mode • Port 0, 2 & 3: perform functions other
bits): than parallel data transfer.
Set/Cleared to select serial mode. The selection of • All 4 ports are bidirectional.
modes are as follows,
• The 8 port pins are connected through 8 D
type port latches.
SM0 SM1 Mode Description PORT 0:
0 0 0 SBUF used as shift register • Port -0 has 8 pins (P0.0-P0.7).
0 1 1 Variable baud, 8-bit UART
• Port-0 can be configured as a normal
1 0 2 baud = f/32 or f/64, 9-bit bidirectional I/O port or it can be used for
UART Address / data interfacing for accessing
1 1 3 baud rate variable, 9- bit external memory. When control is '1', the
UART port is used for address/data interfacing.

BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

11
 ANIL SINGH ECE DEPARTMENT.
When the control is '0', the port can be • Here again due to internal pull-up there is
used as a normal bi-directional I/O port. limited current driving capability
• Port-0 latch is written to with 1's when
used for external memory access.

PORT 3:
• Port-3 has 8 pins (P3.0-P3.7)
Port 1: • Port-3 pins have alternate functions.
• Port-1 has 8 pins (P1.1-P1.7) • Each pin of Port-3 can be individually
• Port-1 does not have any alternate programmed for I/O operation or for
function i.e. it is dedicated solely for I/O alternate function.
interfacing. • The alternate function can be activated
• When used as output port, the pin is pulled only if the corresponding latch has been
up or down through internal pull-up. written to '1'.
• To use port-1 as input port, '1' has to be • To use the port as input port, '1' should be
written to the latch. In this input mode written.
when '1' is written to the pin by the
external device then it read fine.
• But when '0' is written to the pin by the
external device then the external source
must sink current due to internal pull-up.
• If the external device is not able to sink the
current the pin voltage may rise, leading to
a possible wrong reading.

Port 2 :
• Port-2 has 8-pins (P2.0-P2.7)
• Port-2 is used for higher external address
byte or a normal input/output port.
• The I/O operation is similar to Port-1.
Port-2 latch remains stable when Port-2
pin are used for external memory access.

BUDDHA INSTITUTE OF TECHNOLOGY GORAKHPUR

12