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LPC29xx ARM9 microcontroller with CAN and LIN

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Rev. 00.06 — 17 December 2008 User manual

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Document information
Info Content
Keywords LPC2917/01; LPC2919/01; LPC2927; LPC2929; LPC2921; LPC2923;
LPC2925; LPC2930; LPC2939 User Manual, ARM9, CAN, LIN
Abstract This document extends the LPC29xx data sheets with additional details to
support both hardware and software development. It focuses on functional
description and typical application use.
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LPC29xx

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Revision history

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Rev Date Description

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00.06 <tbd>

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Modifications:

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CGU chapter updated with description of CGU1 and internal base clocks.

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SCU chapter: description of SFSP_5_18/18, SEC_DIS, and SEC_STA registers

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added.
• RGU chapter updated.
• PMU chapter updated.
• CFID chapter added.
• Flash/EEPROM chapter updated.
• Parts LPC2921/23/25, LPC2930, and LPC2939 added.
• CGU0 PLL input clock frequency restricted to <= 25 MHz.
• UART modem control and RS485 control registers added.
• I2C pin description and pin usage updated.
• Numerous editorial updates throughout the manual.
• USB host chapter added.
• GPDMA connections updated. GPDMA is not connected to the I2C.
Memory-to-memory transactions are enabled for timers, GPIOs, and WDT.
• List of external pins to event router updated.
• PMU chapter, BASE_STAT register updated.
• USB OTG chapter: dual USB port added (LPC2930/39).
00.05 <tbd> Initial version

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UM10316_0 © NXP B.V. 2008. All rights reserved.

User manual Rev. 00.06 — 17 December 2008 2 of 571

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1. Introduction

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The LPC29xx combine an 125 MHz ARM968E-S CPU core, Full Speed USB 2.0 OTG

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and device, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory

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interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip
targeted at consumer, industrial, medical, and communication. To optimize system power
consumption, the LPC29xx has a very flexible Clock Generation Unit (CGU) that provides
dynamic clock gating and scaling.

2. About this user manual

This document describes the following parts: LPC2917/01, LPC2919/01, LPC2921,
LPC2923, LPC2925, LPC2927, LPC2929, LPC2930, and LPC2939. Differences between
the various parts as they apply to each block or peripheral are listed at the beginning of
each chapter. For an overview of features see Table 1–2.

3. General features
Remark: See Table 1–2 for feature details for each LPC29xx part.

• ARM968E-S processor running at frequencies of up to 125 MHz maximum.

• Multi-layer AHB system bus at 125 MHz with four separate layers.
• On-chip memory:
– Two Tightly Coupled Memories (TCM), up to 32 kB Instruction (ITCM), up to 32 kB
Data TCM (DTCM).
– Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
– 8 kB ETB SRAM.
– Up to 768 kB flash-program memory with 16 kB EEPROM.
• Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
• External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
• Serial interfaces:
– USB 2.0 full-speed device/OTG controller with dedicated DMA controller and
on-chip PHY for device and Host (LPC2930/39 only) functions.
– Two-channel CAN controller supporting Full-CAN and extensive message filtering
– Two LIN master controllers with full hardware support for LIN communication.
– Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485
support.

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– Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations

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deep; Tx FIFO and Rx FIFO.

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– Two I2C-bus interfaces.

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• Other peripherals:

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– Up to three ADCs: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement

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range and one, 8-channel 10-bit ADC with 5.0 V measurement range provide a

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total of up to 24 analog inputs, with conversion times as low as 2.44 μs per

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channel. Each channel provides a compare function to minimize interrupts.
– Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external
signal input.
– Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os.
– Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality.
– Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
– Quadrature encoder interface that can monitor one external quadrature encoder.
– 32-bit watchdog with timer change protection, running on safe clock.
• Up to 108 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper.
• Vectored Interrupt Controller (VIC) with 16 priority levels.
• Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake-up
features.
• Configurable clock-out pin for driving external system clocks.
• Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
• Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
• Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules:
– On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring.
– On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz - max. PLL input 25 MHz.
– On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
– Generation of up to 11 base clocks.
– Seven fractional dividers.
• Highly configurable system Power Management Unit (PMU):
clock control of individual modules.
allows minimization of system operating power consumption in any configuration.
• Standard ARM test and debug interface with real-time in-circuit emulator.
• Boundary-scan test supported.
• ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage.
• Dual power supply:

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– CPU operating voltage: 1.8 V ± 5 %.

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– I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.

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• Available in 100-pin,144-pin, and 208-pin LQFP packages.

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• −40 °C to 85 °C ambient operating temperature range.

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4. Ordering information

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Table 1. Ordering information
Type number Package
Name Description Version
LPC2917FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
LPC2919FBD144/01 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
LPC2921FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2923FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2925FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2927FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
LPC2929FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm SOT486-1
LPC2930FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
LPC2939FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

UM10316_0 © NXP B.V. 2008. All rights reserved.

User manual Rev. 00.06 — 17 December 2008 5 of 571

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4.1 Ordering options
User manual
UM10316_0

NXP Semiconductors
Table 2. LPC29xx part overview
Part Flash SRAM TCM CAN LIN/ Pins UART SPI 3V3 5 V SMC USB USB USB ETM QEI I2C-bus Clkout
number (incl (I/D) UART RS485 ADC ADC device host OTG pin
ETB)
LPC2939 768 kB 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2930 - 56 kB 32/32 kB 2 2 208 2 3 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes
LPC2929 768 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2927 512 kB 56 kB 32/32 kB 2 2 144 2 3 2 Yes Yes Yes No Yes Yes Yes Yes Yes
LPC2925 512 kB 40 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2923 256 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2921 128 kB 24 kB 16/16 kB 2 2 100 2 3 2 No No Yes No No Yes Yes Yes Yes
LPC2919/01 768 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes
Rev. 00.06 — 17 December 2008

LPC2917/01 512 kB 56 kB 16/16 kB 2 2 144 2 3 2 No Yes No No No Yes Yes Yes Yes

Remark: Note that parts LPC2927 and LPC2929 are not fully pin compatible with parts LPC2917/01 and LPC2919/01 or
LPC2917 and LPC2919. On the LPC2927/29 the MSCSS and timer blocks have a reduced pinout.

4.2 Comparison with LPC2917/19 devices

Table 3. Feature comparison

Chapter 1: LPC29xx Introductory

Parts GPDMA UART I2C QEI CAN LIN USB Flash EEPROM SRAM ETB 5V
RS485 OTG/ total SRAM ADC
mode device
LPC2917/19 no no no no 2 2 no 512/768 kB no 80 kB no no
LPC2917/19/01 yes yes yes yes 2 2 no 512/768 kB yes 88 kB 8 kB no

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LPC2927/29 yes yes yes yes 2 2 yes 512/768 kB yes 120 kB 8 kB yes

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© NXP B.V. 2008. All rights reserved.

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information
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5. Block diagram

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JTAG

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LPC2917/01 TEST/DEBUG
INTERFACE
LPC2919/01
ITCM DTCM
16 kB 8 kB SRAM 16 kB
ARM968E-S

1 × master
2 × slave master
VECTORED slave
INTERRUPT AHB TO DTL
master GPDMA CONTROLLER
CONTROLLER BRIDGE

slave slave
CLOCK AHB TO DTL GPDMA REGISTERS
GENERATION BRIDGE
UNIT CGU0/1
slave
EXTERNAL STATIC
RESET MEMORY CONTROLLER
GENERATION
UNIT slave
EMBEDDED SRAM 16 kB
POWER
MANAGEMENT slave
UNIT EMBEDDED SRAM 32 kB
slave
EMBEDDED FLASH 16 kB
slave 512/768 kB EEPROM
AHB
TIMER0/1 MTMR AHB TO APB
MULTI slave
BRIDGE
LAYER AHB TO APB
SYSTEM CONTROL
PWM0/1/2/3 MATRIX BRIDGE

EVENT ROUTER
3.3 V ADC1/2
CHIP FEATURE ID
slave
QUADRATURE AHB TO APB
ENCODER BRIDGE
GENERAL PURPOSE I/O
slave PORTS 0/1/2/3
AHB TO APB
CAN0/1 BRIDGE
TIMER 0/1/2/3
GLOBAL
ACCEPTANCE SPI0/1/2
FILTER

RS485 UART0/1
LIN0/1

WDT
I2C0/1

002aad959

Grey-shaded blocks represent peripherals with connections to the GPDMA.

Fig 1. LPC2917/19/01 block diagram

UM10316_0 © NXP B.V. 2008. All rights reserved.

User manual Rev. 00.06 — 17 December 2008 7 of 571

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JTAG
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LPC2921/2923/2925 TEST/DEBUG

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INTERFACE

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ITCM DTCM

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16 kB 8 kB SRAM 16 kB
ARM968E-S

1 master
2 slaves
master

master GPDMA CONTROLLER

VECTORED slave slave

INTERRUPT AHB TO DTL
BRIDGE GPDMA REGISTERS
CONTROLLER
master

slave USB DEVICE

CLOCK AHB TO DTL slave
GENERATION CONTROLLER
BRIDGE
UNIT
power. clock, and slave
RESET
reset subsystem EMBEDDED SRAM 16 kB
GENERATION
UNIT slave
EMBEDDED SRAM 16 kB
POWER
(LPC2925 only)
MANAGEMENT AHB
UNIT slave
MULTI- EMBEDDED FLASH 16 kB
LAYER 512/256/128 kB EEPROM
slave MATRIX
TIMER0/1 MTMR AHB TO APB slave
BRIDGE AHB TO APB
SYSTEM CONTROL
MSC subsystem BRIDGE
PWM0/1/2/3
general subsystem EVENT ROUTER
3.3 V ADC1/2
CHIP FEATURE ID
slave
QUADRATURE AHB TO APB
ENCODER BRIDGE
GENERAL PURPOSE I/O
PORTS 0/1/5
peripheral subsystem

slave TIMER 0/1/2/3

AHB TO APB
CAN0/1 BRIDGE
SPI0/1/2
GLOBAL networking subsystem
ACCEPTANCE RS485 UART0/1
FILTER
WDT
I2C0/1

002aae224

Grey-shaded blocks represent peripherals with connections to the GPDMA.

Fig 2. LPC2921/23/25 block diagram

UM10316_0 © NXP B.V. 2008. All rights reserved.

User manual Rev. 00.06 — 17 December 2008 8 of 571

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LPC2927/2929 TEST/DEBUG

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INTERFACE

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ITCM DTCM

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32 kB 8 kB SRAM 32 kB
ARM968E-S

1 master
2 slaves
master

master GPDMA CONTROLLER

VECTORED slave slave

INTERRUPT AHB TO DTL
BRIDGE GPDMA REGISTERS
CONTROLLER
master

slave USB OTG/DEVICE

CLOCK AHB TO DTL slave
GENERATION CONTROLLER
BRIDGE
UNIT
power. clock, and slave
RESET
reset subsystem EXTERNAL STATIC
GENERATION
MEMORY CONTROLLER
UNIT slave
POWER EMBEDDED SRAM 16 kB
MANAGEMENT AHB slave
UNIT MULTI-
EMBEDDED SRAM 32 kB
LAYER
slave MATRIX slave
TIMER0/1 MTMR AHB TO APB
EMBEDDED FLASH 16 kB
BRIDGE
512/768 kB EEPROM
PWM0/1/2/3 MSC subsystem
slave
AHB TO APB
SYSTEM CONTROL
3.3 V ADC1/2 BRIDGE

general subsystem EVENT ROUTER

5 V ADC0
CHIP FEATURE ID
QUADRATURE slave
ENCODER AHB TO APB
BRIDGE
GENERAL PURPOSE I/O
slave PORTS 0/1/2/3/5
AHB TO APB peripheral subsystem
CAN0/1 BRIDGE
TIMER 0/1/2/3
GLOBAL networking subsystem
ACCEPTANCE SPI0/1/2
FILTER

RS485 UART0/1
UART/LIN0/1

WDT
I2C0/1

002aae143

Grey-shaded blocks represent peripherals with connections to the GPDMA.

Fig 3. LPC2927/29 block diagram

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LPC2930 TEST/DEBUG

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INTERFACE

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ARM968E-S

1 master
2 slaves
master

master GPDMA CONTROLLER

VECTORED slave slave

INTERRUPT AHB TO DTL
BRIDGE GPDMA REGISTERS
CONTROLLER
master

slave USB HOST/OTG/DEVICE

CLOCK AHB TO DTL slave
GENERATION CONTROLLER
BRIDGE
UNIT
power. clock, and slave
RESET
reset subsystem EXTERNAL STATIC
GENERATION
MEMORY CONTROLLER
UNIT slave
POWER EMBEDDED SRAM 16 kB
MANAGEMENT AHB slave
UNIT MULTI-
EMBEDDED SRAM 32 kB
LAYER
slave MATRIX slave
TIMER0/1 MTMR AHB TO APB
AHB TO APB
BRIDGE SYSTEM CONTROL
BRIDGE
PWM0/1/2/3 MSC subsystem
general subsystem EVENT ROUTER

3.3 V ADC1/2 CHIP FEATURE ID

slave
AHB TO APB
5 V ADC0 BRIDGE
GENERAL PURPOSE I/O
QUADRATURE PORTS 0/1/2/3/4/5
peripheral subsystem
ENCODER
TIMER 0/1/2/3
slave
AHB TO APB
CAN0/1 BRIDGE SPI0/1/2

GLOBAL networking subsystem

RS485 UART0/1
ACCEPTANCE
FILTER
WDT

UART/LIN0/1

I2C0/1

002aae257

Grey-shaded blocks represent peripherals with connections to the GPDMA.

Fig 4. LPC2930 block diagram

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LPC2939 TEST/DEBUG

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INTERFACE

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ITCM DTCM

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32 kB 8 kB SRAM 32 kB
ARM968E-S

1 master
2 slaves
master

master GPDMA CONTROLLER

VECTORED slave slave

INTERRUPT AHB TO DTL
BRIDGE GPDMA REGISTERS
CONTROLLER
master

slave USB HOST/OTG/DEVICE

CLOCK AHB TO DTL slave
GENERATION CONTROLLER
BRIDGE
UNIT
power. clock, and slave
RESET
reset subsystem EXTERNAL STATIC
GENERATION
MEMORY CONTROLLER
UNIT slave
POWER EMBEDDED SRAM 16 kB
MANAGEMENT AHB slave
UNIT MULTI-
EMBEDDED SRAM 32 kB
LAYER
slave MATRIX slave
TIMER0/1 MTMR AHB TO APB
EMBEDDED FLASH 16 kB
BRIDGE
768 kB EEPROM
PWM0/1/2/3 MSC subsystem
slave
AHB TO APB
SYSTEM CONTROL
3.3 V ADC1/2 BRIDGE

general subsystem EVENT ROUTER

5 V ADC0
CHIP FEATURE ID
QUADRATURE slave
ENCODER AHB TO APB
BRIDGE
GENERAL PURPOSE I/O
slave PORTS 0/1/2/3/4/5
AHB TO APB peripheral subsystem
CAN0/1 BRIDGE
TIMER 0/1/2/3
GLOBAL networking subsystem
ACCEPTANCE SPI0/1/2
FILTER

RS485 UART0/1
UART/LIN0/1

WDT
I2C0/1

002aae254

Grey-shaded blocks represent peripherals with connections to the GPDMA.

Fig 5. LPC2939 block diagram

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6. Functional blocks

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This chapter gives an overview of the functional blocks, clock domains, and power modes.

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See Table 1–2 for availability of peripherals and blocks for specific LPC29xx parts.

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The functional blocks are explained in detail in the following chapters. Several blocks are

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management (i.e. clock on or off and whether the clock responds to sleep and wake-up
events).

Table 4. Functional blocks and clock domains

Short Description Comment
Clock domain AHB
ARM ARM9TDMI-S 32-bit RISC processor
SMC Static Memory Controller For external (static) memory banks
SRAM Internal Static Memory -
Clock domain Flash
Flash - Internal Flash Memory
FMC Flash Memory Controller Controller for the internal flash memory
Clock domain USB
USB USB OTG controller -
Clock domain DMA controller
GPDMA General Purpose DMA
controller
Clock domain VIC
VIC Vectored Interrupt Controller Prioritized/vectored interrupt handling
Clock domain general subsystem
CFID Digital Chip ID Identifies the device and its possibilities
ER Event Router Routes wake-up events and external
interrupts (to CGU/VIC)
SCU System Control Unit Configures memory map and I/O
functions
Clock domain peripheral subsystem
GPIO General-Purpose Directly controls I/O pins
Input/Output
TMR Timer Provides match output and capture
inputs
UART Universal Asynchronous Standard 550 serial port
Receiver/Transmitter
WDT Watchdog Timer to guard (software) execution
SPI Serial Peripheral Interface Supports various industry-standard SPI
protocols
Clock domain modulation and sampling-control subsystem

ADC Analog-to-Digital Converter 10-bit Analog-to-Digital Converter

PWM Pulse-Width Modulator Synchronized Pulse-Width Modulator

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Table 4. Functional blocks and clock domains …continued

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Short Description Comment

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TMR Timer Dedicated Sampling and Control Timer

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QEI Quadrature encoder -

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interface

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Clock domain networking subsystem

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CAN Gateway Includes acceptance filter

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LIN Master controller LIN master controller
I2C I2C-bus
Clock domain power control subsystem
CGU0 Clock Generation Unit Controls clock sources and clock
domains
CGU1 clock generation unit USB clocks and clock out
RGU reset generation unit -
PMU power management unit -

7. Architectural overview
The LPC29xx consists of:

• An ARM968E-S processor with real-time emulation support

• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
• Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
• Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
• One ARM Peripheral Bus for event router and system control.
The LPC29xx configures the ARM968E-S processor in little-endian byte order. All
peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the APB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.

8. ARM968E-S processor
The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective controller
core.

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Amongst the most compelling features of the ARM968E-S are:

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• Separate directly connected instruction and data Tightly Coupled Memory (TCM)

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interfaces

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• Write buffers for the AHB and TCM buses

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• Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed-

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point DSP instructions to accelerate signal-processing algorithms and applications.

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Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline
architecture. Typically, in a three-stage pipeline architecture, while one instruction is being
executed its successor is being decoded and a third instruction is being fetched from
memory. In the five-stage pipeline additional stages are added for memory access and
write-back cycles.

The ARM968E-S processor also employs a unique architectural strategy known as

THUMB, which makes it ideally suited to high-volume applications with memory
restrictions or to applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM968E-S processor has two instruction sets:

• Standard 32-bit ARMv5TE set

• 16-bit THUMB set
The THUMB set's 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM's performance advantage over a
traditional 16-bit controller using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.

THUMB code can provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM controller connected to a 16-bit memory system.

The ARM968E-S processor is described in detail in the ARM968E-S data sheet.

9. On-chip flash memory system

The LPC29xx includes up to 768 kB flash memory system. This memory can be used for
both code and data storage. Flash memory can be programmed in-system via a serial port
(e.g., CAN).

10. On-chip static RAM

In addition to the two 16 kB or 32 kB TCMs, the LPC29xx includes two static RAM
memories: one of up to 32 kB and one of 16 kB. Both may be used for code and/or data
storage.

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1. How to read this chapter

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The memory configuration varies for the different LPC29xx parts (see Table 2–5). In

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addition to the memory blocks, peripheral register blocks in memory region 7 are available

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only if the peripheral is implemented. See Table 2–6 for part specific registers. All other
peripheral registers are available on all LPC29xx parts.

Table 5. LPC29xx memory configurations

Part number Flash SRAM TCM (I/D) SMC
SRAM SRAM ETB
(16 kB) (32 kB) (8KB)
LPC2917/01 512 kB yes yes yes 16/16 kB 8 banks, 16
MB each
LPC2919/01 768 kB yes yes yes 16/16 kB 8 banks, 16
MB each
LPC2921 128 kB yes no yes 16/16 kB -
LPC2923 256 kB yes no yes 16/16 kB -
LPC2925 512 kB no yes yes 16/16 kB -
LPC2927 512 kB yes yes yes 32/32 kB 8 banks, 16
MB each
LPC2929 768 kB yes yes yes 32/32 kB 8 banks, 16
MB each
LPC2930 - yes yes yes 32/32 kB 8 banks, 16
MB each
LPC2939 768 kB yes yes yes 32/32 kB 8 banks, 16
MB each

Table 6. LPC29xx configuration of peripheral registers

Part number peripheral peripheral cluster #6 AHB
cluster #2 peripherals
GPIO ADC0 ADC1 ADC2 USB
LPC291719/01 GPIO0/1/2/3 no yes yes no
LPC2919/01 GPIO0/1/2/3 no yes yes no
LPC2921 GPIO0/1/5 no yes yes yes
LPC2923 GPIO0/1/5 no yes yes yes
LPC2925 GPIO0/1/5 no yes yes yes
LPC2927 GPIO0/1/2/3/5 yes yes yes yes
LPC2929 GPIO0/1/2/3/5 yes yes yes yes
LPC2930 GPIO0/1/2/3/4/5 yes yes yes yes
LPC2939 GPIO0/1/2/3/4/5 yes yes yes yes

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2. Memory-map view of the AHB

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The LPC29xx uses an AHB multilayer bus with the CPU and the GPDMA as the bus

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masters. The AHB slaves are connected to the AHB-lite multilayer bus.The ARM968E-S

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CPU has access to all AHB slaves and hence to all address regions.

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3. Memory-map regions

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The ARM9 processor has a 4 GB of address space. The LPC29xx has divided this
memory space into eight regions of 512 MB each. Each region is used for a dedicated
purpose.

An exception to this is region 0; several of the other regions (or a part of it) can be
shadowed in the memory map at this region. This shadowing can be controlled by
software via the programmable re-mapping registers (see Table 6–63).

Table 7. LPC29xx memory regions

Memory region # Address Description
0 0x0000 0000 TCM area and shadow area
1 0x2000 0000 embedded flash area
2 0x4000 0000 external static memory area
3 0x6000 0000 external static memory controller area
4 0x8000 0000 internal SRAM area
5 0xA000 0000 not used
6 0xC000 0000 not used
7 0xE000 0000 bus-peripherals area

Figure 2–6 gives a graphical overview of the LPC29xx memory map.

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User manual
UM10316_0

NXP Semiconductors
4 GB LPC29xx
0xFFFF FFFF
PCR/VIC control 0xE00A 0000
0xFFFF FFFF 0xFFFF 8000
VIC reserved
0xFFFF F000 reserved 0xE008 B000
PCR/VIC 0xF080 0000 LIN1
reserved 0xE008 A000
0xFFFF C000 DMA interface to TCM
subsystem 0xF000 0000 LIN0
0xFFFF B000 CGU1 0xE008 9000
reserved peripherals #4
PMU 0xE018 3000 CAN common regs 0xE008 8000
0xFFFF A000 networking
RGU ETB control 0xE018 2000 CAN AF regs
0xFFFF 9000 subsystem 0xE008 7000
8 kB ETB SRAM 0xE018 0000 CAN ID LUT
0xFFFF 8000 CGU0 0xE008 6000
DMA controller 0xE014 0000 reserved 0xE008 4000
0xE00E 0000 USB controller(1) 0xE010 0000 I2C1 0xE008 3000
0xE00C A000 reserved reserved
0xE00E 0000 I2C0 0xE008 2000
0xE00C 9000 quadrature encoder
PWM3 peripheral subsystem #6 CAN1 0xE008 1000
0xE00C 8000 0xE00C 0000
PWM2 CAN0 0xE008 0000
0xE00C 7000 reserved
peripherals #6 0xE00A 0000
PWM1 MSCSS 0xE006 0000
0xE00C 6000 peripheral subsystem #4
PWM0 subsystem 0xE008 0000 reserved
Rev. 00.06 — 17 December 2008

0xE00C 5000 0xE005 0000

ADC2 reserved GPIO3 to GPIO5(1)
0xE00C 4000 0xE006 0000 0xE004 D000
ADC1 peripheral subsystem #2 GPIO2(1)
0xE00C 3000 0xE004 0000 0xE004 C000
0xE00C 2000 ADC0 (5V)(1) reserved GPIO1 0xE004 B000
0xE002 0000
MSCSS timer1 peripheral subsystem #0 GPIO0 0xE004 A000
0xE00C 1000 0xE000 0000
0xE00C 0000 MSCSS timer0 reserved SPI2 0xE004 9000
peripherals #2
remappable to 0x8000 C000 SPI1
peripheral 0xE004 8000
shadow area 16 kB AHB SRAM(1) subsystem
0x8000 8000 SPI0 0xE004 7000
0x2020 4000 32 kB AHB SRAM(1)
0x2020 0000 flash controller 2 GB 0x8000 0000 UART1 0xE004 6000
flash reserved UART0 0xE004 5000
reserved memory 0x6000 4000
0x200C 0000 EMI/SMC(1) TIMER3 0xE004 4000
0x6000 0000

Chapter 2: LPC29xx
768 kB(1) on-chip ext. static memory banks 7 to 2(1) TIMER2 0xE004 3000
0x2000 0000 flash TIMER1
0x4300 0000 0xE004 2000
16 MB ext. static memory bank 1(1) TIMER0
0x2000 0000 0x4200 0000 0xE004 1000

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16 MB ext. static memory bank 0(1)

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0x0080 0000 1 GB 0x4000 0000 0xE002 0000

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reserved ITCM/DTCM reserved

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0x0040 8000 peripherals #0 reserved

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memory 0x2020 4000 general 0xE000 2000

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32 kB(1) DTCM

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event router

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0x0040 0000 subsystem 0xE000 2000
on-chip flash(1)

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memory
SCU
© NXP B.V. 2008. All rights reserved.

0xE000 1000

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reserved 0x2000 0000

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0x0000 8000 512 MB shadow area CFID 0xE000 0000

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ITCM/DTCM

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0x0000 0000 32 kB(1) ITCM 0 GB 0x0000 0000

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(1) See Section 2–1 for part-specific implementation. Gray-shaded memory regions are accessible by the GPDMA controller.
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Fig 6. LPC29xx system memory map: graphical overview

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3.1 Region 0: TCM/shadow area

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The ARM968E-S processor has its exception vectors located at address logic 0. Since

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flash is the only non-volatile memory available in the LPC29xx, the exception vectors in

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the flash must be located at address logic 0 at reset (AHB_RST).

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0x1FFF FFFF

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region #0 no physical memory

0x0080 0000

D-TCM region aliasses

0x0040 4000/0

Region #0: TCM area

0x0000_0000 - 0x1FFF_FFFF
D-TCM (16 kByte)

0x0040 0000

I-TCM region aliasses

0x0000 4000/0

I-TCM (16/32 kByte)

0x0000 0000
(Offset Address

Fig 7. Region 0 memory map

After booting a choice must be made for region 0. When enabled, the Tightly Coupled
Memories (TCMs) occupy fixed address locations in region 0 as indicated in Figure 2–6.
Information on how to enable the TCMs can be found in the ARM documentation, see
Ref. 32–2.

To enable memory re-mapping, the LPC29xx AHB system memory map provides a
shadow area (region 0) starting at address logic 0. This is a virtual memory region, i.e. no
actual memory is present at the shadow area addresses. A selectable region of the AHB
system memory map is, apart from its own specific region, also accessible via this shadow
area region.

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After reset, the region 1 embedded flash area is always available at the shadow area.

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be re-mapped to region 0 by means of the shadow memory mapping register. For more

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details about the shadow area see Table 6–63.

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3.2 Region 1: embedded flash area

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Figure 2–8 gives a graphical overview of the embedded flash memory map.

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+ 0x1FFFFFFF

+ 0x00200FFF
FLASH IF1
Configuration Area (4 Kbyte)
+ 0x00200000

+ 0x0007FFFF - 0x000BFFF

Embedded FLASH
memory area
512 Kbyte -
768 Kbyte

+ 0x00000000

Fig 8. Region 1 embedded flash memory

Region 1 is reserved for the embedded flash. A data area of 2 Mbyte (to be prepared for a
larger flash-memory instance) and a configuration area of 4 kB are reserved for each
embedded flash instance. Although the LPC29xx contains only one embedded flash
instance, the memory aperture per instance is defined at 4 Mbyte.

3.3 Region 2: external static memory area

Region 2 is reserved for the external static memory. The LPC29xx provides I/O pins for
eight bank-select signals and 24 address lines. This implies that eight memory banks of
16 Mbytes each can be addressed externally.

3.4 Region 3: external static memory controller area

The external Static-Memory Controller configuration area is located at region 3

3.5 Region 4: internal SRAM area

Figure 2–6 gives a graphical overview of the internal SRAM memory map.

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Region 4 is reserved for internal SRAM. The LPC29xx has two internal SRAM instances.

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Instance #0 is 32 kB, instance #1 is 16 kB. See Section 7–1.

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3.6 Regions 5 and 6

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Regions 5 and 6 are not used.

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3.7 Region 7: bus-peripherals area

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Figure 2–6 gives a graphical overview of the bus-peripherals area memory map.

Region 7 is reserved for all stand-alone memory-mapped bus peripherals.

The lower part of region 7 is again divided into APB clusters, also referred to as
subsystems in this User Manual. A APB cluster is typically used as the address space for
a set of APB peripherals connected to a single AHB2APB bridge, the slave on the AHB
system bus. The clusters are aligned on 256 kB boundaries. In the LPC29xx four APB
clusters are in use: General SubSystem (GeSS), Peripheral SubSystem (PeSS),
Networking SubSystem (IVNSS), and the Modulation and Sampling SubSystem
(MSCSS). The APB peripherals are aligned on 4 kB boundaries inside the APB clusters.

The upper part of region 7 is used as the memory area where memory-mapped register
interfaces of stand-alone AHB peripherals and a DTL cluster reside. Each of these is a
slave on the AHB system bus. In the LPC29xx two such slaves are present: the Power,
Clock and Reset subsystem (PCRSS) and the Vectored Interrupt Controller (VIC). The
PCRSS is a DTL cluster in which the CGU, PMU and RGU are connected to the AHB
system bus via an AHB2DTL adapter. The VIC is a DTL target connected to the AHB
system bus via its own AHB2DTL adapter.

4. Memory-map operating concepts

The basic concept in the LPC29xx is that each memory area has a ‘natural’ location in the
memory map. This is the address range for which code residing in that area is written.
Each memory space remains permanently fixed in the same location, eliminating the need
to have portions of the code designed to run in different address ranges.

Because of the location of the exception-handler vectors on the ARM9 processor (at
addresses 0000 0000h through 0000 001Ch: see Table 2–8) By default, after reset, the
embedded flash is mapped at address 0000 0000h to allow initial code to be executed
and to perform the required initialization, which starts executing at 0000 0000h.

The LPC29xx generates the appropriate bus-cycle abort exception if an access is

attempted for an address that is in a reserved or unused address region or unassigned
peripheral spaces. For these areas both attempted data accesses and instruction fetches
generate an exception. Note that write-access addresses should be word-aligned in ARM
code or half-word aligned in Thumb code. Byte-aligned writes are performed as word or
half-word aligned writes without error signalling.

Within the address space of an existing peripheral a data-abort exception is not generated
in response to an access to an undefined address. Address decoding within each
peripheral is limited to that needed to distinguish defined registers within the peripheral
itself. Details of address aliasing within a peripheral space are not defined in the LPC29xx
documentation and are not a supported feature.

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Note that the ARM stores the pre-fetch abort flag along with the associated instruction

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(which will be meaningless) in the pipeline and processes the abort only if an attempt is

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made to execute the instruction fetched from the illegal address. This prevents the

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accidental aborts that could be caused by pre-fetches occurring when code is executed

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very near to a memory boundary.

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Table 2–9 gives the base-address overview of all peripherals:

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Table 8. Interrupt vectors address table
Address Exception
0000 0000h Reset
0000 0004h Undefined instruction
0000 0008h Software interrupt
0000 000Ch Pre-fetch abort (instruction-fetch memory fault)
0000 0010h Data abort (data-access memory fault)
0000 0014h reserved
0000 0018h IRQ
0000 001Ch FIQ

Table 9. Peripherals base-address overview

Base address Base name AHB peripherals
Memory region 0 to region 6
0000 0000h TCM memory
2000 0000h Embedded flash memory
2020 0000h FMC RegBase Embedded-flash controller
configuration registers
4000 0000h External static memory
6000 0000h SMC RegBase External Static-Memory Controller
configuration registers
8000 0000h Internal SRAM memory
APB Cluster 0: general subsystem
E000 0000h CFID RegBase Chip/feature ID register
E000 1000h SCU RegBase System Control Unit
E000 2000h ER RegBase Event Router
APB Cluster 2: peripheral subsystem
E004 0000h WDT RegBase Watchdog Timer
E004 1000h TMR RegBase Timer 0
E004 2000h TMR RegBase Timer 1
E004 3000h TMR RegBase Timer 2
E004 4000h TMR RegBase Timer 3
E004 5000h UART RegBase 16C550 UART 0
E004 6000h UART RegBase 16C550 UART 1
E004 7000h SPI RegBase SPI 0
E004 8000h SPI RegBase SPI 1
E004 9000h SPI RegBase SPI 2

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Table 9. Peripherals base-address overview …continued

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Base address Base name AHB peripherals

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E004 A000h GPIO RegBase General-Purpose I/O 0

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E004 B000h GPIO RegBase General-Purpose I/O 1

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E004 C000h GPIO RegBase General-Purpose I/O 2

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E004 D000h GPIO RegBase General-Purpose I/O 3

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E004 E000h GPIO RegBase General-Purpose I/O 4
E004 F000h GPIO RegBase General-Purpose I/O 5
APB Cluster 4: networking subsystem
E008 0000h CANC RegBase CAN controller 0
E008 1000h CANC RegBase CAN controller 1
E008 2000h I2C RegBase I2C0-bus interface
E008 3000h I2C Regbase I2C1-bus interface
E008 6000h CANAFM RegBase CAN ID look-up table memory
E008 7000h CANAFR RegBase CAN acceptance filter registers
E008 8000h CANCS RegBase CAN central status registers
E008 9000h LIN RegBase LIN master controller 0
E008 A000h LIN RegBase LIN master controller 1
APB Cluster 6: modulation and sampling-control subsystem
E00C 0000h MTMR RegBase MSCSS timer 0
E00C 1000h MTMR RegBase MSCSS timer 1
E00C 2000h ADC RegBase ADC 0
E00C 3000h ADC RegBase ADC 1
E00C 4000h ADC RegBase ADC 2
E00C 5000h PWM RegBase PWM 0
E00C 6000h PWM RegBase PWM 1
E00C 7000h PWM RegBase PWM 2
E00C 8000h PWM RegBase PWM 3
E00C 9000h QEI RegBase Quadrature encoder interface
AHB peripherals: DMA controller, USB controller
E010 0000h USB RegBase USB controller registers
E014 0000h DMA RegBase GPDMA controller registers
Power, Clock and Reset control cluster
FFFF 8000h CGU RegBase Clock Generation Unit
FFFF 9000h RGU RegBase Reset Generation Unit
FFFF A000h PMU RegBase Power Management Unit
Vector interrupt controller
FFFF F000h VIC RegBase Vectored Interrupt Controller

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1. How to read this chapter

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This chapter describes the base clock generation for all LPC29xx parts.

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Table 10. LPC29xx base clock options
Part CGU0 base clocks CGU1 base clocks
LPC2917/19/01 see Table 3–11 CLK_OUT
LPC2921/23/25 see Table 3–11 CLK_OUT, USB_CLK
LPC2927/29 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK
LPC2939 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK
LPC2930 see Table 3–11 CLK_OUT, USB_CLK, USB_INT_CLK

2. Introduction
The CGU0 is part of the Power Control, Clock, and Reset control (PCR) block and
provides the clocks for all subsystems. A second, dedicated CGU1 provides the clocks for
the USB block and a clock output. The CGU1 has two clock inputs to its PLL which are
internally connected to two base clocks in the CGU0.

Both CGUs are functionally identical and have their own PLL and fractional divider
registers.

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BASE_ICLK0_CLK

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BASE_SYS_CLK

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BASE_USB_CLK

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BASE_ICLK1_CLK

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BASE_USB_I2C_CLK USB

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CPU

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AHB MULTILAYER MATRIX
BASE_OUT_CLK

AHB TO APB BRIDGES CLOCK

OUT
CGU1
VIC
BASE_IVNSS_CLK
networking subsystem
GPDMA
branch
FLASH/SRAM/SMC clocks CAN0/1

GLOBAL
USB REGISTERS ACCEPTANCE
branch FILTER
clocks
general subsytem
LIN0/1
SYSTEM CONTROL
EVENT ROUTER
CFID I2C0/1

BASE_PCR_CLK
peripheral subsystem
power control subsystem

GPIO0 to 5 branch RESET/CLOCK

clock GENERATION &
POWER
BASE_TMR_CLK MANAGEMENT
BASE_MSCSS_CLK
TIMER 0/1/2/3
BASE_SPI_CLK modulation and sampling
SPI0/1/2 control subsystem
BASE_UART_CLK
UART0/1 TIMER0/1 MTMR
BASE_SAFE_CLK
WDT PWM0/1/2/3
branch
clocks
QEI

BASE_ADC_CLK ADC0/1/2
branch
clocks
CGU0

The implementation of GPIO, ADC, and memory subsystem branch clocks varies for different LPC29xx parts.
Fig 9. LPC29xx clock generation

3. CGU0 functional description

The CGU0 uses a set of building blocks to generate the clock for the output branches. The
building blocks are as follows:

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• OSC1M (LP_OSC) – 1 MHz crystal oscillator

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•

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XO50M – up to 25 MHz oscillator

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PL160M – PLL

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• FDIV0..6 – 7 Frequency Dividers

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• Output control

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The following clock output branches are generated (Table 3–11):

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Table 11. CGU0 base clocks
Number Name Frequency Description
(MHz) [1]
0 BASE_SAFE_CLK 0.4 base safe clock (always on) for WDT
1 BASE_SYS_CLK 125 base system clock; ARM and AHB clock
2 BASE_PCR_CLK 0.4 [2] base PCR subsystem clock; for power
control subsystem
3 BASE_IVNSS_CLK 125 base IVNSS subsystem clock for
networking subsystem (CAN, LIN, and
I2C)
4 BASE_MSCSS_CLK 125 base MSCSS subsystem clock for
modulation and sampling control
subsystem.
5 BASE_ICLK0_CLK 125 base internal clock 0, for CGU1
6 BASE_UART_CLK 125 base UART clock
7 BASE_SPI_CLK 50 base SPI clock
8 BASE_TMR_CLK 125 base timers clock
9 BASE_ADC_CLK 4.5 base ADCs clock
10 test clock; reserved - this is an internal clock used for testing
only. This clock is running at start-up and
should be disabled in the PMU for
power-down mode (see Table 5–50 for the
test shell clock configuration registers).
11 BASE_ICLK1_CLK 125 base internal clock 1, for CGU1

[1] Maximum frequency that guarantees stable operation of the LPC29xx.

[2] Fixed to low-power oscillator.

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CLOCK GENERATION UNIT (CGU0)

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OUT 0 BASE_SAFE_CLK

SAFE_CLK_CONF
FDIV0
OUT 1 BASE_SYS_CLK
400 kHz LP_OSC
FDIV_CONF0
clkout SYS_CLK_
EXTERNAL clkout120 CONF
PLL FDIV1 OUT 2 BASE_PCR_CLK
OSCLLLATOR clkout240

PLL_CONTROL PCR_CLK_CONF
FDIV_CONF1

OUT 3 BASE_IVNSS_CLK

IVNSS_CLK_CONF

FDIV6
OUT 11 BASE_ICLK1_CLK
(to CGU1)
FDIV_CONF6
ICLK1_CLK_CONF
PLL clkout240

PLL clkout240
PLL clkout120

PLL clkout120
PLL clkout

PLL clkout
EXT OSC

EXT OSC
LP_OSC

LP_OSC
FDIV0

FDIV6

FDIV0

FDIV6

FREQUENCY MONITOR CLOCK DETECTION

AHB TO DTL BRIDGE

FREQ_MON RDET

Fig 10. Schematic representation of the CGU0

The structure of the clock path of each clock output is shown in Figure 3–11.

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OSC1M

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FDIV0..6

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XO50M

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PLL160M

clkout /
clkout120 /
clkout240

Output
Control

Clock
outputs

Fig 11. Structure of the clock generation scheme

3.1 Controlling the XO50M oscillator (external oscillator)

The XO50M oscillator can be disabled using the ENABLE field in the oscillator control
register. Even when enabled, this can be bypassed using the BYPASS field in the same
register. In this case the input of the OSC1M crystal is fed directly to the output.

The XO50M oscillator has an HF pin which selects the operating mode. For operation at
higher frequencies (15-25 MHz), the XO50M oscillator HF must be enabled. For
frequencies below that the pin must be disabled. Setting of the pin is controlled by the HF
in the oscillator control register.

3.2 Controlling the PL160M PLL

The structure of the PLL clock path is shown in Figure 3–12.

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PSEL

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P23EN

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clkout120 /

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clkout240

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Input clock

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CCO / 2PDIV P23

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clkout

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Bypass

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Direct

/ MDIV

MSEL

Fig 12. PLI60MPLL control mechanisms

The PLL reference input clock is provided by the external oscillator (XO50M). The PLLs
accept an input clock frequency in the range of 10 MHz to 25 MHz only. The input
frequency can be directly routed to the post-divider using the BYPASS control. The
post-divider can be bypassed using the DIRECT control.

The post-divider is controlled by settings of the field PSEL in the output control register.
PSEL is a 2-bit value that selects a division between 1 and 8 in powers of 2.

The feedback divider is controlled by settings of the MSEL field in the output control
register. The MSEL is a 5-bit value corresponding to the feedback divider minus 1. Thus, if
MSEL is programmed to 0 the feedback divider is 1.

In normal mode the post-divider is enabled and the following relations are verified:

Fclkout = MDIV × Fclkin = Fcco / 2×PDIV

Values of the dividers are chosen with the following process:

1. Specify the input clock frequency Fclkin

2. Calculate M to obtain the desired output frequency Fclkout with M = Fclkout / Fclkin
3. Find a value for P so that Fcco = 2×P / Fclkout
4. Verify that all frequencies and divider values conform to the limits

In direct mode, the following relations are verified:

Fclkout = M × Fclkin = Fcco

Unless the PLL is configured in bypass mode it must be locked before using it as a clock
source. The PLL lock indication is read from the PLL status register.

Once the output clock is generated it is possible to use a three-phase output control which
generates three clock signals separated in phase by 120°. This setting is controlled by
field P23EN.

Settings to power down the PLL, controlled by field PD in the PLL control register, and
safe switch setting controlled by the AUTOBLOK field are not shown in the illustration.
Note that safe switching of the clock is not enabled at reset.

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3.3 Controlling the frequency dividers

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The seven frequency dividers are controlled by the FDIV0..6 registers.

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The frequency divider divides the incoming clock by (L/D), where L and D are both 12-bit

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values, and attempts to produce a 50% duty-cycle. Each high or low phase is stretched to

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last approximately D/(L*2) input-clock cycles. When D/(L*2) is an integer the duty cycle is

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exactly 50%, otherwise it is an approximation.

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The minimum division ratio is /2, so L should always be less than or equal to D/2. If not, or
if L is equal to 0, the input clock is passed directly to the output without being divided.

3.4 Controlling the clock output

Once a source is selected for one of the clock branches the output clock can be further
sub-divided using an output divider controlled by field IDIV in the clock-output
configuration register.

Each clock-branch output can be individually controlled to power it down and perform safe
switching between clock domains. These settings are controlled by the PD and
AUTOBLOK fields respectively.

The clock output can trigger disabling of the clock branch on a specific polarity of the
output. This is controlled via field RTX of the output-configuration register.

3.5 Reading the control settings

Each of the control registers is associated with a status register. These registers can be
used to read the configured controls of each of the CGU building blocks.

3.6 Frequency monitor

The CGU includes a frequency-monitor mechanism which measures the clock pulses of
one of the possible clock sources against the reference clock. The reference clock is the
PCR block clock CLK_PCR.

When a frequency-monitor measurement begins two counters are started. The first starts
from the specified number of reference-clock cycles (set in field RCNT) and counts down
to 0: the second counts cycles of the monitored frequency starting from 0. The
measurement is triggered by enabling it in field MEAS and stops either when the
reference clock counter reaches 0 or the measured clock counter (in field FCNT)
saturates.

The rate of the measured clock can be calculated using the formula:

Fmeas = Fcore * FCNTfinal / (RCNTinitial - RCNTfinal)

When the measurement is finished either FCNTfinal is equal to the saturated value of the
counter (FCNT is a 14-bit value) or RCNTfinal is zero.

Measurement accuracy is influenced by the ratio between the clocks. For greater
accuracy the frequency to measure should be closer to the reference clock.

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3.7 Clock detection

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All of the clock sources have a clock detector, the status of which can be read in a CGU

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register. This register indicates which sources have been detected.

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If this is enabled, the absence of any clock source can trigger a hardware interrupt.

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3.8 Bus disable

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This safety feature is provided to avoid accidental changing of the clock settings. If it is
enabled, access to all registers except the RBUS register (so that it can be disabled) is
disabled and the clock settings cannot be modified.

3.9 Clock-path programming

The following flowchart shows the sequence for programing a complete clock path:

Configure PLL to use

XO50MOSC as input
Configure XO50MOSC and generate 80MHz
in normal mode with (Fin = 10 MHz Wait for PLL to lock
HF pin enabled and Fcco = 160 MHz)
with 3-phase output
enabled

Configure FDIV5 to use Configure UART_CLK

Configure FR clock
120° PLL output and to use FDIV5 and
to 40 MHz
generate ~3.6866 MHz divide by 2

Fig 13. Programming the clock path

4. CGU1 functional description

The CGU1 block is functionally identical to the CGU0 block and generates two clocks for
the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and
fractional dividers. The PLLs used in CGU0 and CGU1 are identical.

The clock input to the CGU1 PLL is provided by one of two base clocks generated in the
CGU0: BASE_ICLK0_CLK or BASE_INT1CLK. The base clock not used for the PLL can
be configured to drive the output clock directly.

The CGU1 provides the following three base clocks (Table 3–12):

Table 12. CGU1 base clocks

Base clock Parts of the device clocked by this branch clock
BASE_OUT_CLK clock out pin
BASE_USB_CLK USB clock
BASE_USB_I2C_CLK USB OTG I2C clock

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CLOCK GENERATION UNIT

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(CGU1)

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OUT 0 BASE_USB_CLK

clkout
USB_CLK_CONF
BASE_ICLK0_CLK clkout120
PLL FDIV0
BASE_ICLK1_CLK clkout240
OUT 1 BASE_USB_I2C_CLK

PLL_CONTROL FDIV_CONF0
USB_I2C_CLK_CONF

OUT 2 BASE_OUT_CLK

OUT_CLK_CONF
BASE_ICLK0_CLK

BASE_ICLK1_CLK

BASE_ICLK0_CLK

BASE_ICLK1_CLK
PLL clkout240

PLL clkout240
PLL clkout120

PLL clkout120
PLL clkout

PLL clkout
FDIV0

FDIV0

FREQUENCY MONITOR CLOCK DETECTION AHB TO DTL BRIDGE

FREQ_MON RDET

Fig 14. Block diagram of the CGU1

5. CGU register overview

The CGU registers are shown in Table 3–13.

The clock-generation unit registers have an offset to the base address CGU RegBase
which can be found in the memory map (see Section 2–2).

Remark: Any clock-frequency adjustment has a direct impact on the timing of on-board
peripherals such as the UARTs, SPI, Watchdog, timers, CAN controller, LIN master
controller, ADCs, and flash memory interface.

Table 13. CGU0 register overview (CGU0 base address: 0xFFFF 8000)
Address Access Reset value Name Description Reference
offset
000h R 7100 0011h reserved Reserved -
004h R 0000 0000h reserved Reserved -
008h R 0C00 0000h reserved Reserved -
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Table 13. CGU0 register overview (CGU0 base address: 0xFFFF 8000) …continued

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Address Access Reset value Name Description Reference

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F
offset

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00Ch R - reserved Reserved -

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014h R/W 0000 0000h FREQ_MON Frequency monitor register see Table 3–15

R
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FT
018h R 0000 0FE3h RDET Clock detection register see Table 3–16

D
R
01Ch R 0000 0001h XTAL_OSC_STATUS Crystal-oscillator status register see Table 3–17

A
020h R/W 0000 0005h XTAL_OSC_CONTROL Crystal-oscillator control register see Table 3–18
024h R 0005 1103h PLL_STATUS PLL status register see Table 3–19
028h R/W 0005 1103h PLL_CONTROL PLL control register see Table 3–20
02Ch R 0000 1001h FDIV_STATUS_0 FDIV 0 frequency-divider status register see Table 3–21
030h R/W 0000 1001h FDIV_CONF_0 FDIV 0 frequency-divider control register see Table 3–22
034h R 0000 1001h FDIV_STATUS_1 FDIV 1 frequency-divider status register see Table 3–21
038h R/W 0000 1001h FDIV_CONF_1 FDIV 1 frequency-divider control register see Table 3–22
03Ch R 0000 1001h FDIV_STATUS_2 FDIV 2 frequency-divider status register see Table 3–21
040h R/W 0000 1001h FDIV_CONF_2 FDIV 2 frequency-divider control register see Table 3–22
044h R 0000 1001h FDIV_STATUS_3 FDIV 3 frequency-divider status register see Table 3–21
048h R/W 0000 1001h FDIV_CONF_3 FDIV 3 frequency-divider control register see Table 3–22
04Ch R 0000 1001h FDIV_STATUS_4 FDIV 4 frequency-divider status register see Table 3–21
050h R/W 0000 1001h FDIV_CONF_4 FDIV 4 frequency-divider control register see Table 3–22
054h R 0000 1001h FDIV_STATUS_5 FDIV 5 frequency-divider status register see Table 3–21
058h R/W 0000 1001h FDIV_CONF_5 FDIV 5 frequency-divider control register see Table 3–22
05Ch R 0000 1001h FDIV_STATUS_6 FDIV 6 frequency-divider status register see Table 3–21
060h R/W 0000 1001h FDIV_CONF_6 FDIV 6 frequency-divider control register see Table 3–22
064h R 0000 0000h SAFE_CLK_STATUS Output-clock status register for see Table 3–23
BASE_SAFE_CLK
068h R/W 0000 0000h SAFE_CLK_CONF Output-clock configuration register for see Table 3–24
BASE_SAFE_CLK
06Ch R 0000 0000h SYS_CLK_STATUS Output-clock status register for see Table 3–25
BASE_SYS_CLK
070h R/W 0000 0000h SYS_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_SYS_CLK
074h R 0000 0000h PCR_CLK_STATUS Output-clock status register for see Table 3–25
BASE_PCR_CLK
078h R/W 0000 0000h PCR_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_PCR_CLK
07Ch R 0000 0000h IVNSS_CLK_STATUS Output-clock status register for see Table 3–25
BASE_IVNSS_CLK
080h R/W 0000 0000h IVNSS_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_IVNSS_CLK
084h R 0000 0000h MSCSS_CLK_STATUS Output-clock status register for see Table 3–25
BASE_MSCSS_CLK
088h R/W 0000 0000h MSCSS_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_MSCSS_CLK
08Ch R/W 0000 0000h ICLK0_CLK_CONF Output-clock configuration register for see Table 3–25
BASE_ICLK0_CLK

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A
FT
FT

FT
Table 13. CGU0 register overview (CGU0 base address: 0xFFFF 8000) …continued

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R
R

R
A
A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

D
D

R
R

A
A
090h R 0000 0000h ICLK1_CLK_STATUS Output-clock status register for see Table 3–26

FT
FT

D
BASE_ICLK0_CLK

D
R
A
094h R 0000 0000h UART_CLK_STATUS Output-clock status register for see Table 3–25

FT
BASE_UART_CLK

D
R
A
098h R/W 0000 0000h UART_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_UART_CLK
09Ch R 0000 0000h SPI_CLK_STATUS Output-clock status register for see Table 3–25
BASE_SPI_CLK
0A0h R/W 0000 0000h SPI_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_SPI_CLK
0A4h R 0000 0000h TMR_CLK_STATUS Output-clock status register for see Table 3–25
BASE_TMR_CLK
0A8h R/W 0000 0000h TMR_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_TMR_CLK
0ACh R 0000 0000h ADC_CLK_STATUS Output-clock status register for see Table 3–25
BASE_ADC_CLK
0B0h R/W 0000 0000h ADC_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_ADC_CLK
0B4h R 0000 0000h - reserved -
0B8h R/W 0000 0000h - reserved -
0BCh R/W 0000 0000h ICLK1_CLK_CONF Output-clock configuration register for see Table 3–25
BASE_ICLK1_CLK
0C0h R 0000 0000h ICLK1_CLK_STATUS Output-clock status register for see Table 3–26
BASE_ICLK1_CLK
FD8h W 0000 0000h INT_CLR_ENABLE Interrupt clear-enable register see
Table 10–93
FDCh W 0000 0000h INT_SET_ENABLE Interrupt set-enable register see
Table 10–94
FE0h R 0000 0FE3h INT_STATUS Interrupt status register see
Table 10–95
FE4h R 0000 0000h INT_ENABLE interrupt enable register see
Table 10–96
FE8h W 0000 0000h INT_CLR_STATUS Interrupt clear-status register see
Table 10–97
FECh W 0000 0000h INT_SET_STATUS Interrupt set-status register see
Table 10–98
FF0h R - reserved Reserved -
FF4h R/W 0000 0000h BUS_DISABLE Bus disable register see Table 3–29
FF8h R - reserved Reserved -
FFCh R A0A8 1000h reserved Reserved -

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Table 14. CGU1 register overview (CGU1 base address: 0xFFFF B000)

R
R

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A
A

A
FT
FT

F
Address Access Reset value Name Description Reference

D
D
offset

R
R

A
A

FT
FT
000h R 7100 0011h reserved Reserved -

D
D
R
004h R 0000 0000h reserved Reserved -

A
FT
008h R 0C00 0000h reserved Reserved -

D
R
00Ch R - reserved Reserved -

A
014h R/W 0000 0000h FREQ_MON Frequency monitor register see Table 3–15
018h R 0000 0FE3h RDET Clock detection register see Table 3–16
01Ch R 0005 1103h PLL_STATUS PLL status register see Table 3–19
020h R/W 0005 1103h PLL_CONTROL PLL control register see Table 3–20
024h R 0000 1001h FDIV_STATUS_0 FDIV 0 frequency-divider status register see Table 3–21
028h R/W 0000 1001h FDIV_CONF_0 FDIV 0 frequency-divider control register see Table 3–22
02Ch R 0000 0000h USB_CLK_STATUS Output-clock status register for see Table 3–25
BASE_USB_CLK
030h R/W 0000 0000h USB_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_USB_CLK
034h R 0000 0000h USB_I2C_CLK_STATU Output-clock status register for see Table 3–25
S BASE_I2C_USB_CLK
038h R/W 0000 0000h USB_I2C_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_I2C_USB_CLK
03Ch R 0000 0000h OUT_CLK_STATUS Output-clock status register for see Table 3–25
BASE_OUT_CLK
040h R/W 0000 0000h OUT_CLK_CONF Output-clock configuration register for see Table 3–26
BASE_OUT_CLK
FF4h R/W 0000 0000h BUS_DISABLE Bus disable register see Table 3–29

5.1 Frequency monitor register

The CGU can report the relative frequency of any operating clock. The clock to be
measured must be selected by software, while the fixed-frequency BASE_PCR_CLK is
used as the reference frequency. A 14-bit counter then counts the number of cycles of the
measured clock that occur during a user-defined number of reference-clock cycles. When
the MEAS bit is set the measured-clock counter is reset to 0 and counts up, while the 9-bit
reference-clock counter is loaded with the value in RCNT and then counts down towards
0. When either counter reaches its terminal value both counters are disabled and the
MEAS bit is reset to 0. The current values of the counters can then be read out and the
selected frequency obtained by the following equation:
Qselected
fselected = -------------------------------------------------------------------------- × fref
( Qref [ initial ] – Qref [ final ] )

If RCNT is programmed to a value equal to the core clock frequency in kHz and reaches 0
before the FCNT counter saturates, the value stored in FCNT would then show the
measured clock’s frequency in kHz without the need for any further calculation.

Note that the accuracy of this measurement can be affected by several factors.
Quantization error is noticeable if the ratio between the two clocks is large (e.g. 100 kHz
vs. 1kHz), because one counter saturates while the other still has only a small count

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value. Secondly, due to synchronization, the counters are not started and stopped at

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R
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A
A

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exactly the same time. Finally, the measured frequency can only be to the same level of

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F
precision as the reference frequency.

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R

A
A

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FT
Remark: The clock selection in this register depends on whether the register is used for

D
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R
CGU0 or CGU1. In the CGU0, the low-power oscillator (LP_OSC) or the external crystal

A
FT
oscillator can be selected as input. In the CGU1, the two CGU0 base clocks

D
R
BASE_ICLK0_CLK and BASE_ICLK1_CLK, can be selected instead. CGU1 has only one

A
fractional divider register.

Table 15. FREQ_MON register bit description (FREQ_MON, address 0xFFFF 8014 (CGU0)
and 0xFFFF B014 (CGU1))
* = reset value
Bit Symbol Access Value Description
31 to 24 CLK_SEL R/W Clock-source selection for the clock to be
measured.
00h* LP_OSC (CGU0) or BASE_ICLK0_CLK
(CGU1)
01h Crystal oscillator (CGU0) or BASE_ICLK1_CLK
(CGU1)
02h PLL
03h PLL +120°
04h PLL +240°
05h FDIV0 (CGU0 and CGU1)
06h FDIV1 (CGU0 only)
07h FDIV2 (CGU0 only)
08h FDIV3 (CGU0 only)
09h FDIV4 (CGU0 only)
0Ah FDIV5 (CGU0 only)
0Bh FDIV6 (CGU0 only)
23 MEAS R/W Measure frequency
0*
22 to 9 FCNT R Selected clock-counter value
000h*
8 to 0 RCNT R/W Reference clock-counter value
000h*

5.2 Clock detection register

Each clock generator has a clock detector associated with it to alert the system if a clock
is removed or connected. The status register RDET can determine the current
‘clock-present’ status.

If enabled, interrupts are generated whenever ‘clock present’ changes status, so that an
interrupt is generated if a clock changes from ‘present’ to ‘non-present’ or from
‘non-present’ to ‘present’.

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Remark: The clock selection in this register depends on whether the register is used for

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R

R
A
A

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CGU0 or CGU1. In the CGU0, the low-power oscillator (LP_OSC) or the external crystal

FT
FT

F
oscillator can be selected as input. In the CGU1, the two CGU0 base clocks

D
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R
R

A
A
BASE_ICLK0_CLK and BASE_ICLK1_CLK, can be selected instead. In the CGU1, only

FT
FT
one fractional divider register is used.

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D
R
A
FT
Table 16. RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF

D
B018 (CGU1))

R
A
* = reset value
Bit Symbol Access Value Description
31 to 12 reserved R - Reserved
11 FDIV6_PRESENT R Activity-detection register for FDIV 6 (CGU0
only)
1* Clock present
0 Clock not present
10 FDIV5_PRESENT R Activity-detection register for FDIV 5 (CGU0
only)
1* Clock present
0 Clock not present
9 FDIV4_PRESENT R Activity-detection register for FDIV 4 (CGU0
only)
1* Clock present
0 Clock not present
8 FDIV3_PRESENT R Activity-detection register for FDIV 3 (CGU0
only)
1* Clock present
0 Clock not present
7 FDIV2_PRESENT R Activity-detection register for FDIV 2 (CGU0
only)
1* Clock present
0 Clock not present
6 FDIV1_PRESENT R Activity-detection register for FDIV 1 (CGU0
only)
1* Clock present
0 Clock not present
5 FDIV0_PRESENT R Activity-detection register for FDIV 0 (CGU0
and CGU1)
1* Clock present
0 Clock not present
4 PLL240_PRESENT R Activity-detection register for 240°-shifted
PLL output
1* Clock present
0 Clock not present
3 PLL120_PRESENT R Activity-detection register for 120°-shifted
PLL output
1* Clock present
0 Clock not present

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Table 16. RDET register bit description (RDET, address 0xFFFF 8018 (CGU0) or 0xFFFF

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R
R

R
A
B018 (CGU1)) …continued

A
FT
FT

F
* = reset value

D
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R
R

A
Bit Symbol Access Value Description

FT
FT

D
2 PLL_PRESENT R Activity-detection register for normal PLL

D
R
A
output

FT
1* Clock present

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R
A
0 Clock not present
1 XTAL_PRESENT R Activity-detection register for crystal
(CGU0) or -oscillator output
BASE_ICLK0_CLK_ 1* Clock present
PRESENT (CGU1)
0 Clock not present
0 LP_OSC_PRESEN R Activity-detection register for LP_OSC
T (CGU0) or 1* Clock present
BASE_ICLK1_CLK_
PRESENT (CGU1) 0 Clock not present

5.3 Crystal-oscillator status register (CGU0)

The register XTAL_OSC_STATUS reflects the status bits for the crystal oscillator.

Table 17. XTAL_OSC_STATUS register bit description (XTAL_OSC_STATUS, address

0xFFFF 801C)
* = reset value
Bit Symbol Access Value Description
31 to 3 reserved R - Reserved
2 HF R Oscillator HF pin
1* Oscillator high-frequency mode (crystal or
external clock source above 10 MHz)
0 Oscillator low-frequency mode (crystal or
external clock source below 20 MHz)
1 BYPASS R Configure crystal operation or external clock
input pin XIN_OSC
0 Operation with crystal connected
1* Bypass mode. Use this mode when an external
clock source is used instead of a crystal
0 ENABLE R Oscillator-pad enable
0 Power-down
1* Enable

5.4 Crystal oscillator control register (CGU0)

The register XTAL_OSC_CONTROL contains the control bits for the crystal oscillator.
Following a change of ENABLE bit in XTAL_OSC_CONTROL register requires a read in
XTAL_OSC_STATUS to confirm ENABLE bit is indeed changed.

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Table 18. XTAL_OSC_CONTROL register bit description (XTAL_OSC_CONTROL, address

R
R

R
A
A

A
0xFFFF 8020)

FT
FT

F
* = reset value

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D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

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D
31 to 3 reserved R - Reserved

R
A
FT
2 HF R/W Oscillator HF pin

D
R
1* Oscillator high-frequency mode (crystal or

A
external clock source 15 to 25 MHz)[2]
0 Oscillator low-frequency mode (crystal or
external clock source 1 to 20 MHz)[2]
1 BYPASS R/W Configure crystal operation or external-clock
input pin XIN_OSC[1]
0* Operation with crystal connected
1 Bypass mode. Use this mode when an external
clock source is used instead of a crystal
0 ENABLE R/W Oscillator-pad enable[1]
0 Power-down
1* Enable

[1] Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device
operation!
[2] For between 15 MHz to 20 MHz the state of the HF pin is don’t care, see also the crystal specification notes
in Ref. 32–1. Section 11 (Oscillator).

5.5 PLL status register (CGU0 and CGU1)

The register PLL_STATUS reflects the status bits of the PLL.

Table 19. PLL_STATUS register bit description (PLL_STATUS, address 0xFFFF 8024
(CGU0) and 0xFFFF B024 (CGU1))
* = reset value
Bit Symbol Access Value Description
31 to 1 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
0 LOCK R Indicates if the PLL is in lock or not.
1 In lock
0* Not in lock

5.6 PLL control register (CGU0 and CGU1)

The PLL_CONTROL register contains the control bits for the PLL. In the CGU0, only the
crystal oscillator is allowed as an input to the PLL. In the CGU1, both internal base clocks,
BASE_ICLK0_CLK and BASE_ICLK1_CLK, can be inputs to the PLL.

Post-divider ratio programming

The division ratio of the post-divider is controlled by PSEL[0:1] in the PLL_CONTROL

register. The division ratio is twice the value of P. This guarantees an output clock with a
50% duty cycle.

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Feedback-divider ratio programming

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F
The feedback-divider division ratio is controlled by MSEL[4:0] in the PLL_CONTROL

D
D

R
R
register. The division ratio between the PLL output clock and the input clock is the decimal

A
A

FT
FT
value on MSEL[4:0] plus one.

D
D
R
A
Frequency selection, mode 1 (normal mode)

FT
D
R
A
In this mode the post-divider is enabled, giving a 50% duty cycle clock with the frequency
relations described below:

The output frequency of the PLL is given by the following equation:

fcco
fclkoutPLL = Mfclkin = ----------------
(2 ⋅ P)

To select the appropriate values for M and P:

1. Specify the input clock frequency fclkin

2. Calculate M to obtain the desired output frequency fclkout PLL with M = fclkout/fclkin
3. Find a value for P so that fcco = 2 × P × fclkout
4. Verify that all frequencies and divider values conform to the limits specified.

Frequency selection, mode 2 (direct CCO mode)

In this mode the post-divider is bypassed and the CCO clock is sent directly to the
output(s), leading to the following frequency equation:

fclkout = Mfclkin = fcco

To select the appropriate values for M and P:

1. Specify the input clock frequency fclkin

2. Calculate M to obtain the desired output frequency fclkout with M = fclkout/fclkin
3. Verify that all frequencies and divider values conform to the limits specified.

Note that although the post-divider is not used, it still runs in this mode. To reduce current
consumption to the lowest possible value it is recommended to set PSEL[1:0] to ’00’. This
sets the post-divider to divide by two, which causes it to consume the least amount of
current.

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Table 20. PLL_CONTROL register bit description (PLL_CONTROL, address 0xFFFF 8028

R
R

R
A
A

A
(CGU0) and 0xFFFF B028 (CGU1))

FT
FT

F
* = reset value

D
D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

D
D
31 to 24 CLK_SEL R/W Clock-source Selection for clock generator to

R
A
be connected to the input of the PLL.

FT
D
00h* Not used (CGU0) or BASE_ICLK0_CLK

R
A
(CGU1)
01h Crystal oscillator (CGU0) or BASE_ICLK1_CLK
(CGU1)
02h to Not used
FFh
23 to 16 MSEL[4:0] R/W Feedback-divider division ratio (M)[1]
00000 1
00001 2
00010 3
00011 4
00100* 5
: :
11111 32
15 to 12 reserved R Reserved
11 AUTOBLOK W 1 Enables auto-blocking of clock when
programming changes
0 No action
10 reserved R - Reserved
9 and 8 PSEL[1:0] R/W Post-divider division ratio (2P)[1]
00 2
01* 4
10 8
11 16
7 DIRECT R/W Direct CCO clock output control
0* Clock output goes through post-divider
1 Clock signal goes directly to outputs
6 to 3 reserved R Reserved
7 to 3 reserved R Reserved
2 P23EN R/W Three-phase output mode control
0* PLL +120° and PLL +240° outputs disabled
1 PLL +120° and PLL +240° outputs enabled
1 BYPASS R/W Input-clock bypass control
0 CCO clock sent to post-dividers (only for test
modes)
1* PLL input clock sent to post-dividers
0 PD R/W Power-down control
0 Normal mode
1* Power-down mode[2]

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[1] Changing the divider ratio while the PLL is running is not recommended. Since there is no way of

D
D

D
R
R

R
synchronizing the change of the MSEL and PSEL values with the divider the risk exists that the counter will

A
A

A
FT
FT

F
read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output

D
D
clock. The recommended way of changing between divider settings is to power down the PLL, adjust the

R
R

A
A
divider settings and then let the PLL start up again.

FT
FT

D
D
[2] To power down the PLL, P23EN bit should also be set to 0.

R
A
FT
D
5.7 Frequency divider status register

R
A
There is one status register FDIV_STATUS_n for each frequency divider (n = 0..6 for
CGU0). Note that there is only one frequency divider in the CGU1. The status bits reflect
the inputs to the FDIV as driven from the control register

Table 21. FDIV_STATUS_n register bit description (FDIV_STATUS_0 to 6, address 0xFFFF

802C/34/3C/44/4C/54/5C (CGU0) and FDIV_STATUS_0, address 0xFFFF B024
(CGU1))
* = reset value
Bit Symbol Access Value Description
31 to 24 CLK_SEL R Selected source clock for FDIV n
00h* LP_OSC (CGU0) or (BASE_ICLK0_CLK)
(CGU1)
01h Crystal oscillator (CGU0) or
(BASE_ICLK1_CLK) (CGU1)
02h PLL
03h PLL +1200
04h PLL +2400
05h to Not used
FFh
23 to 12 LOAD R Load value
001h*
11 to 0 DENOMINATOR R Denominator or modulo value.
001h*

5.8 Frequency divider configuration register

There is one control register FDIV_CONF_n for each frequency divider (n = 0..6).

The frequency divider divides the incoming clock by (LOAD/DENOMINATOR), where

LOAD and DENOMINATOR are both 12-bit values programmed in the control register
FDIV_CONTROL_n.

Essentially the output clock generates ‘LOAD’ positive edges during every
‘DENOMINATOR’ cycle of the input clock. An attempt is made to produce a 50%
duty-cycle. Each high or low phase is stretched to last approximately
DENOMINATOR/(LOAD*2) input clock cycles. When DENOMINATOR/(LOAD*2) is an
integer the duty cycle is exactly 50%: otherwise the waveform will only be an
approximation. It will be close to 50% for relatively large non-integer values of
DENOMINATOR/(LOAD*2), but not for small values.

The minimum division ratio is divide-by-2, so LOAD should always be less than or equal to
(DENOMINATOR/2). If this is not true, or if LOAD is equal to 0, the input clock is passed
directly to the output with no division.

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Table 22. FDIV_CONF_n register bit description (FDIV_CONF_n, address 0xFFFF

R
R

R
A
A

A
8030/38/40/48/50/58/60 (CGU0) and FDIV_CONF_0, address 0xFFFF B028 (CGU1))

FT
FT

F
* = reset value

D
D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

D
D
31 to 24 CLK_SEL R/W Selected source clock for FDIV n

R
A
FT
00h* LP_OSC (CGU0) or (BASE_ICLK0_CLK)

D
(CGU1)

R
A
01h Crystal oscillator (CGU0) or
(BASE_ICLK1_CLK) (CGU1)
02h PLL
03h PLL +1200
04h PLL +2400
05h to Invalid
FFh
23 to 12 LOAD R/W Load value
001h*
11 to 0 DENOMINATOR R/W Denominator or modulo value.
001h*

5.9 Output-clock status register for BASE_SAFE_CLK and

BASE_PCR_CLK
There is one status register for each CGU output clock generated. All output generators
have the same register bits. Exceptions are the output generators for BASE_SAFE_CLK
and BASE_PCR_CLK, which are described here. For the other outputs, see
Section 3–5.11.

Table 23. SAFE_CLK_STATUS (address 0xFFFF 8064), PCR_CLK_STATUS (address 0xFFFF

0074) register bit description
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved
4 to 2 IDIV R 000* Integer divide value
1 to 0 reserved R - Reserved.

5.10 Output-clock configuration register for BASE_SAFE_CLK and

BASE_PCR_CLK
There is one configuration register for each CGU output clock generated. All output
generators have the same register bits. An exception is the output generators for
BASE_SAFE_CLK and BASE_PCR_CLK, which are described here. For the other
outputs see Section 3–5.12.

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Table 24. SAFE_CLK_CONF (address 0xFFFF 8068), PCR_CLK_CONF (address 0xFFFF

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8078) register bit description

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* = reset value

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Bit Symbol Access Value Description

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31 to 24 CLK_SEL R/W Selected source clock

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00h* LP_OSC

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01h to Invalid: the hardware will not accept these

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FFh values when written
23 to 5 reserved R - Reserved; do not modify, read as logic 0, write
as logic 0
4 to 2 IDIV R/W 000* Integer divide value
1 to 0 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0

5.11 Output-clock status register for CGU0 clocks

There is one status register for each CGU output clock generated. All output generators
have the same register bits. Exceptions are the output generators for BASE_SAFE_CLK
and BASE_PCR_CLK, see Section 3–5.9.

Table 25. XX_CLK_STATUS register bit description (XX = SYS (address 0xFFFF 806C),
IVNSS (address 0xFFFF 807C), MSCSS (address 0xFFFF 8084), UART (address
0xFFFF 8094), SPI (address 0xFFFF 809C), TMR (address 0xFFFF 80A4), ADC
(address 0xFFFF 80AC))
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved
4 to 2 IDIV R 000* Integer divide value
1 RTX R 0* Clock-disable polarity
0 PD R 0* Power-down clock slice

5.12 Output-clock configuration register for CGU0 clocks

There is one configuration register for each CGU output clock generated. All output
generators have the same register bits. Exceptions are the output generators for
BASE_SAFE_CLK and BASE_PCR_CLK, see Section 3–5.10.

XX = SYS, IVNSS, MSCSS, UART, SPI, TMR or ADC, ICLK0/1_CLK

Each output generator takes in one input clock and sends one clock out of the CGU. In
between the clock passes through an integer divider and a clock control block. A clock
blocker/switch block connects to the clock control block.

The integer divider has a 3-bit control signal, IDIV, and divides the incoming clock by any
value from 1 through 8. The divider value is equal to (IDIV + 1); if IDIV is equal to zero, the
incoming clock is passed on directly to the next stage. When the input to the integer
divider has a 50% duty cycle the divided output will have a 50% duty cycle for all divide
values. If the incoming duty cycle is not 50% only even divide values will produce an
output clock with a 50% duty cycle.

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Table 26. XX_CLK_CONF register bit description (XX = SYS (address 0xFFFF 8070), IVNSS

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(address 0xFFFF 8080), MSCSS (address 0xFFFF 8088), UART (address 0xFFFF

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8098), SPI (address 0xFFFF 80A0), TMR (address 0xFFFF 80A8), ADC (address

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0xFFFF 80B0))

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* = reset value

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Bit Symbol Access Value Description

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31 to 24 CLK_SEL R/W selected source clock

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00h* LP_OSC
01h Crystal oscillator[1]
02h PLL
03h PLL +1200
04h PLL +2400
05h FDIV0
06h FDIV1
07h FDIV2
08h FDIV3
09h FDIV4
0Ah FDIV5
0Bh FDIV6
23 to 12 reserved R - Reserved
11 AUTOBLOK W - Enables auto-blocking of clock when
programming changes
10 to 5 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
4 to 2 IDIV R/W 000* Integer divide value
1 reserved R/W 0* Reserved; do not modify. Read as logic 0, write
as logic 0
0 PD R/W 0* Power-down clock slice

[1] At reset release, the JTAGSEL pin is sampled. If it is LOW (ARM debug), the crystal oscillator (XO50M) will
be selected as source for BASE_SYS_CLK.

5.13 Output-clock status register for CGU1 clocks

There is one status register for each CGU1 output clock generated. All output generators
have the same register bits.

Table 27. XX_CLK_STATUS register bit description (XX = USB_CLK (address 0xFFFF
B02C), USB_I2C (address 0xFFFF B034), OUT_CLK (address 0xFFFF B03C))
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved
4 to 2 IDIV R 000* Integer divide value
1 RTX R 0* Clock-disable polarity
0 PD R 0* Power-down clock slice

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5.14 Output-clock configuration register for CGU1 clocks

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There is one configuration register for each CGU1 output clock generated. All output

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generators have the same register bits. The CGU1 output clock can be generated directly

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from the two CGU0 base clocks BASE_ICLK0_CLK and BASE_ICLK1_CLK or from the

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CGU1 PLL.

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Each output generator takes in one input clock and sends one clock out of the CGU. In

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between the clock passes through an integer divider and a clock control block. A clock
blocker/switch block connects to the clock control block.

The integer divider has a 3-bit control signal, IDIV, and divides the incoming clock by any
value from 1 through 8. The divider value is equal to (IDIV + 1); if IDIV is equal to zero, the
incoming clock is passed on directly to the next stage. When the input to the integer
divider has a 50% duty cycle the divided output will have a 50% duty cycle for all divide
values. If the incoming duty cycle is not 50% only even divide values will produce an
output clock with a 50% duty cycle.

Table 28. XX_CLK_CONF register bit description (XX = USB_CLK (address 0xFFFF B030),
USB_I2C_CLK (address 0xFFFF B038), OUT_CLK (address 0xFFFF B040))
* = reset value
Bit Symbol Access Value Description
31 to 24 CLK_SEL R/W selected source clock
00h* BASE_ICLK0_CLK
01h BASE_ICLK1_CLK
02h PLL
03h PLL +1200
04h PLL +2400
05h FDIV0
06h - reserved
0Bh
23 to 12 reserved R - Reserved
11 AUTOBLOK W - Enables auto-blocking of clock when
programming changes
10 to 5 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
4 to 2 IDIV R/W 000* Integer divide value
1 reserved R/W 0* Reserved; do not modify. Read as logic 0, write
as logic 0
0 PD R/W 0* Power-down clock slice

[1] When JTAG = 1, crystal Oscillator will be the default value for the BASE_SYS_CLK

5.15 Bus disable register

The BUS_DISABLE register prevents any disabled register in the CGU0 from being
written to.

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Table 29. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 8FF4

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(CGU0) and 0xFFFF BFF4 (CGU1))

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* = reset value

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Bit Symbol Access Value Description

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31 to 1 reserved R - Reserved; do not modify. Read as logic 0, write

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as logic 0

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0 RRBUS R/W Bus write-disable bit

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1 No writes to registers within CGU are possible
(except the BUS_DISABLE register)
0* Normal operation

5.16 CGU0 interrupt bit description

Table 3–30 gives the interrupts for the CGU0. The first column gives the bit number in the
interrupt registers. For a general explanation of the interrupt concept and a description of
the registers see Section 10–5.

Table 30. CGU interrupt sources

Register Interrupt source Description
bit
31 to 12 unused Unused
11 FDIV6 FDIV 6 activity state change
10 FDIV5 FDIV 5 activity state change
9 FDIV4 FDIV 4 activity state change
8 FDIV3 FDIV 3 activity state change
7 FDIV2 FDIV 2 activity state change
6 FDIV1 FDIV 1 activity state change
5 FDIV0 FDIV 0 activity state change
4 PL160M240 PLL +240° activity state change
3 PL160M120 PLL +120° activity state change
2 PL160M PLL activity state change
1 crystal Crystal-oscillator activity state change
0 LP_OSC Ring-oscillator activity state change

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. The USB reset is not available on

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the LPC2917/19/01 parts.

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2. Introduction
The RGU is part of the Power Control, Clock, and Reset Subsystem (PCRSS) together
with the CGU (see Section 3–3) and PMU.

3. RGU functional description

The RGU allows generation of independent reset signals for the following outputs:

Table 31. Reset output configuration

Reset output Reset source Parts of the device reset when activated
POR_RST power-on reset module LP_OSC; source for RGU_RST
RGU_RST POR_RST, RST_N pin RGU internal; source for PCR_RST
PCR_RST RGU_RST, WATCHDOG PCR (Power, Clock, and Reset) internal;
source for COLD_RST
COLD_RST PCR_RST parts with COLD_RST as reset source below
WARM_RST COLD_RST parts with WARM_RST as reset source below
SCU_RST COLD_RST SCU
CFID_RST COLD_RST CFID
FMC_RST COLD_RST embedded Flash-Memory Controller (FMC)
EMC_RST COLD_RST embedded SRAM-Memory Controller
SMC_RST COLD_RST external Static-Memory Controller (SMC)
GESS_A2V_RST WARM_RST GeSS AHB-to-APB bridge
PESS_A2V_RST WARM_RST PeSS AHB-to-APB bridge
GPIO_RST WARM_RST all GPIO modules
UART_RST WARM_RST all UART modules
TMR_RST WARM_RST all Timer modules in PeSS
SPI_RST WARM_RST all SPI modules
IVNSS_A2V_RST WARM_RST IVNSS AHB-to-APB bridge
IVNSS_CAN_RST WARM_RST all CAN modules including Acceptance filter
IVNSS_LIN_RST WARM_RST all LIN modules
MSCSS_A2V_RST WARM_RST MSCSS AHB to APB bridge
MSCSS_PWM_RST WARM_RST all PWM modules
MSCSS_ADC_RST WARM_RST all ADC modules
MSCSS_TMR_RST WARM_RST all Timer modules in MSCSS
I2C_RST WARM_RST all I2C modules

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Table 31. Reset output configuration …continued

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Reset output Reset source Parts of the device reset when activated

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QEI_RST WARM_RST Quadrature encoder

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DMA_RST WARM_RST GPDMA controller

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USB_RST WARM_RST USB controller

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VIC_RST WARM_RST Vectored Interrupt Controller (VIC)

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AHB_RST WARM_RST CPU and AHB Bus infrastructure

Generation of reset outputs is controlled using registers RESET_CTRL0 and

RESET_CTRL1. Note that a POR reset can also be triggered by software.

The RGU monitors the reset cause for each reset output. The reset cause can be
retrieved with two levels of granularity.

The first level is monitored by the RESET_STATUS0 to 3 registers and indicates one of
the following reset causes (see Table 4–36 to Table 4–39):

• No reset has taken place

• Watchdog reset
• Reset generated by software via RGU register
• Other cause

The second level of granularity is monitored by one individual register for each reset
output in which the detailed reset cause is indicated (see Table 4–42 to Table 4–46).
Detailed reset causes depend on the reset hierarchy:

• POR reset (does not have a reset source register as it can only be activated by POR)
• RGU reset
• Watchdog reset
• PCR (Power control, Clock, and Reset Subsystem) reset
• Cold reset
• Warm reset

3.1 Reset hierarchy

The different types of system reset can be ordered according to their scope. The hierarchy
is as follows (see Table 4–32):

1. POR reset: resets everything in the IC.

2. External reset: resets everything in the IC except the OSC 1M oscillator.
3. RGU reset: resets RGU and then has the same effect as Watchdog reset.
4. Watchdog-triggered reset: triggers PCR reset.
5. PCR reset: triggers cold reset and resets Watchdog and flash controller
general-purpose outputs.
6. Cold reset: triggers warm reset and resets external memory controller, flash controller,
SRAM controller, the SCU, and the CFID.
7. Warm reset: Resets non-memory peripherals (UART, ADC, I2C, timers, etc.). Does
not reset memory controllers, SCU, CFID or Watchdog.
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Table 32. Reset priority

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Priority Reset OSC1M RGU WDT SCU Flash CFID Memory all other

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controller controllers peripherals

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(SRAM,SMC)

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1 POR yes yes yes yes yes yes yes yes

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2 EXT no yes yes yes yes yes yes yes

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RESET

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3 RGU no yes yes yes yes yes yes yes
4 WDT no no yes yes yes yes yes yes
5 PCR no no yes yes yes yes yes yes
6 Cold no no no no yes yes yes yes
7 Warm no no no no no no no yes

4. RGU register overview

The Reset Generation Unit (RGU) registers are shown in Table 4–33.

The RGU registers have an offset to the base address RGU RegBase which can be found
in the memory map (see Section 2–2).

Table 33. RGU register overview (base address: 0xFFFF 9000)

Address Access Reset value Name Description Reference
offset
100h W - RESET_CTRL0 Reset control register 0 see Table 4–34
104h W - RESET_CTRL1 Reset control register 1 see Table 4–35
110h R/W <tbd> RESET_STATUS0 Reset status register 0 see Table 4–36
114h R/W <tbd> RESET_STATUS1 Reset status register 1 see Table 4–37
118h R/W <tbd> RESET_STATUS2 Reset status register 2 see Table 4–38
11Ch R/W <tbd> RESET_STATUS3 Reset status register 3 see Table 4–39
150h R FFFF FFFFh RST_ACTIVE_STATUS0 Reset-Active Status register 0 see Table 4–40
154h R FFFF FFFFh RST_ACTIVE_STATUS1 Reset-Active Status register 1 see Table 4–41
404h R/W 0000 0000h RGU_RST_SRC Source register for RGU reset see Table 4–42
408h R/W 0000 0000h PCR_RST_SRC Source register for PCR reset see Table 4–43
40Ch R/W 0000 0010h COLD_RST_SRC Source register for COLD reset see Table 4–44
410h R/W 0000 0020h WARM_RST_SRC Source register for WARM reset see Table 4–45
480h R/W 0000 0020h SCU_RST_SRC Source register for SCU reset see Table 4–45
484h R/W 0000 0020h CFID_RST_SRC Source register for CFID reset see Table 4–45
490h R/W 0000 0020h FMC_RST_SRC Source register for EFC reset see Table 4–45
494h R/W 0000 0020h EMC_RST_SRC Source register for EMC reset see Table 4–45
498h R/W 0000 0020h SMC_RST_SRC Source register for SMC reset see Table 4–45
4A0h R/W 0000 0040h GESS_A2V_RST_SRC Source register for GeSS AHB2APB see Table 4–46
bridge reset
4A4h R/W 0000 0040h PESS_A2V_RST_SRC Source register for PeSS AHB2APB see Table 4–46
bridge reset
4A8h R/W 0000 0040h GPIO_RST_SRC Source register for GPIO reset see Table 4–46
4ACh R/W 0000 0040h UART_RST_SRC Source register for UART reset see Table 4–46

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Table 33. RGU register overview (base address: 0xFFFF 9000) …continued

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Address Access Reset value Name Description Reference

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offset

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4B0h R/W 0000 0040h TMR_RST_SRC Source register for Timer reset see Table 4–46

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4B4h R/W 0000 0040h SPI_RST_SRC Source register for SPI reset see Table 4–46

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4B8h R/W 0000 0040h IVNSS_A2V_RST_SRC Source register for IVNSS AHB2APB see Table 4–46

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bridge reset

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4BCh R/W 0000 0040h IVNSS_CAN_RST_SRC Source register for IVNSS CAN reset see Table 4–46
4C0h R/W 0000 0040h IVNSS_LIN_RST_SRC Source register for IVNSS LIN reset see Table 4–46
4C4h R/W 0000 0040h MSCSS_A2V_RST_SRC Source register for MSCSS AHB2APB see Table 4–46
bridge reset
4C8h R/W 0000 0040h MSCSS_PWM_RST_SRC Source register for MSCSS PWM reset see Table 4–46
4CCh R/W 0000 0040h MSCSS_ADC_RST_SRC Source register for MSCSS ADC reset see Table 4–46
4D0h R/W 0000 0040h MSCSS_TMR_RST_SRC Source register for MSCSS Timer reset see Table 4–46
4D4h R/W 0000 0040h I2C_RST_SRC Source register for I2C reset see Table 4–46
4D8h R/W 0000 0040h QEI_RST_SRC Source register for QEI reset see Table 4–46
4DCh R/W 0000 0040h DMA_RST_SRC Source register for DMA reset see Table 4–46
4E0h R/W 0000 0040h USB_RST_SRC Source register for USB reset see Table 4–46
4F0h R/W 0000 0040h VIC_RST_SRC Source register for VIC reset see Table 4–46
4F4h R/W 0000 0040h AHB_RST_SRC Source register for AHB reset see Table 4–46
FF4h R/W 0000 0000h BUS_DISABLE Bus-disable register see Table 4–47
FF8h R 0000 0000h reserved Reserved
FFCh R A098 1000h reserved Reserved

4.1 RGU reset control register

The RGU reset control register allows software to activate and release individual reset
outputs. Each bit corresponds to an individual reset output, and writing a ‘1’ activates that
output. The reset output is automatically de-activated after a fixed delay period.

Table 34. RESET_CONTROL0 register bit description(RESET_CONTROL0, address

0xFFFF 9100)
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved; do not modify, write as logic 0
4 WARM_RST_CTRL W - Activate WARM_RST
3 COLD_RST_CTRL W - Activate COLD_RST
2 PCR_RST_CTRL W - Activate PCR_RST
1 RGU_RST_CTRL W - Activate RGU_RST
0 reserved R - Reserved; do not modify. Write as logic 0

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Table 35. RESET_CONTROL1 register bit description (RESET_CONTROL1, 0xFFFF 9104)

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* = reset value

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Bit Symbol Access Value Description

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31 and reserved R - Reserved; do not modify, write as

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30 logic 0

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29 AHB_RST_CTRL W - Activate AHB_RST

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28 VIC_RST_CTRL W - Activate VIC_RST

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27 to 25 reserved R - Reserved; do not modify. Write as
logic 0
24 USB W - Activate USB_RST
23 DMA_RST_CTRL W - Activate DMA_RST
22 MSCSS_QEI_RST_CTRL W - Activate MSCSS_QEI_RST
21 IVNSS_I2C_RST_CTRL W - Activate IVNSS_I2C_RST
20 MSCSS_TMR_RST_CTRL W - Activate MSCSS_TMR_RST
19 MSCSS_ADC_RST_CTRL W - Activate MSCSS_ADC_RST
18 MSCSS_PWM_RST_CTRL W - Activate MSCSS_PWM_RST
17 MSCSS_A2V_RST_CTRL W - Activate MSCSS_A2V_RST
16 IVNSS_LIN_RST_CTRL W - Activate IVNSS_LIN_RST
15 IVNSS_CAN_RST_CTRL W - Activate IVNSS_CAN_RST
14 IVNSS_A2V_RST_CTRL W - Activate IVNSS_A2V_RST
13 SPI_RST_CTRL W - Activate SPI_RST
12 TMR_RST_CTRL W - Activate TMR_RST
11 UART_RST_CTRL W - Activate UART_RST
10 GPIO_RST_CTRL W - Activate GPIO_RST
9 PESS_A2V_RST_CTRL W - Activate PESS_A2V_RST
8 GESS_A2V_RST_CTRL W - Activate GESS_A2V_RST
7 reserved R - Reserved; do not modify. Write as
logic 0
6 SMC_RST_CTRL W - Activate SMC_RST
5 EMC_RST_CTRL W - Activate EMC_RST
4 FMC_RST_CTRL W - Activate FMC_RST
3 and 2 reserved R - Reserved; do not modify. Read as
logic 0
1 CFID_RST_CTRL W - Activate CFID_RST
0 SCU_RST_CTRL W - Activate SCU_RST

4.2 RGU reset status register

The reset status register shows which source (if any) caused the last reset activation per
individual reset output of the RGU. When one (or more) inputs of the RGU caused the
Reset Output to go active (indicated by value’01’), the respective **_RST_SRC register
can be read, see Section 4–4.4. The register is cleared by writing 0000 0000h to it.

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Table 36. RESET_STATUS0 register bit description (RESET_STATUS0, address

R
R

R
A
A

A
0xFFFF 9110)

FT
FT

F
* = reset value

D
D

R
R

A
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Bit Symbol Access Value Description

FT
FT

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D
31 to 10 reserved R - Reserved; do not modify. Read as logic 0,

R
A
write as logic 0

FT
D
9 and 8 WARM_RST_STAT R/W Status of warm reset

R
A
00 No reset activated since RGU last came out of
reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
7 and 6 COLD_RST_STAT R/W Status of cold reset
00 No reset activated since RGU last came out of
reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
5 and 4 PCR_RST_STAT R/W Status of PCR reset
00* No reset activated since RGU last came out of
reset
01 Input reset to the RGU
10 Reserved
11 Reset control register
3 and 2 RGU_RST_STAT R/W Status of RGU reset
00* No reset activated since RGU last came out of
reset
01 Input reset to the RGU
10 Reserved
11 Reset control register
1 and 0 POR_RST_STAT R/W Status of POR reset
00* No reset activated since RGU last came out of
reset
01 Power On Reset
10 Reserved
11 Reset control register

Table 37. RESET_STATUS1 register bit description (RESET_STATUS1, address

0xFFFF 9114)
* = reset value
Bit Symbol Access Value Description
31 to 0 reserved R - Reserved; do not modify. Read as logic 0

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Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address

R
R

R
A
A

A
0xFFFF 9118)

FT
FT

F
* = reset value

D
D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

D
D
31 and 30 IVNSS_CAN_RST_STAT R/W Reset IVNSS CAN status

R
A
FT
00 No reset activated since RGU last

D
came out of reset

R
A
01* Input reset to the RGU
10 Reserved
11 Reset control register
29 and 28 IVNSS_A2V_RST_STAT R/W Reset IVNSS AHB2APB status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
27 and 26 SPI_RST_STAT R/W Reset SPI status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
25 and 24 TMR_RST_STAT R/W Reset Timer status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
23 and 22 UART_RST_STAT R/W Reset UART status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
21 and 20 GPIO_RST_STAT R/W Reset GPIO status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register

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A

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FT

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Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address

D
D

D
R
R

R
A
0xFFFF 9118) …continued

A
FT
FT

F
* = reset value

D
D

R
R

A
Bit Symbol Access Value Description

FT
FT

D
19 and 18 PESS_A2V_RST_STAT R/W Reset PeSS AHB2APB status

D
R
A
00 No reset activated since RGU last

FT
came out of reset

D
R
A
01* Input reset to the RGU
10 Reserved
11 Reset control register
17 and 16 GESS_A2V_RST_STAT R/W Reset GeSS AHB2APB status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
15 and 14 reserved R - Reserved; do not modify. Read as
logic 0, write as logic 0
13 and 12 SMC_RST_STAT R/W Reset SMC status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
11 and 10 EMC_RST_STAT R/W Reset EMC status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
9 and 8 FMC_RST_STAT R/W Reset FMC status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
7 to 4 reserved R 05h* Reserved
3 and 2 CFID_RST_STAT R/W Reset CFID status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register

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Table 38. RESET_STATUS2 register bit description (RESET_STATUS2, address

D
D

D
R
R

R
A
0xFFFF 9118) …continued

A
FT
FT

F
* = reset value

D
D

R
R

A
Bit Symbol Access Value Description

FT
FT

D
1 and 0 SCU_RST_STAT R/W Reset SCU status

D
R
A
00 No reset activated since RGU last

FT
came out of reset

D
R
A
01* Input reset to the RGU
10 Reserved
11 Reset control register

Table 39. RESET_STATUS3 register bit description (RESET_STATUS3, address

0xFFFF 911C)
* = reset value
Bit Symbol Access Value Description
31 to 28 reserved R 05h* Reserved; do not modify. Read as
logic 0
27 and 26 AHB_RST_STAT R/W Reset AHB status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
25 and 24 VIC_RST_STAT R/W Reset INTC status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
23 to 18 reserved R 15h* Reserved; do not modify. Read as
logic 0
17 and 16 USB_STAT R/W Reset USB status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
15 and 13 DMA_STAT R/W Reset DMA status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register

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Table 39. RESET_STATUS3 register bit description (RESET_STATUS3, address

D
D

D
R
R

R
A
0xFFFF 911C) …continued

A
FT
FT

F
* = reset value

D
D

R
R

A
Bit Symbol Access Value Description

FT
FT

D
13 and 12 MSCSS_QEI_STAT R/W Reset MSCSS QEI status

D
R
A
00 No reset activated since RGU last

FT
came out of reset

D
R
A
01* Input reset to the RGU
10 Reserved
11 Reset control register
11 and 10 IVNSCC_I2C_STAT R/W Reset IVNSCC I2C status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
9 and 8 MSCSS_TMR_RST_STAT R/W Reset MSCSS Timer status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
7 and 6 MSCSS_ADC_RST_STAT R/W Reset MSCSS ADC status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
5 and 4 MSCSS_PWM_RST_STAT R/W Reset MSCSS PWM status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register
3 and 2 MSCSS_A2V_RST_STAT R/W Reset MSCSS AHB2APB status
00 No reset activated since RGU last
came out of reset
01* Input reset to the RGU
10 Reserved
11 Reset control register

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Table 39. RESET_STATUS3 register bit description (RESET_STATUS3, address

D
D

D
R
R

R
A
0xFFFF 911C) …continued

A
FT
FT

F
* = reset value

D
D

R
R

A
Bit Symbol Access Value Description

FT
FT

D
1 and 0 IVNSS_LIN_RST_STAT R/W Reset IVNSS LIN status

D
R
A
00 No reset activated since RGU last

FT
came out of reset

D
R
A
01* Input reset to the RGU
10 Reserved
11 Reset control register

4.3 RGU reset active status register

The reset active status register shows the current value of the reset outputs of the RGU.
Note that the resets are active LOW.

Table 40. RST_ACTIVE_STATUS0 register bit description (RST_ACTIVE_STATUS0, address

0xFFFF 9150)
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved; do not modify
4 WARM_RST_STAT R 1* Current state of WARM_RST
3 COLD_RST_STAT R 1* Current state of COLD_RST
2 PCR_RST_STAT R 1* Current state of PCR_RST
1 RGU_RST_STAT R 1* Current state of RGU_RST
0 POR_RST_STAT R 1* Current state of POR_RST

Table 41. RST_ACTIVE_STATUS1 register bit description (RST_ACTIVE_STATUS1, address

0xFFFF 9154)
* = reset value
Bit Symbol Access Value Description
31 and reserved R - Reserved; do not modify
30
29 AHB_RST_STAT R 1* Current state of AHB_RST
28 VIC_RST_STAT R 1* Current state of VIC_RST
27 to 25 reserved R - Reserved; do not modify
24 USB_RST_STAT W - Current state of DMA_RST
23 DMA_RST_STAT W - Current state of DMA_RST
22 MSCSS_QEI_RST_STAT W - Current state of MSCSS_QEI_RST
21 IVNSS_I2C_RST_STAT W - Current state of IVNSS_I2C_RST
20 MSCSS_TMR_RST_STAT R 1* Current state of MSCSS_TMR_RST
19 MSCSS_ADC_RST_STAT R 1* Current state of MSCSS_ADC_RST
18 MSCSS_PWM_RST_STAT R 1* Current state of MSCSS_PWM_RST
17 MSCSS_A2V_RST_STAT R 1* Current state of MSCSS_A2V_RST
16 IVNSS_LIN_RST_STAT R 1* Current state of IVNSS_LIN_RST
15 IVNSS_CAN_RST_STAT R 1* Current state of IVNSS_CAN_RST
14 IVNSS_A2V_RST_STAT R 1* Current state of IVNSS_A2V_RST

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Table 41. RST_ACTIVE_STATUS1 register bit description (RST_ACTIVE_STATUS1, address

D
D

D
R
R

R
A
0xFFFF 9154) …continued

A
FT
FT

F
* = reset value

D
D

R
R

A
Bit Symbol Access Value Description

FT
FT

D
13 SPI_RST_STAT R 1* Current state of SPI_RST

D
R
A
12 TMR_RST_STAT R 1* Current state of TMR_RST

FT
D
11 UART_RST_STAT R 1* Current state of UART_RST

R
A
10 GPIO_RST_STAT R 1* Current state of GPIO_RST
9 PESS_A2V_RST_STAT R 1* Current state of PESS_A2V_RST
8 GESS_A2V_RST_STAT R 1* Current state of GESS_A2V_RST
7 reserved R - Reserved; do not modify
6 SMC_RST_STAT R 1* Current state of SMC_RST
5 EMC_RST_STAT R 1* Current state of EMC_RST
4 FMC_RST_STAT R 1* Current state of FMC_RST
3 and 2 reserved R - Reserved; do not modify
1 CFID_RST_STAT R 1* Current state of CFID_RST
0 SCU_RST_STAT R 1* Current state of SCU_RST

4.4 RGU reset source registers

The reset source register indicates for each RGU reset output which specific reset input
caused it to go active.

POR reset

Remark: The POR_RST reset output of the RGU does not have a source register as it
can only be activated by the POR reset module.

RGU reset

The following reset source register description is applicable to the RGU reset output of the
RGU, which is activated by the RST_N input pin or the POR reset, see Table 10–92. To be
able to detect the source of the next PCR reset the register should be cleared by writing a
1 after read.

Table 42. RGU_RST_SRC register bit description (RGU_RST_SRC, address 0xFFFF 9404)
* = reset value
Bit Symbol Access Value Description
31 to 2 reserved R - Reserved; do not modify. Read as logic 0
1 RSTN_PIN R/W 0* Reset activated by external input reset
0 POR R/W 0* Reset activated by power-on-reset

PCR reset

The following reset source register description is applicable to the PCR reset output of the
RGU, which is activated by the Watchdog Timer or the RGU reset, see Table 10–92. To be
able to detect the source of the next PCR reset the register should be cleared by writing a
1 after read.

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Table 43. PCR_RST_SRC register bit description (PCR_RST_SRC, address 0xFFFF 9408)

R
R

R
A
A

A
* = reset value

FT
FT

F
D
D
Bit Symbol Access Value Description

R
R

A
A

FT
FT
31 to 4 reserved R - Reserved; do not modify. Read as logic 0

D
D
R
3 WDT_TMR R/W 0* Reset activated by Watchdog timer

A
FT
(WDT)

D
R
2 RGU R/W 0* Reset activated by RGU reset

A
1 to 0 reserved R - Reserved; do not modify. Read as logic 0

Cold reset

The following reset source register description is applicable for the COLD reset output of
the RGU, that is activated by the PCR reset, see Table 10–92. To be able to detect the
source of the next COLD reset the register should be cleared by writing a 0 after read.

Table 44. COLD_RST_SRC register bit description (COLD_RST_SRC, address

0xFFFF 940C)
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved; do not modify. Read as logic 0
4 PCR R/W 1* Reset activated by PCR reset
3 to 0 reserved R - Reserved; do not modify. Read as logic 0

Peripherals activated by cold reset

The following reset source register description is applicable to all the reset outputs of the
RGU that are activated by the COLD reset, see Table 10–92. To be able to detect the next
reset the register should be cleared by writing a 0 after read.

Table 45. XX_RST_SRC register bit description (WARM_RST_SRC to SMC_RST_SRC,

addresses 0xFFFF 9410 to 0xFFFF 9498)
* = reset value
Bit Symbol Access Value Description
31 to 6 reserved R - Reserved; do not modify. Read as logic 0
5 COLD R/W 1* Reset activated by COLD reset
4 to 0 reserved R - Reserved; do not modify. Read as logic 0

Peripherals activated by warm reset

The following reset source register description is applicable to all the reset outputs of the
RGU that are activated by the WARM reset, see Table 10–92. To be able to detect the
next reset the register should be cleared by writing a 0 after read.

Table 46. YY_RST_SRC register bit description (GESS_A2V_RST_SRC to AHB_RST_SRC,

address 0xFFFF 94A0 to 0xFFFF 9FF4)
* = reset value
Bit Symbol Access Value Description
31 to 7 reserved R - Reserved; do not modify. Read as logic 0
6 WARM R/W 1* Reset activated by WARM reset
5 to 0 reserved R - Reserved; do not modify. Read as logic 0

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4.5 RGU bus-disable register

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R

R
A
A

A
FT
FT

F
The BUS_DISABLE register prevents any register in the CGU from being written to.

D
D

R
R

A
A
Table 47. BUS_DISABLE register bit description (BUS_DISABLE, address 0xFFFF 9FF4)

FT
FT
* = reset value

D
D
R
A
Bit Symbol Access Value Description

FT
D
31 to 1 reserved R - Reserved; do not modify. Read as logic 0

R
A
0 RRBUS R/W Bus write-disable bit
1 No writes to registers within RGU are possible
(except the BUS_DISABLE register)
0* Normal operation

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Chapter 5: LPC29xx Power Management Unit (PMU)

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Rev. 00.06 — 17 December 2008 User manual

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1. How to read this chapter

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The implementation of some branch clocks for power control depends on the peripheral

D
R
and memory configuration of each LPC29xx part, see Table 5–48. All other branch clocks

A
are available in all LPC29xx parts.

Table 48. Branch clocks implemented in LPC29xx (x = CLK_CFG_ or CLK_STAT_)

Part SRAM Flash USB GPIO ADC
xRAM0 xRAM1 xFMC xUSB_CLK xUSB_ xUSB xGPIO xADC0, xADC1, xADC2,
I2C_CLK xADC0_ xADC1_ xADC2_
APB APB APB
LPC2917/19/01 yes yes yes no no no 0/1/2/3 no yes yes
LPC2921/23 yes no yes yes no yes 0/1/5 no yes yes
LPC2925 yes yes yes yes no yes 0/1/5 no yes yes
LPC2927/29 yes yes yes yes yes yes 0/1/2/3/5 yes yes yes
LPC2930 yes yes no yes yes yes 0/1/2/3/4/5 yes yes yes
LPC2939 yes yes yes yes yes yes 0/1/2/3/4/5 yes yes yes

2. Introduction
The PMU is part of the Power Control and Reset Subsystem (PCRSS) together with the
CGU0/1 (see Section 3–2) and RGU (see Section 4–2).

3. PMU functional description

Table 49. Branch clock overview
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Base clock Branch clock name/clock leafs Implemented switch on/off
mechanism
WAKE-UP AUTO RUN
BASE_SAFE_CLK CLK_SAFE 0 0 1

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Table 49. Branch clock overview …continued

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A
Legend:

A
FT
FT

F
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored

D
D

R
R
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored

A
A

FT
FT
‘+’ Indicates that the related register bit is readable and writable

D
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Base clock Branch clock name/clock leafs Implemented switch on/off

A
FT
mechanism

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WAKE-UP AUTO RUN

A
BASE_SYS_CLK CLK_SYS_CPU + + 1
CLK_SYS + + 1
CLK_SYS_PCR + + 1
CLK_SYS_FMC + + +
CLK_SYS_RAM0 + + +
CLK_SYS_RAM1 + + +
CLK_SYS_SMC + + +
CLK_SYS_GESS + + +
CLK_SYS_VIC + + +
CLK_SYS_PESS + + +
CLK_SYS_GPIO0 + + +
CLK_SYS_GPIO1 + + +
CLK_SYS_GPIO2 + + +
CLK_SYS_GPIO3 + + +
CLK_SYS_IVNSS_A + + +
CLK_SYS_MSCSS_A + + +
CLK_SYS_GPIO4 + + +
CLK_SYS_GPIO5 + + +
CLK_SYS_DMA + + +
CLK_SYS_USB + + +
BASE_PCR_CLK CLK_PCR_SLOW + + 1
BASE_IVNSS_CLK CLK_IVNSS_APB + + +
CLK_IVNSS_CANCA + + +
CLK_IVNSS_CANC0 + + +
CLK_IVNSS_CANC1 + + +
CLK_IVNSS_I2C0 + + +
CLK_IVNSS_I2C1 + + +
CLK_IVNSS_LIN0 + + +
CLK_IVNSS_LIN1 + + +
BASE_MSCSS_CLK CLK_MSCSS_APB + + +
CLK_MSCSS_MTMR0 + + +
CLK_MSCSS_MTMR1 + + +
CLK_MSCSS_PWM0 + + +
CLK_MSCSS_PWM1 + + +
CLK_MSCSS_PWM2 + + +
CLK_MSCSS_PWM3 + + +

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FT
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D

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R
R

R
A
A

A
FT
FT

FT
Table 49. Branch clock overview …continued

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R

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A
Legend:

A
FT
FT

F
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored

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D

R
R
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored

A
A

FT
FT
‘+’ Indicates that the related register bit is readable and writable

D
D
R
Base clock Branch clock name/clock leafs Implemented switch on/off

A
FT
mechanism

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WAKE-UP AUTO RUN

A
BASE_MSCSS_CLK CLK_MSCSS_ADC0_APB + + +
CLK_MSCSS_ADC1_APB + + +
CLK_MSCSS_ADC2_APB + + +
CLK_MSCSS_QEI + + +
BASE_OUT_CLK CLK_OUT_CLK + + +
BASE_UART_CLK CLK_UART0 + + +
CLK_UART1 + + +
BASE_SPI_CLK CLK_SPI0 + + +
CLK_SPI1 + + +
CLK_SPI2 + + +
BASE_TMR_CLK CLK_TMR0 + + +
CLK_TMR1 + + +
CLK_TMR2 + + +
CLK_TMR3 + + +
BASE_ADC_CLK CLK_ADC0 + + +
CLK_ADC1 + + +
CLK_ADC2 + + +
BASE_TEST_CLK CLK_TSSHELL - - -
BASE_USB_I2C_CLK CLK_USB_I2C + + +
BASE_USB_CLK CLK_USB + + +

The PMU allows definition of the power mode for each individual clock leaf. The clock
leaves are divided into branches as follows:

3.1 PMU clock-branch run mode

• the clock should be running
• the clock leaf should be disabled by the AHB automatic-switching setting
• the leaf should follow the system in entering sleep mode and waiting for a wake-up
All these settings can be controlled via the corresponding registers CLK_CFG_<leaf>.

The following clock leaves are exceptions to the general rule:

• CLK_SYS_CPU – cannot be disabled.

• CLK_SYS – cannot be disabled.
• CLK_SYS_PCR – cannot be disabled.

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Clocks that have been programmed to enter sleep mode follow the chosen setting of the

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A

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PD field in register PM. This means that with a single write-action all of these domains can

FT
FT

F
be set either to sleep or to wake up.

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A
A

FT
FT
Since application of configuration settings may not be instantaneous, the current setting

D
D
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can be read in register CLK_STAT_<leaf>. The registers CLK_STAT_<leaf> indicate the

A
FT
configured settings and in field STATEM_STAT the current setting. The possible states

D
R
are:

A
• run – normal clock enabled.
• wait – request has been sent to AHB to disable the clock but is waiting to be granted.
• sleep0 – clock disabled.
• sleep1 – clock disabled and request removed.

3.2 PMU clock branch overview

Within each clock branch the PMU keeps an overview of the power state of the separate
leaves. This indication can be used to determine whether the clock to a branch can be
safely disabled. This overview is kept in register BASE_STAT and contains one bit per
clock branch.

4. PMU register overview

The PMU registers have an offset to the base address PMU RegBase which can be found
in the memory map, see Section 2–2.

Table 50. PMU register overview (base address: FFFF A000h)

Address Access Reset value Name Description Reference
offset
000h R/W 0000 0000h PM Power mode register see Table 5–51
004h R 0000 1FFFh BASE_STAT Base-clock status register see Table 5–52
100h R/W 0000 0001h CLK_CFG_SAFE Safe-clock configuration register see Table 5–53
104h R 0000 0001h CLK_STAT_SAFE Safe-clock status register see Table 5–54
200h R/W 0000 0001h CLK_CFG_CPU CPU-clock configuration register see Table 5–53
204h R 0000 0001h CLK_STAT_CPU CPU-clock status register see Table 5–54
208h R/W 0000 0001h CLK_CFG_SYS System-clock configuration register see Table 5–53
20Ch R 0000 0001h CLK_STAT_SYS System-clock status register see Table 5–54
210h R/W 0000 0001h CLK_CFG_PCR System-clock_pcr configuration see Table 5–53
register
214h R 0000 0001h CLK_STAT_PCR System-clock_pcr status register see Table 5–54
218h R/W 0000 0001h CLK_CFG_FMC Flash-clock configuration register see Table 5–53
21Ch R 0000 0001h CLK_STAT_FMC Flash-clock status register see Table 5–54
220h R/W 0000 0001h CLK_CFG_RAM0 AHB clock to embedded memory see Table 5–53
controller 0 configuration register
224h R 0000 0001h CLK_STAT_RAM0 AHB clock to embedded memory see Table 5–54
controller 0 status register

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Table 50. PMU register overview (base address: FFFF A000h) …continued

D
D

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R

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A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

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R

A
A
228h R/W 0000 0001h CLK_CFG_RAM1 AHB clock to embedded memory see Table 5–53

FT
FT

D
controller 1 configuration register

D
R
A
22Ch R 0000 0001h CLK_STAT_RAM1 AHB clock to embedded memory see Table 5–54

FT
controller 1 status register

D
R
A
230h R/W 0000 0001h CLK_CFG_SMC AHB clock to Static Memory Controller see Table 5–53
configuration register
234h R 0000 0001h CLK_STAT_SMC AHB clock to Static Memory Controller see Table 5–54
status register
238h R/W 0000 0001h CLK_CFG_GESS AHB/APB clock to GeSS module see Table 5–53
configuration register
23Ch R 0000 0001h CLK_STAT_GESS AHB/APB clock to GeSS module see Table 5–54
status register
240h R/W 0000 0001h CLK_CFG_VIC AHB/DTL clock to interrupt controller see Table 5–53
configuration register
244h R 0000 0001h CLK_STAT_VIC AHB/DTL clock to interrupt controller see Table 5–54
status register
248h R/W 0000 0001h CLK_CFG_PESS AHB/APB clock to PeSS module see Table 5–53
configuration register
24Ch R 0000 0001h CLK_STAT_PESS AHB/APB clock to PeSS module see Table 5–54
status register
250h R/W 0000 0001h CLK_CFG_GPIO0 APB clock to General-Purpose I/O 0 see Table 5–53
configuration register
254h R 0000 0001h CLK_STAT_GPIO0 APB clock to General-Purpose I/O 0 see Table 5–54
status register
258h R/W 0000 0001h CLK_CFG_GPIO1 APB clock to General-Purpose I/O 1 see Table 5–53
configuration register
25Ch R 0000 0001h CLK_STAT_GPIO1 APB clock to General-Purpose I/O 1 see Table 5–54
status register
260h R/W 0000 0001h CLK_CFG_GPIO2 APB clock to General-Purpose I/O 2 see Table 5–53
configuration register
264h R 0000 0001h CLK_STAT_GPIO2 APB clock to General-Purpose I/O 2 see Table 5–54
status register
268h R/W 0000 0001h CLK_CFG_GPIO3 APB clock to General-Purpose I/O 3 see Table 5–53
status register
26Ch R 0000 0001h CLK_STAT_GPIO3 APB clock to General-Purpose I/O 3 see Table 5–54
status register
270h R/W 0000 0001h CLK_CFG_IVNSS_A AHB clock to IVNSS module- see Table 5–53
configuration register
274h R 0000 0001h CLK_STAT_IVNSS_A AHB clock to IVNSS module-status see Table 5–54
register
278h R/W 0000 0001h CLK_CFG_MSCSS_A AHB/APB clock to MSCSS module- see Table 5–53
configuration register
27Ch R 0000 0001h CLK_STAT_MSCSS_A AHB/APB clock to MSCSS module- see Table 5–54
status register
280h R/W 0000 0001h CLK_CFG_GPIO4 APB clock to General-Purpose I/O 4 see Table 5–53
status register

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Table 50. PMU register overview (base address: FFFF A000h) …continued

D
D

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R
R

R
A
A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

D
D

R
R

A
A
284h R 0000 0001h CLK_STAT_GPIO4 APB clock to General-Purpose I/O 4 see Table 5–54

FT
FT

D
status register

D
R
A
288h R/W 0000 0001h CLK_CFG_GPIO5 APB clock to General-Purpose I/O 5 see Table 5–53

FT
status register

D
R
A
28Ch R 0000 0001h CLK_STAT_GPIO5 APB clock to General-Purpose I/O 5 see Table 5–54
status register
290h R/W 0000 0001h CLK_CFG_DMA GPDMA clock configuration register see Table 5–53
294h R 0000 0001h CLK_STAT_DMA GPDMA clock status register see Table 5–54
298h R/W 0000 0001h CLK_CFG_USB USB register interface clock see Table 5–53
configuration register
29Ch R 0000 0001h CLK_STAT_USB USB register interface status register see Table 5–54
300h R/W 0000 0001h CLK_CFG_PCR_IP IP clock to PCR module configuration- see Table 5–53
register
304h R 0000 0001h CLK_STAT_PCR_IP IP clock to PCR module-status see Table 5–54
register
400h R/W 0000 0001h CLK_CFG_IVNSS_APB APB clock to IVNSS module- see Table 5–53
configuration register
404h R 0000 0001h CLK_STAT_IVNSS_APB APB clock to IVNSS module status- see Table 5–54
register
408h R/W 0000 0001h CLK_CFG_CANCA IP clock to CAN gateway acceptance- see Table 5–53
filter configuration register
40Ch R 0000 0001h CLK_STAT_CANCA IP clock to CAN gateway acceptance- see Table 5–54
filter status register
410h R/W 0000 0001h CLK_CFG_CANC0 IP clock to CAN gateway 0 see Table 5–53
configuration register
414h R 0000 0001h CLK_STAT_CANC0 IP clock to CAN gateway 0 status see Table 5–54
register
418h R/W 0000 0001h CLK_CFG_CANC1 IP clock to CAN gateway 1 see Table 5–53
configuration register
41Ch R 0000 0001h CLK_STAT_CANC1 IP clock to CAN gateway 1 status see Table 5–54
register
420h R/W 0000 0001h CLK_CFG_I2C0 IP clock to I2C0 configuration register see Table 5–53
424h R 0000 0001h CLK_STAT_I2C0 IP clock to I2C0 status register see Table 5–54
428h R/W 0000 0001h CLK_CFG_I2C1 IP clock to I2C1 configuration register see Table 5–53
42Ch R 0000 0001h CLK_STAT_I2C1 IP clock to I2C1 status register see Table 5–54
430h - - - - reserved -
43Ch
440h R/W 0000 0001h CLK_CFG_LIN0 IP clock to LIN controller 0 see Table 5–53
configuration register
444h R 0000 0001h CLK_STAT_LIN0 IP clock to LIN controller 0 status see Table 5–54
register
448h R/W 0000 0001h CLK_CFG_LIN1 IP clock to LIN controller 1 see Table 5–53
configuration register
44Ch R 0000 0001h CLK_STAT_LIN1 IP clock to LIN controller 1 status see Table 5–54
register

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Table 50. PMU register overview (base address: FFFF A000h) …continued

D
D

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R
R

R
A
A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

D
D

R
R

A
A
450h - - - reserved -

FT
FT

D
-4FCh

D
R
A
500h R/W 0000 0001h CLK_CFG_MSCSS_APB APB clock to MSCSS module- see Table 5–53

FT
configuration register

D
R
A
504h R 0000 0001h CLK_STAT_MSCSS_APB APB clock to MSCSS module-status see Table 5–54
register
508h R/W 0000 0001h CLK_CFG_MTMR0 IP clock to timer 0 in MSCSS see Table 5–53
configuration register
50Ch R 0000 0001h CLK_STAT_MTMR0 IP clock to timer 0 in MSCSS status see Table 5–54
register
510h R/W 0000 0001h CLK_CFG_MTMR1 IP clock to timer 1 in MSCSS see Table 5–53
configuration register
514h R 0000 0001h CLK_STAT_MTMR1 IP clock to timer 1 in MSCSS status see Table 5–54
register
518h R/W 0000 0001h CLK_CFG_PWM0 IP clock to PWM 0 in MSCSS see Table 5–53
configuration register
51Ch R 0000 0001h CLK_STAT_PWM0 IP clock to PWM 0 in MSCSS status see Table 5–54
register
520h R/W 0000 0001h CLK_CFG_PWM1 IP clock to PWM 1 in MSCSS see Table 5–53
configuration register
524h R 0000 0001h CLK_STAT_PWM1 IP clock to PWM 1 in MSCSS status see Table 5–54
register
528h R/W 0000 0001h CLK_CFG_PWM2 IP clock to PWM 2 in MSCSS see Table 5–53
configuration register
52Ch R 0000 0001h CLK_STAT_PWM2 IP clock to PWM 2 in MSCSS status see Table 5–54
register
530h R/W 0000 0001h CLK_CFG_PWM3 IP clock to PWM 3 in MSCSS see Table 5–53
configuration register
534h R 0000 0001h CLK_STAT_PWM3 IP clock to PWM 3 in MSCSS status see Table 5–54
register
538h R/W 0000 0001h CLK_CFG_ADC0_APB APB clock to ADC 0 in MSCSS see Table 5–53
configuration register
53Ch R 0000 0001h CLK_STAT_ADC0_APB APB clock to ADC 0 in MSCSS status see Table 5–54
register
540h R/W 0000 0001h CLK_CFG_ADC1_APB APB clock to ADC 1 in MSCSS see Table 5–53
configuration register
544h R 0000 0001h CLK_STAT_ADC1_APB APB clock to ADC 1 in MSCSS status see Table 5–54
register
548h R/W 0000 0001h CLK_CFG_ADC2_APB APB clock to ADC 2 in MSCSS see Table 5–53
configuration register
54Ch R 0000 0001h CLK_STAT_ADC2_APB APB clock to ADC 2 in MSCSS status see Table 5–54
register
550h R/W 0000 0001h CLK_CFG_QEI_APB APB clock to QEI in MSCSS see Table 5–53
configuration register
554h R 0000 0001h CLK_STAT_QEI_APB APB clock to QEI in MSCSS status see Table 5–54
register

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Table 50. PMU register overview (base address: FFFF A000h) …continued

D
D

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R
R

R
A
A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

D
D

R
R

A
A
558h - R/W 0000 0001h reserved Reserved -

FT
FT

D
5FFh

D
R
A
600h R 0000 0001h CLK_CFG_OUT_CLK clock out configuration register see Table 5–53

FT
D
604h R/W 0000 0001h CLK_STAT_OUT_CLK clock out status register see Table 5–54

R
A
700h R/W 0000 0001h CLK_CFG_UART0 IP clock to UART-0 configuration see Table 5–53
register
704h R 0000 0001h CLK_STAT_UART0 IP clock to UART-0 status register see Table 5–54
708h R/W 0000 0001h CLK_CFG_UART1 IP clock to UART 1 configuration see Table 5–53
register
70Ch R 0000 0001h CLK_STAT_UART1 IP clock to UART 1 status register see Table 5–54
800h R/W 0000 0001h CLK_CFG_SPI0 IP clock to SPI 0 configuration register see Table 5–53
804h R 0000 0001h CLK_STAT_SPI0 IP clock to SPI 0 status register see Table 5–54
808h R/W 0000 0001h CLK_CFG_SPI1 IP clock to SPI 1 configuration register see Table 5–53
80Ch R 0000 0001h CLK_STAT_SPI1 IP clock to SPI 1 status register see Table 5–54
810h R/W 0000 0001h CLK_CFG_SPI2 IP clock to SPI 2 configuration register see Table 5–53
814h R 0000 0001h CLK_STAT_SPI2 IP clock to SPI 2 status register see Table 5–54
900h R/W 0000 0001h CLK_CFG_TMR0 IP clock to Timer 0 configuration see Table 5–53
register
904h R 0000 0001h CLK_STAT_TMR0 IP clock to Timer 0 status register see Table 5–54
908h R/W 0000 0001h CLK_CFG_TMR1 IP clock to Timer 1 configuration see Table 5–53
register
90Ch R 0000 0001h CLK_STAT_TMR1 IP clock to Timer 1 status register see Table 5–54
910h R/W 0000 0001h CLK_CFG_TMR2 IP clock to Timer 2 configuration see Table 5–53
register
914h R 0000 0001h CLK_STAT_TMR2 IP clock to Timer 2 status register see Table 5–54
918h R/W 0000 0001h CLK_CFG_TMR3 IP clock to Timer 3 configuration see Table 5–53
register
91Ch R 0000 0001h CLK_STAT_TMR3 IP clock to Timer 3 status register see Table 5–54
A00h R/W 0000 0001h CLK_CFG_ADC0 IP clock to ADC 0 status register see Table 5–53
A04h R 0000 0001h CLK_STAT_ADC0 IP clock to ADC 0 status register see Table 5–54
A08h R/W 0000 0001h CLK_CFG_ADC1 IP clock to ADC 1 status register see Table 5–53
A0Ch R 0000 0001h CLK_STAT_ADC1 IP clock to ADC 1 status register see Table 5–54
A10h R/W 0000 0001h CLK_CFG_ADC2 IP clock to ADC 2 configuration see Table 5–53
register
A14h R 0000 0001h CLK_STAT_ADC2 IP clock to ADC 2 status register see Table 5–54
B00h R/W 0000 0001h CLK_CFG_TSSHELL IP clock to test clock configuration see Table 5–53
register.
Remark: This is an internal clock
used for testing only. It is running at
start-up and should be disabled for
power-down mode using this register.
B04h R 0000 0001h CLK_STAT_TSSHELL IP clock to test clock status register see Table 5–54
C00h R/W 0000 0001h CLK_CFG_USB_I2C IP clock to USB I2C configuration see Table 5–53
register
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Table 50. PMU register overview (base address: FFFF A000h) …continued

D
D

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R
R

R
A
A

A
Address Access Reset value Name Description Reference

FT
FT

F
offset

D
D

R
R

A
A
C04h R 0000 0001h CLK_STAT_USB_I2C IP clock to USB I2C status register see Table 5–54

FT
FT

D
D
D00h R/W 0000 0001h CLK_CFG_USB_CLK IP clock to USB CLK configuration see Table 5–53

R
A
register

FT
D
D04h R 0000 0001h CLK_STAT_USB_CLK IP clock to USB CLK status register see Table 5–54

R
A
FF8h - 0000 0000h reserved Reserved
FFCh - A0B6 0000h reserved Reserved

4.1 Power mode register (PM)

This register contains a single bit, PD, which when set disables all output clocks with
wake-up enabled. Clocks disabled by the power-down mechanism are reactivated when a
wake-up interrupt is detected or when a 0 is written to the PD bit.

Table 51. PM register bit description (PM, address 0xFFFF A000)

* = reset value
Bit Symbol Access Value Description
31 to 1 reserved R - Reserved; do not modify. Read as logic 0
0 PD R/W Initiate power-down mode:
1 Clocks with wake-up mode enabled
(WAKEUP=1) are disabled
0* Normal operation

4.2 Base-clock status register

Each bit in this register indicates whether the specified base clock can be safely switched
off. A logic zero indicates that all branch clocks generated from this base clock are
disabled, so the base clock can also be switched off. A logic 1 value indicates that there is
still at least one branch clock running.

Table 52. BASE_STAT register bit description (BASE_STAT, address 0xFFFF A004)
* = reset value
Bit Symbol Access Value Description
31 to 13 reserved R - Reserved; do not modify. Read as logic 0
12 BASE12_STA R 1* Indicator for BASE_USB_CLK
11 BASE11_STAT R 1* Indicator for BASE_USB_I2C_CLK
10 BASE10_STAT R 1* Indicator for BASE_CLK_TESTSHELL
9 BASE9_STAT R 1* Indicator for BASE_ADC_CLK
8 BASE8_STAT R 1* Indicator for BASE_TMR_CLK
7 BASE7_STAT R 1* Indicator for BASE_SPI_CLK
6 BASE6_STAT R 1* Indicator for BASE_UART_CLK
5 BASE5_STAT R 1* Indicator for BASE_OUT_CLK
4 BASE4_STAT R 1* Indicator for BASE_MSCSS_CLK
3 BASE3_STAT R 1* Indicator for BASE_IVNSS_CLK

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Table 52. BASE_STAT register bit description (BASE_STAT, address 0xFFFF A004)

D
D

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R
R

R
A
* = reset value

A
FT
FT

F
Bit Symbol Access Value Description

D
D

R
R

A
A
2 BASE2_STAT R 1* Indicator for BASE_PCR_CLK

FT
FT

D
D
1 BASE1_STAT R 1* Indicator for BASE_SYS_CLK

R
A
FT
0 BASE0_STAT R 1* Indicator for BASE_SAFE_CLK

D
R
A
4.3 PMU clock configuration register for output branches
Each generated output clock from the PMU has a configuration register.

Table 53. CLK_CFG_XXX register bit description (CLK_CFG_SAFE to CLK_CFG_USB_CLK,

addresses 0xFFFF A100 to 0xFFFF AD00)
* = reset value
Bit Symbol Access Value Description
31 to 3 reserved R - Reserved; do not modify. Read as logic 0
2 WAKEUP[1] R/W 1 The branch clock is ’wake-up enabled’. When
the PD bit in the Power Mode register (see
Section 5–4.1) is set, and clocks which are
wake-up enabled are switched off. These
clocks will be switched on if a wake-up event is
detected or if the PD bit is cleared. If register bit
AUTO is set, the AHB disable protocol must
complete before the clock is switched off.
0* PD bit has no influence on this branch clock
1 AUTO[1] R/W 1 Enable auto (AHB disable mechanism). The
PMU initiates the AHB disable protocol before
switching the clock off. This protocol ensures
that all AHB transactions have been completed
before turning the clock off
0* No AHB disable protocol is used.
0 RUN[2] R/W 1* The WAKEUP, PD (and AUTO) control bits
determine the activation of the branch clock. If
register bit AUTO is set the AHB disable
protocol must complete before the clock is
switched off.
0 Branch clock switched off

[1] Tied off to logic LOW for some branch clocks. All writes are ignored for those with tied bits.
[2] Tied off to logic HIGH for some branch clocks. All writes are ignored for those with tied bits.

4.4 Status register for output branch clock

Like the configuration register, each generated output clock from the PMU has a status
register. When the configuration register of an output clock is written to the value of the
actual hardware signals may not be updated immediately. This may be due to the auto or
wake-up mechanism. The status register shows the current value of these signals.

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Chapter 5: LPC29xx Power Management Unit (PMU)

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Table 54. CLK_STAT_XXX register bit description (CLK_STAT_SAFE to

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CLK_STAT_USB_CLK, addresses 0xFFFF A104 to 0xFFFF AD04)

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* = reset value

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Bit Symbol Access Value Description

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31 to 10 reserved R - Reserved; do not modify. Read as logic 0

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9 and 8 SM R Status of state machine controlling the clock-

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enable signal

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00* RUN = clock enabled
01 WAIT = request sent to AHB master to disable
clock. Waiting for AHB master to grant the
request
10 SLEEP1 = clock disabled and request removed
11 SLEEP0 = clock disabled
7 to 3 reserved R - Reserved; do not modify. Read as logic 0
2 WS R Wake-up mechanism enable status
1 Enabled
0* Not enabled
1 AS R Auto (AHB disable mechanism) enable status
1 Enabled
0* Not enabled
0 RS R Run-enable status
1* Enabled
0 Not enabled

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. See Table 6–55 for available

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GPIO pins and registers that are part specific.

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Table 55. LPC29xx SCU usage
Part number GPIO GPIO GPIO GPIO GPIO GPIO USB D+/- USB
port 0 port 1 port 2 port 3 port 4 port 5 port SSMM3/
selection SMP3
registers registers
LPC2917/19/01 P0[31:0] P1[31:0] P2[27:0] P3[15:0] - - - no
LPC2921/23/25 P0[31:0] P1[27:0] - - - - for P5[19:18] yes
LPC2927/29 P0[31:0] P1[27:0] P2[27:0] P3[15:0] - - for P5[19:18] yes
LPC2930 P0[31:0] P1[27:0] P2[27:0] P3[15:0] P4[23:0] P5[15:0] for P[19:16] yes
LPC2939 P0[31:0] P1[27:0] P2[27:0] P3[15:0] P4[23:0] P5[15:0] for P[19:16] yes

2. Introduction
The SCU controls some device functionality that is not part of any other block. Settings
made in the SCU influence the complete system.

The SCU manages the port-selection registers. The function of each I/O pin can be
configured. Not all peripherals of the device can be used at the same time, so the desired
functions are chosen by selecting a function for each I/O pin.

In addition, memory mapping features and AHB priority settings are controlled by the
SCU.

3. SCU register overview

The System Control Unit registers are shown in Table 6–56.

The System Control Unit registers have an offset to the base address SCU RegBase
which can be found in the memory map (see Section 2–2).

Table 56. SCU register overview (base address: 0xE000 1000)

Name Address Access Reset value Description Reference
offset
SFSP0_BASE 000h R/W 0000 0000h Function-select port 0 base Table 6–57
address
SFSP1_BASE 100h R/W 0000 0000h Function-select port 1 base Table 6–57
address
SFSP2_BASE 200h R/W 0000 0000h Function-select port 2 base Table 6–57
address
SFSP3_BASE 300h R/W 0000 0000h Function-select port 3 base Table 6–57
address

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Table 56. SCU register overview (base address: 0xE000 1000) …continued

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Name Address Access Reset value Description Reference

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offset

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SFSP4_BASE 400h R/W 0000 0000h Function-select port 4 base Table 6–57

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address

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SFSP5_BASE 500h R/W 0000 0000h Function-select port 5 base Table 6–57

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address

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SFSP5_16 540h R/W 0000 0000h Function select port 5 pin Table 6–59
16 (USB port 2, USB_D−2)
- 544h - 0000 0000h reserved -
SFSP5_18 548h R/W 0000 0000h Function select port 5 pin Table 6–60
18 (USB port 2, USB_D−1)
- 54Ch - 0000 0000h - -
SEC_DIS B00h R/W Security disable register Table 6–61
SEC_STA B04h R Security status register Table 6–62
SSMM0 C00h R/W 2000 0000h Shadow memory mapping Table 6–63
register for ARM
SSMM1 C04h R/W 2000 0000h Shadow memory mapping Table 6–63
register for master DMA0
SSMM2 C08h R/W 2000 0000h Shadow memory mapping Table 6–63
register for master DMA1
SSMM3 C0Ch R/W 2000 0000h Shadow memory mapping Table 6–63
register for master USB
SMP0 D00h R 0000 0000h Master priority ARM
SMP1 D04h R 0000 0000h Master priority DMA0
SMP2 D08h R 0000 0000h Master priority DMA1
SMP3 D0Ch R 0000 0000h Master priority USB
- FF4h R 0000 0000h Reserved; do not modify.
Read as logic 0
- FFCh R A09B 2000h Reserved; do not modify.
Read as logic 0

3.1 SCU port function select registers

The port function select register configures the pin functions individually on the
corresponding I/O port. For an overview of pinning, see Section 11–2. Each port pin has
its individual register. Each port has its SFSPn_BASE register as defined above in
Table 6–56. n runs from 0 to 4, m runs from 0 to 31. For port 5, m runs from 0 to 15.

Table 6–57 shows the address locations of the SFSPn_m registers within a port memory
space as indicated by SFSPn_BASE.

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Table 57. SCU port function select register overview (base address: 0xE000 1000 (port 0),

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0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400

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F
(port4), 0xE000 1500 (port 5))

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Ports not pinned out are reserved; do not modify, read as logic 0.

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Name Address Access Reset value Description Reference

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offset

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SFSPn_0 00h R/W 0000 0000h Function-select port n, pin see

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0 register Table 6–58

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SFSPn_1 04h R/W 0000 0000h Function-select port n, pin see
1 register Table 6–58
SFSPn_2 08h R/W 0000 0000h Function-select port n, pin see
2 register Table 6–58
SFSPn_3 0Ch R/W 0000 0000h Function-select port n, pin see
3 register Table 6–58
SFSPn_4 10h R/W 0000 0000h Function-select port n, pin see
4 register Table 6–58
SFSPn_5 14h R/W 0000 0000h Function-select port n, pin see
5 register Table 6–58
SFSPn_6 18h R/W 0000 0000h Function-select port n, pin see
6 register Table 6–58
SFSPn_7 1Ch R/W 0000 0000h Function-select port n, pin see
7 register Table 6–58
SFSPn_8 20h R/W 0000 0000h Function-select port n, pin see
8 register Table 6–58
SFSPn_9 24h R/W 0000 0000h Function-select port n, pin see
9 register Table 6–58
SFSPn_10 28h R/W 0000 0000h Function-select port n, pin see
10 register Table 6–58
SFSPn_11 2Ch R/W 0000 0000h Function-select port n, pin see
11 register Table 6–58
SFSPn_12 30h R/W 0000 0000h Function-select port n, pin see
12 register Table 6–58
SFSPn_13 34h R/W 0000 0000h Function-select port n, pin see
13 register Table 6–58
SFSPn_14 38h R/W 0000 0000h Function-select port n, pin see
14 register Table 6–58
SFSPn_15 3Ch R/W 0000 0000h Function-select port n, pin see
15 register Table 6–58
SFSPn_16 40h R/W 0000 0000h Function-select port n, pin see
16 register Table 6–58
SFSPn_17 44h R/W 0000 0000h Function-select port n, pin see
17 register Table 6–58
SFSPn_18 48h R/W 0000 0000h Function-select port n, pin see
18 register Table 6–58
SFSPn_19 4Ch R/W 0000 0000h Function-select port n, pin see
19 register Table 6–58
SFSPn_20 50h R/W 0000 0000h Function-select port n, pin see
20 register Table 6–58
SFSPn_21 54h R/W 0000 0000h Function-select port n, pin see
21 register Table 6–58
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Table 57. SCU port function select register overview (base address: 0xE000 1000 (port 0),

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0xE000 1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400

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F
(port4), 0xE000 1500 (port 5)) …continued

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Ports not pinned out are reserved; do not modify, read as logic 0.

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Name Address Access Reset value Description Reference

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offset

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SFSPn_22 58h R/W 0000 0000h Function-select port n, pin see

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22 register Table 6–58

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SFSPn_23 5Ch R/W 0000 0000h Function-select port n, pin see
23 register Table 6–58
SFSPn_24 60h R/W 0000 0000h Function-select port n, pin see
24 register Table 6–58
SFSPn_25 64h R/W 0000 0000h Function-select port n, pin see
25 register Table 6–58
SFSPn_26 68h R/W 0000 0000h Function-select port n, pin see
26 register Table 6–58
SFSPn_27 6Ch R/W 0000 0000h Function-select port n, pin see
27 register Table 6–58
SFSPn_28 70h R/W 0000 0000h Function-select port n, pin see
28 register Table 6–58
SFSPn_29 74h R/W 0000 0000h Function-select port n, pin see
29 register Table 6–58
SFSPn_30 78h R/W 0000 0000h Function-select port n, pin see
30 register Table 6–58
SFSPn_31 7Ch R/W 0000 0000h Function-select port n, pin see
31 register Table 6–58

Table 6–58 shows the bit assignment of the SFSPn_m registers (n runs from 0 to 4, m
runs from 0 to 31. For port 5, m runs from 0 to 15).

Remark: Note that on Reset the ADC pins P0[23] to P0[8] are set to digital inputs without
internal pull-up/down on reset. This guarantees that these pins are 5 V tolerant after reset,
even though the analog inputs to ADC1 and ADC2 are not. The default pad type is analog
input for all other port pins (except P5[19:16]).

Table 58. SFSPn_m register bit description (base address: 0xE000 1000 (port 0), 0xE000
1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4),
0xE000 1500 (port 5))
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved. Read as logic 0
4 to 2 PAD_TYPE[1] R/W Input pad type
000*[2] Analog input[3]
001 Digital input without internal pull up/down
010 Not allowed
011 Digital input with internal pull up[4]
100 Not allowed
101 Digital input with internal pull down
110 Not allowed
111 Digital input with bus keeper

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Table 58. SFSPn_m register bit description (base address: 0xE000 1000 (port 0), 0xE000

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1100 (port 1), 0xE000 1200 (port 2), 0xE000 1300 (port3), 0xE000 1400 (port4),

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F
0xE000 1500 (port 5)) …continued

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* = reset value

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Bit Symbol Access Value Description

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1 to 0 FUNC_SEL[1:0] R/W Function-select; for the function-to-port-pin

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mapping tables[5]

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00* Select pin function 0
01 Select pin function 1
10 Select pin function 2
11 Select pin function 3

[1] These bits control the input section of the I/O buffer. The FUNC_SEL bits will define if a pin is input or
output depending on the function selected. For GPIO mode the direction is controlled by the direction
register, see Table 16–203. Note that input pad type must be set correctly in addition to the FUNC_SEL bits
also for functions of type input.
[2] The reset value for port pins P0[23:8] is 001 (digital input without internal pull-up/down). This guarantees
that the ADC pins are 5 V tolerant after reset even though the analog pad of ADC1 and ADC2 is not 5 V
tolerant.
[3] The ‘analog’ connection towards the ADC is always enabled. Use PAD_TYPE = 000 when used as analog
input to avoid the input buffer oscillating on slow analog-signal transitions or noise. The digital input buffer is
switched off.
[4] When pull-up is activated the input is not 5 V -tolerant.
[5] Each pin has up to four functions.

Setting the FUNC_SEL bits in the SFSP5_16 register also determines the function of port
5[17]. If the USB_D−2 function is selected for P5[16], P5[17] is automatically assigned to
the USB_D+2 function. If P5[16] is GPIO, P5[17] is assigned to GPIO as well.

Table 59. SFSP5_16 function select register bit description (SFSP5_16, address
0xE000 1540)
Bit Symbol Access Value Description
31 to 2 reserved R - Reserved. Read as
logic 0
1 to 0 FUNC_SEL[1:0] R/W Function-select; for the
function-to-port-pin
mapping tables
00* Select pin function GPIO
on P5[16]
01 Select pin USB_D−2
10 reserved
11 reserved

Setting the FUNC_SEL bits in the SFSP5_18 register also determines the function of port
5[19]. If the USB_D−1 function is selected for P5[18], P5[19] is automatically assigned to
the USB_D+1 function. If P5[18] is selected GPIO, P5[19] is assigned to GPIO as well.

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Table 60. SFSP5_18 function select register bit description (SFSP_5_18, address

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0xE000 1548)

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Bit Symbol Access Value Description

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31:5 - - - reserved

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4 VBUS R/W <tbd>

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0 port 1 in host or device

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mode

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1 port 1 in OTG mode
3 to 2 - - - reserved
1 to 0 FUNC_SEL[1:0] R/W Function-select; for the
function-to-port-pin mapping
tables
00* Select pin function GPIO on
P5[18]
01 Select pin USB_D−1
10 reserved
11 reserved

3.1.1 Functional description

The digital I/O pins of the device are divided into four ports. For each pin of these ports
one out of four functions can be chosen. Refer to Figure 6–15 for a schematic
representation of an I/O-pin. The I/O functionality is dependent on the application.

The function of an I/O can be changed ‘on the fly’ during run-time. By default it is assigned
to function 0, which is the GPIO. For each pin of these ports a programmable pull-up and
pull-down resistor (R) is present.

Remark: Even though the default function is GPIO, the pad type has to be set to digital in
the SFSPn_m registers in order to use the GPIO functionality (see Table 6–58).

SFSPx_y
Vdd
RESERVED PAD_TYPE FUNC_SEL

Function 0
Function 1
Function 2
Function 3

Vss Vss

Fig 15. Schematic representation of an I/O pin

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3.2 JTAG security registers

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Table 61. Security disable register bit description (SEC_DIS, address 0xE000 1B00)

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Bit Symbol Access Value Description

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31:2 - - - reserved

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1 DIS R/W JTAG security enable/disable

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1 Disables JTAG security and clears bit 1 on SEC_STA

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0 enables JTAG security
0 - - - reserved

Table 62. Security disable register bit description (SEC_STA, address 0xE000 1B04)
Bit Symbol Access Value Description
31:2 - - - reserved
1 DIS R JTAG security
1 JTAG security enabled
0 JTAG security disabled
0 - - - reserved

3.3 Shadow memory mapping registers

The shadow memory mapping register defines which part of the memory region is present
in the shadow memory area. The shadow memory mapping start address is the pointer
within a region indicating the shadowing to the shadow area starting at location 0000
0000h. In this way a whole region or only a part of the flash, SRAM or external memory
bank can be remapped to the shadow area.

The SSMM0 register defines the memory mapping seen by the ARM CPU master, the
SSMM1 and SSMM2 register defines the memory mapping for the DMA0 and DMA1
masters, and the SSMM3 register for the USB master.

Table 63. SSMMx register bit description (SSMM0/1/2/3, addresses: 0xE000 1C00, 0xE000
1C04, 0xE000 1C08, 0xE000 1C0C)
* = reset value
Bit Symbol Access Value Description
31 to 10 SMMSA[21:0] R/W 2000 0000h* shadow memory map start address;
memory start address for mapping (a part
of) a region to the shadow area; the start
address is aligned on 1 kB boundaries and
therefore the lowest 10 bits must be always
logic 0
9 to 0 reserved - - reserved; do not modify, read as logic 0,
write
as logic 0

3.4 AHB master priority registers

By default, AHB access is scheduled round-robin. However, the AHB access priority of
each of the AHB bus masters can be set by writing the priority integer value (highest
priority = 1, lowest priority = 4) to the master’s priority register SMPn.

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All masters with the same priority are scheduled on a round-robin basis.

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Table 64. SMPx register bit description (SMP0/1/2/3, addresses: 0xE000 1D00 (ARM),

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0xE000 1D04 (DMA0), 0xE000 1D08 (DMA1), 0xE000 1D0C (USB))

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* = reset value

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Bit Symbol Access Value Description

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31:3 - - - reserved

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2:0 PRIO R/W 0h AHB priority (1: highest, 4: lowest)

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1. Introduction

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The CFID module contains registers that show and control the functionality of the chip. It

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contains an ID to identify the silicon and registers containing information about the

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features enabled/disabled on the chip.

2. CFID register overview

The CFID registers are shown in Table 7–65.

The CFID registers have an offset to the base address CFID RegBase which can be
found in the memory map.

Table 65. CFID register overview (Base address: 0xE000 0000)

Address Access Reset value Name Description Reference
offset
000h R <tbd> CHIPID <tbd> see
Table 7–66
100h R <tbd> FEAT0 <tbd> see
Table 7–67
104h R <tbd> FEAT1 <tbd> see
Table 7–68
108h R <tbd> FEAT2 <tbd> see
Table 7–69
10Ch R <tbd> FEAT3 <tbd> see
Table 7–70
FF4h R <tbd> reserved Reserved
FFCh R <tbd> reserved Reserved

2.1 Chip identification

Contains the Unique ID of the LPC29xx parts. The value will be equal to the JTAG/IEEE
1149.1 boundary-scan ID.

Table 7–66 shows the bit assignment of the CHIPID register.

Table 66. CHIPID register bit description (CHIPID, address 0xE000 0000)
Bit Symbol Access Value Description
31 to 28 VERSION R <tbd> <tbd>
27 to 12 PART_NR R <tbd> <tbd>
11 to 1 MANUFACTURER_ID[10:0] R <tbd> <tbd>
0 reserved R <tbd> <tbd>

2.2 Package information register

This contains a code to identify the package of the LPC2917/19.

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Table 7–67 shows the bit assignment of the FEAT0 register.

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Table 67. FEAT0 register bit description (FEAT0, address 0xE000 0100)

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Bit Symbol Access Value Description

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31 to 4 reserved R - Reserved; do not modify. Read as

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logic 0

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3 to 0 PACKAGE_ID[3:0] R <tbd> <tbd>

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<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>

2.3 Configuration register 1

Table 7–68 shows the bit assignment of the FEAT1 register.

Table 68. FEAT 1 register bit description (FEAT1, address 0xE000 0104)
Bit Symbol Access Value Description
31 to 29 R <tbd> <tbd>
28 to 24 R <tbd> <tbd>
23 to 21 R <tbd> <tbd>
20 to 16 R <tbd> <tbd>
15 to 8 R <tbd> <tbd>
7 to 0 R <tbd> <tbd>

2.4 Configuration register 2

This contains a code to identify the configured type of the CFID module. It can be used by
software to detect different hardware versions of the device. Table 7–69 shows the bit
assignment of the FEAT2 register.

Table 69. FEAT2 register bit description (FEAT2, address 0xE000 0108)
Bit Symbol Access Value Description
31 to R <tbd> <tbd>
30
29 to 28 R <tbd> <tbd>
27 to 26 R <tbd> <tbd>
25 to 24 R <tbd> <tbd>
23 to 16 R <tbd> <tbd>
15 to 8 R <tbd> <tbd>
7 to 0 R <tbd> <tbd>

2.5 Configuration register 3

This contains a code to identify the configured type of the CFID module. It can be used by
software to detect different hardware versions of the device. Table 7–69 shows the bit
assignment of the FEAT3 register.

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Table 70. FEAT3 register bit description (FEAT3, address 0xE000 010C)

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Bit Symbol Access Value Description

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31 JTAGSEC R The setting of this bit is determined by the

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setting of the JTAG security in the flash

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index sector (see Section 28–2.6.3).

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1 JTAG security enabled. No JTAG access.

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0 JTAG security disabled.

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30 R 1 <tbd>
29 to 28 R 1 <tbd>
27 to 26 R 1 <tbd>
25 to 24 R 1 <tbd>
23 to 16 R 1 <tbd>
15 to 8 R 1 <tbd>
7 to 0 R 1 <tbd>

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. Not all event sources are

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connected to pins. Table 8–71 shows the event router connections that vary for different

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LPC29xx parts.

Table 71. Available external event router connections

Part External USB CAN/LIN (n = 0,1) I2C SPI UART
interrupt (n = 0,1) (m = 0,1, (n = 0,1)
pins 2)
LPC2921/23/25 EI[0:3] USB_D+1 RXDCn; RXDLn SCLn SDIm RXDn
LPC2917/19/01 EI[0:7] - RXDCn; RXDLn SCLn SDIm RXDn
LPC2927/29 EI[0:7] USB_D+1; RXDCn; RXDLn SCLn SDIm RXDn
USB_SCL1
LPC2930 EI[0:7] USB_D+1/2; RXDCn; RXDLn SCLn SDIm RXDn
USB_SCL1
LPC2939 EI[0:7] USB_D+1/2; RXDCn; RXDLn SCLn SDIm RXDn
USB_SCL1

2. Event router functional description

The Event Router provides bus-controlled routing of input events to the VIC for use as
interrupt or wake-up signals to the CGU. Event inputs are connected to internal
peripherals and to external interrupt pins. All event inputs are described in Table 8–72.

The CAN and LIN receive-pin events can be used as extra external interrupt pins when
CAN and/or LIN functionality is not needed.

A schematic representation of the Event Router is shown in Figure 8–16.

wake-up
(CGU)

EVENT INPUT MASK Interrupt

(VIC)
PEND
RSR
CLR

SET
INT

INT

APR ATR MASK

MASK MASK
SET CLR

Fig 16. Schematic representation of the Event Router

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Input events are processed in event slices; one for each event signal. Each of these slices

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generates one event signal and is visible in the RSR (Raw Status Register). These events

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are then AND-ed with enables from the MASK register to give PEND (PENDing register)

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event status. If one or more events are pending the output signals are active.

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An event input slice is controlled through bits in the APR (Activation Polarity Register), the

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ATR (Activation Type Register), INT_SET (INTerrupt SET) and INT_CLR (INTerrupt

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CLeaR).

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• The polarity setting (APR) conditionally inverts the interrupt input event.
• The activation type setting (ATR) selects between latched/edge or direct/level event.
• The resulting interrupt event is visible through a read-action in the RSR.
• The RSR is AND-ed with the MASK register and the result is visible in the PEND
register.
• The wake-up (CGU) and interrupt (VIC) outputs are active if one of the events is
pending.

2.1 Event router pin connections

The event router module in the LPC29xx is connected to the pins listed below. The pins
are combined with other functions on the port pins of the LPC29xx. Table 8–72 shows the
pins connected to the event router, and also the corresponding bit position in the
event-router registers and the default polarity.

Table 72. Event-router pin connections

Symbol Direction Bit position Description Default
polarity
EXTINT0 IN 0 external interrupt input 0 1
EXTINT1 IN 1 external interrupt input 1 1
EXTINT2 IN 2 external interrupt input 2 1
EXTINT3 IN 3 external interrupt input 3 1
EXTINT4 IN 4 external interrupt input 4 1
EXTINT5 IN 5 external interrupt input 5 1
EXTINT6 IN 6 external interrupt input 6 1
EXTINT7 IN 7 external interrupt input 7 1
CAN0 RXDC IN 8 CAN0 receive data input wake-up 0
CAN1 RXDC IN 9 CAN1 receive data input wake-up 0
I2C0_SCL IN 10 I2C0 SCL clock input <tbd>
I2C1_SCL IN 11 I2C1 SCL clock input <tbd>
USB_D+1 IN 12 <tbd> <tbd>
USB_D+2 IN 13 <tbd> <tbd>
LIN0 RXDL IN 14 LIN0 receive data input wake-up 0
LIN1 RXDL IN 15 LIN1 receive data input wake-up 0
SPI0 SDI IN 16 SPI0 data in <tbd>
SPI1 SDI IN 17 SPI1 data in <tbd>
SPI2 SDI IN 18 SPI2 data in <tbd>
UART0 RXD IN 19 UART0 receive data input <tbd>

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Table 72. Event-router pin connections …continued

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Symbol Direction Bit position Description Default

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polarity

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UART1 RXD IN 20 UART1 receive data input <tbd>

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USB_I2C_SCL IN 21 <tbd> <tbd>

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- na 22 CAN interrupt (internal) 1

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- na 23 VIC FIQ (internal) 1

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- na 24 VIC IRQ (internal) 1
- - 26 to 25 reserved -

3. Event Router register overview

The event-router registers are shown in Table 8–73. These registers have an offset to the
base address ER RegBase which can be found in the memory map.

Table 73. Event Router register overview (base address: E000 2000h)
Address Access Reset value Name Description Reference
offset
C00h R 0000 0000h PEND Event status register see
Table 8–74
C20h W - INT_CLR Event-status clear register see
Table 8–75
C40h W - INT_SET Event-status set register see
Table 8–76
C60h R 07FF FFFFh MASK Event-enable register see
Table 8–77
C80h W - MASK_CLR Event-enable clear register see
Table 8–78
CA0h W - MASK_SET Event-enable set register see
Table 8–79
CC0h R/W 01C0 00FFh APR Activation polarity register see
Table 8–80
CE0h R/W 07FF FFFFh ATR Activation type register see
Table 8–81
D00h R - reserved Reserved; do not modify -
D20h R/W 0000 0000h RSR Raw-status register see
Table 8–82

3.1 Event status register

The event status register determines when the Event Router forwards an interrupt request
to the Vectored Interrupt Controller, if the corresponding event enable has been set.

Table 8–74 shows the bit assignment of the PEND register.

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Table 74. PEND register bit description

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* = reset value

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Bit Symbol Access Value Description

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31 to 27 reserved R - Reserved; do not modify. Read as logic 0

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26 PEND[26] R 1 An event has occurred on a corresponding pin,

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or logic 1 is written to bit 26 in the INT_SET

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0* No event is pending or logic 1 has been written
to bit 26 in the INT_CLR register
: : : : :
0 PEND[0] R 1 An event has occurred on a corresponding pin
or logic 1 is written to bit 0 in the INT_SET
register
0* No event is pending or logic 1 has been written
to bit 0 in the INT_CLR register

3.2 Event-status clear register

The event-status clear register clears the bits in the event status register.

Table 8–75 shows the bit assignment of the INT_CLR register.

Table 75. INT_CLR register bit description

Bit Symbol Access Value Description
31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 INT_CLR[26] W 1 Bit 26 in the event status register is cleared
0 Bit 26 in the event status register is unchanged
: : : : :
0 INT_CLR[0] W 1 Bit 0 in the event status register is cleared
0 Bit 0 in the event status register is unchanged

3.3 Event-status set register

The event-status set register sets the bits in the event status register.

Table 8–76 shows the bit assignment of the INT_SET register.

Table 76. INT_SET register bit description

Bit Symbol Access Value Description
31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 INT_SET[26] W 1 Bit 26 in the event status register is set
0 Bit 26 in the event status register is unchanged
: : : : :
0 INT_SET[0] W 1 Bit 0 in the event status register is set
0 Bit 0 in the event status register is unchanged

3.4 Event enable register

The event enable register determines when the Event Router sets the event status and
forwards this to the VIC if the corresponding event-enable has been set.
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Table 8–77 shows the bit assignment of the MASK register.

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Table 77. MASK register bit description

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* = reset value

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Bit Symbol Access Value Description

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31 to 27 reserved R - Reserved; do not modify. Read as logic 0

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26 MASK[26] R Event enable

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This bit is set by writing a logic 1 to bit 26 in the
MASK_SET register
This bit is cleared by writing a logic 1 to bit 26 in
the MASK_CLR register
1*
: : : : :
0 MASK[0] R Event enable
This bit is set by writing a logic 1 to bit 0 in the
MASK_SET register
This bit is cleared by writing a logic 1 to bit 0 in
the MASK_CLR register
1*

3.5 Event-enable clear register

The event-enable clear register clears the bits in the event enable register.

Table 8–78 shows the bit assignment of the MASK_CLR register.

Table 78. MASK_CLR register bit description

Bit Symbol Access Value Description
31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 MASK_CLR[26] W 1 Bit 26 in the event enable register is cleared
0 Bit 26 in the event enable register is unchanged
: : : : :
0 MASK_CLR[0] W 1 Bit 0 in the event enable register is cleared
0 Bit 0 in the event enable register is unchanged

3.6 Event-enable set register

The event-enable set register sets the bits in the event enable register.

Table 8–79 shows the bit assignment of the MASK_SET register.

Table 79. MASK_SET register bit description

Bit Symbol Access Value Description
31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 MASK_SET[26] W 1 Bit 26 in the event-enable register is set
0 Bit 26 in the event-enable register is unchanged
: : : : :
0 MASK_SET[0] W 1 Bit 0 in the event enable register is set
0 Bit 0 in the event enable register is unchanged

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3.7 Activation polarity register

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The APR is used to configure which level is the active state for the event source.

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Table 8–80 shows the bit assignment of the APR register.

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Table 80. APR register bit description

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Bit Symbol Access Value Description

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31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 APR[26] R/W 1[1] The corresponding event is HIGH sensitive
(HIGH-level or rising edge)
0[1] The corresponding event is LOW sensitive
(LOW-level or falling edge)
: : : : :
APR[0] R/W 1[1] The corresponding event is HIGH sensitive
(HIGH-level or rising edge)
0[1] The corresponding event is LOW sensitive
(LOW-level or falling edge)

[1] Reset value is logic 1 for APR[24:22] and APR[7:0]; reset value is logic 0 for APR[26:25] and APR[21:8].

3.8 Activation type register

The ATR is used to configure whether an event is used directly or is latched. If the event is
latched the interrupt persists after its source has become inactive until it is cleared by an
interrupt-clear write action. The Event Router includes an edge-detection circuit which
prevents re-assertion of an event interrupt if the input remains at active level after the latch
is cleared. Level-sensitive events are expected to be held and removed by the event
source.

Table 8–81 shows the bit assignment of the ATR register.

Table 81. ATR register bit description

* = reset value
Bit Symbol Access Value Description
31 to 27 reserved R - Reserved; do not modify. Read as logic 0
26 ATR[24] R/W 1* Corresponding event is latched
(edge-sensitive)
0 Corresponding event is directly forwarded
(level- sensitive)
: : : : :
0 ATR[0] R/W 1* Corresponding event is latched
(edge-sensitive)
0 Corresponding event is directly forwarded
(level-sensitive)

3.9 Raw status register

The RSR shows unmasked events including latched events. Level-sensitive events are
removed by the event source: edge-sensitive events need to be cleared via the event-
clear register.

Table 8–82 shows the bit assignment of the RSR register.

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Table 82. RSR register bits

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Bit Symbol Access Value Description

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31 to 27 reserved R - Reserved; do not modify. Read as logic 0

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26 RSR[26] R 1 Corresponding event has occurred

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0* Corresponding event has not occurred

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: : : : :

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0 RSR[0] R 1 Corresponding event has occurred
0* Corresponding event has not occurred

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. See xxx for interrupt requests that

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are not implemented in all parts. All other interrupt requests are available in all LPC29xx

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parts (see Table 9–90).

Table 83. Available interrupt requests

Part USB interrupts ADC interrupt requests
LPC2921/23/25 46 to 48, 50 17, 18 (ADC1/2)
LPC2917/19/01 45 to 51 17, 18 (ADC1/2)
LPC2927/29 45 to 51 16, 17, 18 (ADC0/1/2)
LPC2930 45 to 51 16, 17, 18 (ADC0/1/2)
LPC2939 45 to 51 16, 17, 18 (ADC0/1/2)

2. VIC functional description

The VIC is a very flexible and powerful block for interrupting the ARM processor on
request. The VIC routes incoming interrupt requests from multiple source to the ARM
processor core. Figure 9–17 shows the VIC connections. An interrupt target is configured
for each interrupt request input of the controller, and the various device peripherals are
connected to the interrupt request inputs. An extensive list of inputs can be found in
Table 9–90.

FIQ
wake-up
Event
wake-up
Router IRQ
wake-up

Timer t IRQ
Timer 1
Timer 0 VIC ARM
FIQ

Interrupt
Requests
...
...
...

Fig 17. Schematic representation of the VIC connections

The ARM core has two possible interrupt targets: IRQ and FIQ.

• The FIQ is designed to support a data transfer or channel process, and has sufficient
private registers to remove the need for register-saving in service routines. This
minimizes the overhead of context switching. FIQ should not enable interrupt during
execution: if needed an IRQ should be used for this purpose.

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• The IRQ exception has a lower priority than FIQ and is masked out when an FIQ

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exception occurs. IRQ service routines should take care of saving and/or restoring the

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used registers themselves.

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The VIC also provides IRQ and FIQ wake-up events to the Event Router. This enables the

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system to wake up upon an interrupt. See also Section 10–5 for interrupt and wake-up

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structure.

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Interrupt Request 1 Interrupt Selection

Active Enable Pending 1 Priority Mask

High/Low Priority Mask FIQ
IRQ

INT 1

FIQ
Target
IRQ/FIQ IRQ

Priority

VECTOR FIQ
Interrupt Request N
VECTOR IRQ
Active Enable Pending N
High/Lo w

INT N

Target
IRQ/FIQ

Priority

Fig 18. Schematic representation of the VIC

A representation of the VIC is shown in Figure 9–18. Each interrupt request has its own
configuration:

• Polarity (active HIGH or LOW): The interrupt request inputs are level-sensitive. The
activation level can be programmed according to the connected peripheral (see
Table 8–72 for the recommended setting).
• Target (IRQ/FIQ): Two targets are possible within the ARM architecture:
– IRQ, Interrupt request; This target is referred to as TARGET1
– FIQ, Fast Interrupt request; This target is referred to as TARGET0
• Priority of the pending interrupt is compared with the priority mask of the selected
target.
– The interrupt is masked if the priority value of the pending interrupt is equal to or
lower than the value in the priority mask.
– For each interrupt target, pending interrupt requests with priority above the priority
threshold are combined through a logical OR, and the result is then routed towards
the interrupt target.

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If the level-sensitive interrupt request line of the VIC is enabled (depending on the polarity

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setting), the request is forwarded to the interrupt selection. The interrupt selection part

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selects the interrupt request line with the highest priority, based on the target and priority

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of the interrupt request and priority masks.

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The VIC introduces an interrupt latency (measured from assertion of an INT_N signal to

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an assertion of IRQ/FIQ) of less than two periods of the system clock.

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The INT_VECTOR register can be used to identify the interrupt request line that needs to
be served. It can be used as an interrupt vector to the interrupt service routine. In
TABLE_ADDR the offset of the vector table can be programmed. Together with the INDEX
this information forms a vector.

The IRQ or FIQ generates a corresponding exception on the ARM core. The exception
handler should read the INT_VECTOR register to determine the highest-priority interrupt
source. This functionality should be implemented in a dispatcher, usually in the assembler.
This dispatcher performs the following steps:

2.1 Non-nested interrupt service routine

1. Put all registers that are used (according to the ARM-Procedure-Call Standard) on
stack.
2. Determine the interrupt source by reading The INT_VECTOR register
3. Call the interrupt service routine
4. Get all (saved) registers back from the stack
5. End the interrupt service routine by restoring the Program Counter register (PC).

2.2 Nested interrupt service routine

1. Put all registers that are used (according to the ARM-Procedure-Call Standard) on
stack.
2. Determine the interrupt source by reading The INT_VECTOR register
3. Raise the priority-masking threshold to the priority level of the interrupt request to be
served
4. Re-enable interrupt in the processor
5. Call the interrupt service routine
6. Restore the saved priority mask
7. Get all (saved) registers back from the stack
8. End the interrupt service routine by restoring the program counter.

3. VIC programming example

The VIC driver provides an API to set up an interrupt source with all its parameters. All this
information ends up in the INT_REQUEST register of the VIC.

In most cases interrupt handling is controlled by some kind of OS. Installation of interrupt
vector tables depends on this.

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4. VIC register overview

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The VIC registers have an offset from the base address VIC RegBase which can be found

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in the memory map; see Table 2–7.

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Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h)

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Address Access Reset value Name Description Reference

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000h R/W - INT_PRIORITYMASK_0 Target 0 priority-mask register see
Table 9–85
004h R/W - INT_PRIORITYMASK_1 Target 1 priority-mask register see
Table 9–85
100h R/W - INT_VECTOR_0 Target 0 vector register see
Table 9–86
104h R/W - INT_VECTOR_1 Target 1 vector register see
Table 9–86
200h R - INT_ PENDING_1_31 Interrupt-pending status register see
Table 9–87
204h R - INT_ PENDING_32_53 Interrupt-pending status register see
Table 9–88
300h R 0001 0F3F INT_FEATURES Interrupt controller features register see
Table 9–89
404h R/W - INT_REQUEST_1 Interrupt Request 1 control register see
Table 9–91
408h R/W - INT_REQUEST_2 Interrupt Request 2 control register see
Table 9–91
40Ch R/W - INT_REQUEST_3 Interrupt Request 3 control register see
Table 9–91
410h R/W - INT_REQUEST_4 Interrupt Request 4 control register see
Table 9–91
414h R/W - INT_REQUEST_5 Interrupt Request 5 control register see
Table 9–91
418h R/W - INT_REQUEST_6 Interrupt Request 6 control register see
Table 9–91
41Ch R/W - INT_REQUEST_7 Interrupt Request 7 control register see
Table 9–91
420h R/W - INT_REQUEST_8 Interrupt Request 8 control register see
Table 9–91
424h R/W - INT_REQUEST_9 Interrupt Request 9 control register see
Table 9–91
428h R/W - INT_REQUEST_10 Interrupt Request 10 control register see
Table 9–91
42Ch R/W - INT_REQUEST_11 Interrupt Request 11 control register see
Table 9–91
430h R/W - INT_REQUEST_12 Interrupt Request 12 control register see
Table 9–91
434h R/W - INT_REQUEST_13 Interrupt Request 13 control register see
Table 9–91
438h R/W - INT_REQUEST_14 Interrupt Request 14 control register see
Table 9–91

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Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h) …continued

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Address Access Reset value Name Description Reference

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43Ch R/W - INT_REQUEST_15 Interrupt Request 15 control register see

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Table 9–91

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440h R/W - INT_REQUEST_16 Interrupt Request 16 control register see

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Table 9–91

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444h R/W - INT_REQUEST_17 Interrupt Request 17 control register see

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Table 9–91
448h R/W - INT_REQUEST_18 Interrupt Request 18 control register see
Table 9–91
44Ch R/W - INT_REQUEST_19 Interrupt Request 19 control register see
Table 9–91
450h R/W - INT_REQUEST_20 Interrupt Request 20 control register see
Table 9–91
454h R/W - INT_REQUEST_21 Interrupt Request 21 control register see
Table 9–91
458h R/W - INT_REQUEST_22 Interrupt Request 22 control register see
Table 9–91
45Ch R/W - INT_REQUEST_23 Interrupt Request 23 control register see
Table 9–91
460h R/W - INT_REQUEST_24 Interrupt Request 24 control register see
Table 9–91
464h R/W - INT_REQUEST_25 Interrupt Request 25 control register see
Table 9–91
468h R/W - INT_REQUEST_26 Interrupt Request 26 control register see
Table 9–91
46Ch R/W - INT_REQUEST_27 Interrupt Request 27 control register see
Table 9–91
470h R/W - INT_REQUEST_28 Interrupt Request 28 control register see
Table 9–91
474h R/W - INT_REQUEST_29 Interrupt Request 29 control register see
Table 9–91
478h R/W - INT_REQUEST_30 Interrupt Request 30 control register see
Table 9–91
47Ch R/W - INT_REQUEST_31 Interrupt Request 31 control register see
Table 9–91
480h R/W - INT_REQUEST_32 Interrupt Request 32 control register see
Table 9–91
484h R/W - INT_REQUEST_33 Interrupt Request 33 control register see
Table 9–91
488h R/W - INT_REQUEST_34 Interrupt Request 34 control register see
Table 9–91
48Ch R/W - INT_REQUEST_35 Interrupt Request 35 control register see
Table 9–91
490h R/W - INT_REQUEST_36 Interrupt Request 36 control register see
Table 9–91
494h R/W - INT_REQUEST_37 Interrupt Request 37 control register see
Table 9–91

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Table 84. Vectored Interrupt Controller register overview (base address: FFFF F000h) …continued

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Address Access Reset value Name Description Reference

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498h R/W - INT_REQUEST_38 Interrupt Request 38 control register see

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Table 9–91

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49Ch R/W - INT_REQUEST_39 Interrupt Request 39 control register see

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Table 9–91

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4A0h R/W - INT_REQUEST_40 Interrupt Request 40 control register see

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Table 9–91
4A4h R/W - INT_REQUEST_41 Interrupt Request 41 control register see
Table 9–91
4A8h R/W - INT_REQUEST_42 Interrupt Request 42 control register see
Table 9–91
4ACh R/W - INT_REQUEST_43 Interrupt Request 43 control register see
Table 9–91
4B0h R/W - INT_REQUEST_44 Interrupt Request 44 control register see
Table 9–91
4B4h R/W - INT_REQUEST_45 Interrupt Request 45 control register see
Table 9–91
4B8h R/W - INT_REQUEST_46 Interrupt Request 46 control register see
Table 9–91
4BCh R/W - INT_REQUEST_47 Interrupt Request 47 control register see
Table 9–91
4C0h R/W - INT_REQUEST_48 Interrupt Request 48 control register see
Table 9–91
4C4h R/W - INT_REQUEST_49 Interrupt Request 49 control register see
Table 9–91
4C8h R/W - INT_REQUEST_50 Interrupt Request 50 control register see
Table 9–91
4CCh R/W - INT_REQUEST_51 Interrupt Request 51 control register see
Table 9–91
4D0h R/W - INT_REQUEST_52 Interrupt Request 52 control register see
Table 9–91
4D4h R/W - INT_REQUEST_53 Interrupt Request 53 control register see
Table 9–91
4D8h R/W - INT_REQUEST_54 Interrupt Request 54 control register see
Table 9–91
4DCh R/W - INT_REQUEST_55 Interrupt Request 55 control register see
Table 9–91

4.1 Interrupt priority mask register

The interrupt priority-mask registers define the thresholds for priority-level masking. Each
interrupt target has its own priority limiter which can be used to define the minimum priority
level for nesting interrupts. Typically, the priority limiter is set to the priority level of the
interrupt service routine that is currently being executed so that only interrupt requests at
a higher priority level lead to a nested interrupt service. Nesting can be disabled by setting
the priority level to Fh in the interrupt request register.

Table 9–85 shows the bit assignment of the INT_PRIORITYMASK_0 and

INT_PRIORITYMASK_1 registers.

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Table 85. INT_PRIORITYMASK_n registers bit description (INT_PRIORITYMASK_0/1,

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addresses 0xFFFF F000 and 0xFFFF F004)

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Bit Symbol Access Reset Description

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value

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31 to 4 reserved R - Reserved; do not modify. Read as logic

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0

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3 to 0 PRIORITY_LIMITER[3:0] R/W - Priority limiter. This sets a priority

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threshold that incoming interrupt
requests must exceed to trigger
interrupt requests towards the controller
and power management controller

4.2 Interrupt vector register

The interrupt vector registers identify for each interrupt target the highest-priority enabled
pending interrupt request that is present at the time when the register is being read. The
software interrupt service routine must always read the vector register that corresponds to
the interrupt target. The interrupt vector content can be used as vector into a memory
based table like that shown in Figure 9–19. This table has 32 entries. To be able to use the
register content as a full 32-bit address pointer the table must be aligned to a 512-byte
address boundary (or 2048 to be future-proof). If only the index variable is used as offset
into the table then this address alignment is not required. Each table entry is 64 bits wide.
It is recommended to pack for each table entry:

• The start address of a peripheral-specific interrupt service routine, plus

• The associated priority-limiter value (if nesting of interrupt service routines is
performed)

A vector with index 0 indicates that no interrupt is pending with a priority above the priority
threshold. For this special-case entry the vector table should implement a ‘no-interrupt’
handler.

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Interrupt service routine 2

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Entry point

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Interrupt service routine 1
Index Priority limiter 2

010h Vector 2 Entry point

Pointer
00Ch Priority limiter 1

008h Vector 1 "no interrupt" handler

004h unused

TABLE_ADDR + 000h Vector 0 Entry point

Interrupt vector table Device specific

in memory interrupt service routine
in memory
001aaa172

Fig 19. Memory-based interrupt vector and priority table

Table 9–86 shows the bit assignment of the INT_VECTOR registers.

Table 86. INT_VECTORn register bit description (INT_VECTOR0/1, addresses 0xFFFF F100
and 0xFFFF F104)
Bit Symbol Access Value Description
31 to 11 TABLE_ADDR[20:0] R/W - Table start address. This indicates the lower
address boundary of a 512-byte aligned
vector table in memory. To be compatible
with future extension an address boundary of
2048 bytes is recommended
10 and reserved R - Reserved; do not modify. Read as logic 0
9
8 to 3 INDEX[5:0] R/W[1] Index. This indicates the interrupt request
line of the interrupt request to be served by
the controller
00 0000 No interrupt request to be serviced
00 0001 Service interrupt request at input 1
: :
01 1111 Service interrupt request at input 31
2 to 0 NULL[2:0] R/W[1] 0h Always reflecting logic 0s

[1] Write as 0.

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4.3 Interrupt-pending register 1

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The interrupt-pending register gathers the pending bits of interrupt requests 1 to 31.

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Software can make use of this feature to gain a faster overview of pending interrupts than

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it would get by reading the individual interrupt request registers.

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The INT_PENDING_1_31 register is read-only.

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Table 9–87 shows the bit assignment of the INT_PENDING_1_31 register.

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Table 87. INT_PENDING_1_31 register bit description (INT_PENDING_1_31, address
0xFFFF F200)
Bit Symbol Access Value Description
31 PENDING[31] R 1 Interrupt request 31 is pending
0 There is no interrupt request 31
: : : :
1 PENDING[1] R 1 Interrupt request 1 is pending
0 There is no interrupt request 1
0 R 0 Reserved; read as logic 0

4.4 Interrupt-pending register 2

The interrupt-pending register gathers the pending bits of all interrupt requests 32 to 63.
Software can make use of this feature to gain a faster overview on pending interrupts than
it would get by reading the individual interrupt request registers.

The INT_PENDING_32_63 register is read only.

Table 9–88 shows the bit assignment of the INT_PENDING_32_63 register.

Table 88. INT_PENDING_32_63 register bit description (INT_PENDING_32_63, address

0xFFFF F204)
Bit Symbol Access Value Description
31 to 25 reserved R - Reserved; read as don’t care
24 PENDING[63] R 1 Interrupt request 63 is pending
0 There is no interrupt request 63
: : : :
0 PENDING[32] R 1 Interrupt request 32 is pending
0 There is no interrupt request 32

4.5 Interrupt controller features register

The interrupt controller features register indicates the VIC configuration which an ISR can
use for implementing interrupt controller configuration-specific behavior.

The INT_FEATURES register is read-only

Table 9–89 shows the bit assignment of the INT_FEATURES register.

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Table 89. INT_FEATURES register bit description (INT_FEATURES, address 0xFFFF F300)

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* = reset value

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Bit Symbol Access Value Description

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31 to 16 reserved R - Reserved; read as don’t care

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21 to 16 T R Number of targets (minus one)

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01h*

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15 to 8 P R Number of priorities (minus one)

A
0Fh*
7 to 0 N R Number of interrupt requests
3Fh*

4.6 Interrupt request register

The reference between the interrupt source and interrupt request line is reflected in
Table 9–90.

Table 90. Interrupt source and request reference

Interrupt Interrupt source Description
request
1 Watchdog Interrupt from Watchdog timer
2 timer 0 Capture or match interrupt from timer 0
3 timer 1 Capture or match interrupt from timer 1
4 timer 2 Capture or match interrupt from timer 2
5 timer 3 Capture or match interrupt from timer 3
6 UART 0 General interrupt from 16C550 UART 0
7 UART 1 General interrupt from 16C550 UART 1
8 SPI 0 General interrupt from SPI 0
9 SPI 1 General interrupt from SPI 1
10 SPI 2 General interrupt from SPI 2
11 flash Signature, burn or erase finished interrupt from flash
12 embedded RT-ICE Comms Rx for ARM debug mode
13 embedded RT-ICE Comms Tx for ARM debug mode
14 MSCSS timer 0 Capture or match interrupt from MSCSS timer 0
15 MSCSS timer 1 Capture or match interrupt from MSCSS timer 1
16 ADC int_req 0 ADC interrupt from ADC 0
17 ADC int_req 1 ADC interrupt from ADC 1
18 ADC int_req 2 ADC interrupt from ADC 2
19 PWM 0 PWM interrupt from PWM 0
20 PWM capt match 0 PWM capture/match interrupt from PWM 0
21 PWM 1 PWM interrupt from PWM 1
22 PWM capt match 1 PWM capture/match interrupt from PWM 1
23 PWM 2 PWM interrupt from PWM 2
24 PWM capt match 2 PWM capture/match interrupt from PWM 2
25 PWM 3 PWM interrupt from PWM 3
26 PWM capt match 3 PWM capture/match interrupt from PWM 3

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Table 90. Interrupt source and request reference …continued

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Interrupt Interrupt source Description

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F
request

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27 Event Router Event, wake up tick interrupt from Event Router

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28 LIN master controller 0 General interrupt from LIN master controller 0

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29 LIN master controller 1 General interrupt from LIN master controller 1

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30 I2C0 I2C interrupt from I2C0 (SI state change)

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31 I2C1 I2C interrupt from I2C1 (SI state change)
32 GPDMA DMA
33 GPDMA DMA err
34 GPDMA DMA tc
35 all CAN controllers FullCAN
36 all CAN controllers Combined general interrupt of all CAN controllers and the
CAN look-up table[1]
37 CAN controller 0 Message-received interrupt from CAN controller 0[2]
38 CAN controller 1 Message-received interrupt from CAN controller 1[2]
39 - 42 - reserved
43 CAN controller 0 Message-transmitted interrupt from CAN controller 0
44 CAN controller 1 Message-transmitted interrupt from CAN controller 1
45 USB I2C
46 USB device, high-priority
47 USB device, low-priority
48 USB device DMA
49 reserved
50 USB ATX
51 USB OTG timer
52 QEI quadrature encoder interrupt
53 - 54 - reserved
55 CGU0
56 CGU1
63 - 57 - reserved

[1] Combined general interrupt of all CAN controllers and the CAN look-up table; The following interrupts are
combined here: error-warning interrupt (EWI), data-overrun interrupt (DOI), error-passive interrupt (EPI),
arbitration-lost Interrupt (ALI), bus-error Interrupt (BEI) and look-up table error interrupt (CALUTE); see
Section 21–9.4and Section 21–10.8 for details.
[2] Message-received interrupt from a CAN controller. The receive interrupt (RI) and the ID ready interrupt (IDI)
are combined here; see Section 21–9.14 for details.

The interrupt request registers hold the configuration information related to interrupt
request inputs of the interrupt controller and allow it to issue software interrupt requests.
Each interrupt line has its own interrupt request register.

Table 9–91 shows the bit assignment of the INT_REQUEST register.

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Table 91. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses

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0xFFFF F404 to 0xFFFF F4E0).

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F
* = reset value

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Bit Symbol Access Value Description

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31 PENDING R Pending interrupt request. This reflects

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the state of the interrupt source

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channel. The pending status is also

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visible in the interrupt-pending register

A
1 An interrupt request is pending
0 There is no interrupt request
30 SET_SWINT W Set software-interrupt request
1 Sets the local software-interrupt request
state
0* No effect on the local software-interrupt
request state. This bit is always read as
logic 0
29 CLR_SWINT W Clear software-interrupt request
1 clears the local software-interrupt
request state
0* no effect on the local software-interrupt
request state. This bit is always read as
logic 0
28 WE_PRIORITY_LEVEL W Write-enable priority level
1 Enables the bit-state change during the
same register access
0 Does not change the bit state. This bit is
always read as logic 0
27 WE_TARGET W - Write-enable target
1 Enables the bit-state change during the
same register access. For changing the
bit state software must first disable the
interrupt request (bit ENABLE = 0), then
change this bit and finally re-enable the
interrupt request (bit ENABLE = 1)
0 Does not change this bit state. This bit
is always read as logic 0
26 WE_ENABLE W Write enable
1 Enables this bit-state change during the
same register access
0 Does not change this bit state. This bit
is always read as logic 0
25 WE_ACTIVE_LOW W Write-enable active LOW
1 Enables the bit-state change during the
same register access
0 Does not change the bit state. This bit is
always read as logic 0
24 to 18 reserved R - Reserved; do not modify. Read as logic
0

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Table 91. INT_REQUESTn register bit description (INT_REQUEST1 to 56, addresses

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0xFFFF F404 to 0xFFFF F4E0).

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F
* = reset value

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Bit Symbol Access Value Description

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17 ACTIVE_LOW R/W Active-LOW interrupt line. This selects

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the polarity of the interrupt request line.

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State changing is only possible if the

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corresponding write-enable bit has been

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set
1 The interrupt request is active LOW
0* The interrupt request is active HIGH
16 ENABLE R/W Enable interrupt request. This controls
interrupt-request processing by the
interrupt controller. State changing is
only possible if the corresponding write-
enable bit has been set
1 The interrupt request may cause an
ARM processor interrupt request if
further conditions become true
0* The interrupt request is discarded and
will not cause an ARM processor
interrupt
15 to 9 reserved R - Reserved; do not modify. Read as logic
0
8 TARGET R/W Interrupt target. This defines the target
of an interrupt request. State changing
is only possible if the corresponding
write-enable bit has been set
1 The target is the IRQ
0* The target is the FIQ
7 to 4 reserved R - Reserved; do not modify. Read as logic
0
3 to 0 PRIORITY_LEVEL[3:0] R/W - Interrupt priority level. This determines
the priority level of the interrupt request.
State changing is only possible if the
corresponding write-enable bit has been
set. Priority level 0 masks the interrupt
request, so it is ignored. Priority level 1
has the lowest priority and level 15 the
highest

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Rev. 00.06 — 17 December 2008 User manual

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts.

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2. Introduction
This chapter contains power control, interrupt, and wake-up features that pertain to
various functions and peripherals on the LPC29xx.

3. Power modes

Power Mode := “Idle”

(CGU.CPM register)

Power Mode Power Mode

Reset
“Normal” “Idle”

wake-up event
(from Event Router to CGU )

Fig 20. Power modes

The device operates in normal-power mode after reset. In this mode the device is fully
functional, i.e. all clock domains are available1. The system can be put into idle-power
mode either partially or fully. In this mode selected clock domains are switched off, and
this might also suspend execution of the software. The clock domains are enabled again
upon a wake-up event. This wake-up event is provided by the Event Router.

The clock domains that can be switched off during idle-power mode depend on the
selected wake-up events. For an external interrupt (e.g. EXTINT0) no active clock is
required, i.e. all clock domains can be switched off. However, for wake-up on a timer
interrupt the clock domain of the timer should stay enabled during low-power mode. In
general, each subsystem that might cause a wake-up upon an interrupt must be excluded
from the low power mode, i.e. the clock domain of the subsystem should stay enabled.2

1. Although all clock domains are available, not all the domains are enabled. E.g. the ADC clock domain is switched off by default
after reset.
2. The CAN and LIN controllers can issue a wake-up event via activity on the CAN or LIN bus. This feature does not require an active
clock for their subsystem; but the first message can be lost.

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Section 3–3. Configuration of wake-up events is handled by the Event Router, see

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Section 8–2.

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4. Reset and power-up behavior

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The LPC29xx contains external reset input and internal power-up reset circuits. This

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ensures that a reset is internally extended internally until the oscillators and flash have
reached a stable state. Table 10–92 shows the reset pin.

Table 92. Reset pin

Symbol Direction Description
RSTN in external reset input, active LOW; pulled up internally

At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC29xx is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.

5. Functional description of the interrupt and wake-up structure

An overview of the interrupt and wake-up structure is given in Figure 10–21. The main
functions are:

• Events and interrupt requests causing an interrupt (IRQ or FIQ) on the ARM
processor.
• Events and interrupt requests causing a wake-up. During low-power mode selected
clock domains are switched off, and they are turned on by this wake-up.

wake-up

... IRQ
Ext. ... Event
UART ... CGU VIC ARM
Int. Router
FIQ

Events

Interrupt Requests

Fig 21. Interrupt and wake-up structure

In this case the VIC (Vectored Interrupt Controller) is configured to send an interrupt (IRQ
or FIQ) towards the ARM processor. Examples are interrupts to indicate the reception of
data via a serial interface, or timer interrupts. The Event Router serves as a multiplexer for
internal and external events and indicates the occurrence of such an event towards the
VIC (Event-Router interrupt). The Event Router is also able to latch the occurrence of
these events (level or edge-triggered).

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IRQ

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UART VIC ARM

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Interrupt Requests

Fig 22. Interrupt (UART) causing an IRQ

IRQ
Event
VIC ARM
Router

Events

Interrupt Requests

Fig 23. Event causing an IRQ

6. Interrupt device architecture

In the LPC29xx a general approach is taken to generate interrupt requests towards the
CPU. A vectored Interrupt Controller (VIC) receives and collects the interrupt requests as
generated by the several modules in the device.

Figure 10–24 shows the logic used to gate the event signal originating from the function
with the parameters provided by the user software.

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Request

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>1

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&

STATUS ENABLE

>1
Event

SET CLEAR SET CLEAR

STATUS STATUS ENABLE ENABLE

Control
Interface

Fig 24. Interrupt device architecture

A set of software-accessible variables is provided for each interrupt source to control and
observe interrupt request generation. In general, a pair of read-only registers is used for
each event that leads to an interrupt request:

• STATUS captures the event. The variable is typically set by a hardware event and
cleared by the software ISR, but for test purposes it can also be set by software
• ENABLE enables the assertion of an interrupt-request output signal for the captured
event

In conjunction with the STATUS/ENABLE variables, commands are provided to set and
clear the variable state through a software write-action to write-only registers. These
commands are SET_STATUS, CLR_STATUS, SET_ENABLE and CLR_ENABLE.

The event signal is logically OR-ed with its associated SET_STATUS register bit, so both
events writing to the SET_STATUS register sets the STATUS register.

Typically, the result of multiple STATUS/ENABLE pairs is logically OR-ed per functional
group, forming an interrupt request signal towards the Vectored Interrupt Controller.

6.1 Interrupt registers

A list is provided for each function in the detailed block-description part of this document,
containing the interrupt sources for that function. A table is also provided to indicate the bit
positions per interrupt source. These positions are identical for all the six registers
INT_STATUS, INT_ENABLE, INT_SET_STATUS, INT_CLEAR_STATUS,
INT_SET_ENABLE and INT_CLEAR_ENABLE.

Up to 32 interrupt bits are available for each register.

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6.1.1 Interrupt clear-enable register

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Write ‘1’ actions to this register set one or more ENABLE variables in the INT_ENABLE

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register. INT_SET_ENABLE is write-only. Writing a 0 has no effect.

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Table 93. INT_CLR_ENABLE register bit description

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Bit Variable Name Access Value Description

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i CLR_ENABLE[i] W 1 Clears the ENABLE[i] variable in corresponding

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INT_ENABLE register (set to 0)

6.1.2 Interrupt set-enable register

Write ‘1’ actions to this register set one or more ENABLE variables in the INT_ENABLE
register. INT_SET_ENABLE is write-only. Writing a 0 has no effect.

Table 94. INT_SET_ENABLE register bit description

Bit Variable Name Access Value Description
i SET_ENABLE[i] W 1 Sets the ENABLE[i] variable in corresponding
INT_ENABLE register to 1

6.1.3 Interrupt status register

The interrupt status register reflects the status of the corresponding interrupt event that
leads to an interrupt request. INT_STATUS is a read-only register. Its content is either
changed by a hardware event (from logic 0 to 1 in the case of an event), or by software
writing a 1 to the INT_CLR_STATUS or INT_SET_STATUS register.

Table 95. INT_STATUS register bit description

* = reset value
Bit Variable Name Access Value Description
i STATUS[i] R 1 Event captured; request for interrupt service on
the corresponding interrupt request signal if
ENABLE[i] = 1 interrupt for end of scan
0*

6.1.4 Interrupt enable register

This register enables or disables generation of interrupt requests on associated interrupt-
request output signals. INT_ENABLE is a read-only register. Its content is changed by
software writing to the INT_CLR_ENABLE or INT_SET_ENABLE registers.

Table 96. INT_ENABLE register bit description

* = reset value
Bit Variable Name Access Value Description
i ENABLE[i] R 1 Enables interrupt request generation. The
corresponding interrupt request output signal is
asserted when STATUS[i] =1
0*

6.1.5 Interrupt clear-status register

Write ‘1’ actions to this register clear one or more status variables in the INT_STATUS
register. Writing a ‘0’ has no effect.

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Table 97. INT_CLR_STATUS register bit description

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Bit Variable Name Access Value Description

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i CLR_STATUS[i] W 1 Clears STATUS[i] variable in INT_STATUS

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register (set to 0)

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6.1.6 Interrupt set-status register

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Write ‘1’ actions to this register set one or more STATUS variables in the INT_STATUS

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register. This register is write-only and is intended for debug purposes. Writing a ‘0’ has no
effect.

Table 98. INT_SET_STATUS register bit description

Bit Variable Name Access Value Description
i SET_STATUS[i] W 1 Sets STATUS[i] variable in INT_STATUS
register to 1

7. ISR functional description

The LPC29xx includes several peripherals, some of these influence each other during
normal operation: for example the behaviors of the VIC and the Event Router. In most
cases interrupt handling is controlled by some kind of OS, so the VIC and event-router
functionality is divided into two components, ISR and ESR (Section 10–8). The ISR
component can be used in situations where no OS is present or the OS does not support
this functionality.

The ISR component also makes possible recursive calls to tmISR_EnableInterrupts and
tmISR_DisableInterrupts. In this way atomic actions can be created, and can call other
functions that contain atomic actions. Enabling or disabling the interrupts is dealt with
automatically. A general rule is to keep atomic actions as small as possible.

8. Event-service routine (ESR) - Event handling

8.1 ESR functional description

This driver converts generated events to interrupt signals that are asserted in the VIC. It
does not cover wake-up and power functions since these are handled by the CGU.

External interrupts are routed via the Event Router. When one of these signals is asserted
the Event Router generates an interrupt on the VIC. The VIC then asserts the ARM core.

Handling of the VIC is done by the OS or by the ISR driver (see Section 10–7). Before the
ESR driver is used the interrupt-handling software must be initialized. This is done by the
OS or by the ISR driver.

The Event Router reacts to certain events when they are enabled. If an enabled event is
asserted, the Event Router signals the VIC. This leads to execution of a special interrupt
function: tmESR_EventDispatcher. This function checks the event-router status and
executes the ESR of the active event source.

Usage of the ESR driver consists of several steps:

• Initialization of the driver:

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– Initialization of the interrupt functionality (outside the scope of this driver)

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– Installation of the event-dispatcher interrupt function

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– Initialization of the ESR driver

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• Installation of the ESR:

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– Configure the signal specifications for external interrupts

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With this API the edge/level sensitivity can be programmed

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– Install the ESR handler.
This function installs the ESR handler in the ESR vector table.
– Enable the ESR handler.
– Enable the specified event.

9. Wake-up
In low-power mode, selected idle clock domains are switched off. The wake-up signal
towards the CGU enables the clock of these domains. A typical application is to configure
all clock domains to switch off. Since the clock of the ARM processor is also switched off,
execution of software is suspended and resumed on wake-up.

In this case the Event Router is configured to send a wake-up signal towards the CGU
(Clock Generation Unit). Examples are events to indicate the reception of data (e.g. on the
CAN receiver) or external interrupts.

The VIC can be used (IRQ wake-up event or FIQ wake-up event of the Event Router) to
generate a wake-up event on an interrupt occurrence. This is only possible if the clock
domain of the interrupt source is excluded from low-power mode. The VIC does not need
a clock to generate these wake-up events.

Examples of use are to configure a timer to wake up the system after a defined time, or to
wake up on receiving data via the UART.

wake-up

Event
UART CGU
Router

Events

Fig 25. Interrupt (UART) causing a wake-up

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Event

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UART CGU VIC

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Events

Interrupt Requests

Fig 26. Event causing a wake-up

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1. How to read this chapter

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See Table 11–99 for pin configurations of all LPC29xx parts.

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Table 99. Feature overview
Part Pin configuration Pin assignment
LPC2917/19/01 Figure 11–27 Table 11–100
LPC2921/23/25 Figure 11–28 Table 11–101
LPC2927/29 Figure 11–29 Table 11–102
LPC2930 Figure 11–30 Table 11–103
LPC2939 Figure 11–30 Table 11–103

2. LPC2917/19/01 pinning information

The LPC29xx have up to four ports: two of 32 pins each, one of 28 pins and one of 16
pins. The pin to which each function is assigned is controlled by the SFSP registers in the
SCU. The functions combined on each port pin are shown in the pin description tables in
this section.
144

109

1 108

LPC2917FBD144
LPC2919FBD144

36 73
37

72

002aad935

Fig 27. Pin configuration for SOT486-1 (LQFP144)

Table 100. LPC2917/19/01 LQFP144 pin assignment

Pin name Pin Description
Default function Function 1 Function 2 Function 3
TDO 1[1] IEEE 1149.1 test data out
P2[21]SDI2/ 2[1] GPIO 2, pin 21 SPI2 SDI PWM2 CAP1 EXTBUS D19
PCAP2[1]/D19
P0[24]/TXD1/ 3[1] GPIO 0, pin 24 UART1 TXD CAN1 TXD SPI2 SCS0
TXDC1/SCS2[0]
P0[25]/RXD1/ 4[1] GPIO 0, pin 25 UART1 RXD CAN1 RXD SPI2 SDO
RXDC1/SDO2

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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P0[26]/TXD1/ 5[1] GPIO 0, pin 26 - UART1 TXD SPI2 SDI

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SDI2

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P0[27]/RXD1/ 6[1] GPIO 0, pin 27 - UART1 RXD SPI2 SCK

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SCK2

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P0[28]/CAP0[0]/ 7[1] GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0
MAT0[0]
P0[29]/CAP0[1]/ 8[1] GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1
MAT0[1]
VDD(IO) 9 3.3 V power supply for I/O
P2[22]/SCK2/ 10[1] GPIO 2, pin 22 SPI2 SCK PWM2 CAP2 EXTBUS D20
PCAP2[2]/D20
P2[23]/SCS1[0]/ 11[1] GPIO 2, pin 23 SPI1 SCS0 PWM3 CAP0 EXTBUS D21
PCAP3[0]/D21
P3[6]/SCS0[3]/ 12[1] GPIO 3, pin 6 SPI0 SCS3 PWM1 MAT0 LIN1/UART TXD
PMAT1[0]/
TXDL1
P3[7]/SCS2[1]/ 13[1] GPIO 3, pin 7 SPI2 SCS1 PWM1 MAT1 LIN1/UART RXD
PMAT1[1]/
RXDL1
P0[30]/CAP0[2]/ 14[1] GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
MAT0[2]
P0[31]/CAP0[3]/ 15[1] GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3
MAT0[3]
P2[24]/SCS1[1]/ 16[1] GPIO 2, pin 24 SPI1 SCS1 PWM3 CAP1 EXTBUS D22
PCAP3[1]/D22
P2[25]/SCS1[2]/ 17[1] GPIO 2, pin 25 SPI1 SCS2 PWM3 CAP2 EXTBUS D23
PCAP3[2]/D23
VDD(CORE) 18 1.8 V power supply for digital core
VSS(CORE) 19 ground for digital core
P1[31]/CAP0[1]/ 20[1] GPIO 1, pin 31 TIMER0 CAP1 TIMER0 MAT1 EXTINT5
MAT0[1]/EI5
VSS(IO) 21 ground for I/O
P1[30]/CAP0[0]/ 22[1] GPIO 1, pin 30 TIMER0 CAP0 TIMER0 MAT0 EXTINT4
MAT0[0]/EI4
P3[8]/SCS2[0]/ 23[1] GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 -
PMAT1[2]
P3[9]/SDO2/PM 24[1] GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 -
AT1[3]
P1[29]/CAP1[0]/ 25[1] GPIO 1, pin 29 TIMER1 CAP0 PWM TRAP0 PWM3 MAT5
TRAP0/
PMAT3[5]
P1[28]/CAP1[1]/ 26[1] GPIO 1, pin 28 TIMER1 CAP1, ADC1 PWM TRAP1 PWM3 MAT4
TRAP1/ EXT START
PMAT3[4]
P2[26]/CAP0[2]/ 27[1] GPIO 2, pin 26 TIMER0 CAP2 TIMER0 MAT2 EXTINT6
MAT0[2]/EI6

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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P2[27]/CAP0[3]/ 28[1] GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7

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MAT0[3]/EI7

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P1[27]/CAP1[2]/ 29[1] GPIO 1, pin 27 TIMER1 CAP2, ADC2 PWM TRAP2 PWM3 MAT3

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TRAP2/ EXT START

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PMAT3[3]
P1[26]/ 30[1] GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2
PMAT2[0]/
TRAP3/
PMAT3[2]
VDD(IO) 31 3.3 V power supply for I/O
P1[25]/ 32[1] GPIO 1, pin 25 PWM1 MAT0 - PWM3 MAT1
PMAT1[0]/
PMAT3[1]
P1[24]/ 33[1] GPIO 1, pin 24 PWM0 MAT0 - PWM3 MAT0
PMAT0[0]/
PMAT3[0]
P1[23]/ 34[1] GPIO 1, pin 23 UART0 RXD - EXTBUS CS5
RXD0/CS5
P1[22]/TXD0/ 35[1] GPIO 1, pin 22 UART0 TXD - EXTBUS CS4
CS4
TMS 36[1] IEEE 1149.1 test mode select, pulled up internally
TCK 37[1] IEEE 1149.1 test clock
P1[21]/CAP3[3]/ 38[1] GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3, EXTBUS D7
CAP1[3]/D7 MSCSS PAUSE
P1[20]/CAP3[2]/ 39[1] GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6
SCS0[1]/D6
P1[19]/CAP3[1]/ 40[1] GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5
SCS0[2]/D5
P1[18]/CAP3[0]/ 41[1] GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO EXTBUS D4
SDO0/D4
P1[17]/CAP2[3]/ 42[1] GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI EXTBUS D3
SDI0/D3
VSS(IO) 43 ground for I/O
P1[16]/CAP2[2]/ 44[1] GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK EXTBUS D2
SCK0/D2
P2[0]/MAT2[0]/ 45[1] GPIO 2, pin 0 TIMER2 MAT0 PWM TRAP3 EXTBUS D8
TRAP3/D8
P2[1]/MAT2[1]/ 46[1] GPIO 2, pin 1 TIMER2 MAT1 PWM TRAP2 EXTBUS D9
TRAP2/D9
P3[10]/SDI2/ 47[1] GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 -
PMAT1[4]
P3[11]/SCK2/ 48[1] GPIO 3, pin 11 SPI2 SCK PWM1 MAT5 -
PMAT1[5]
P1[15]/CAP2[1]/ 49[1] GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 EXTBUS D1
SCS0[0]/D1

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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P1[14]/CAP2[0]/ 50[1] GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0

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SCS0[3]/D0

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P1[13]/SCL1/ 51[1] GPIO 1, pin 13 EXTINT3 I2C1 SCL EXTBUS WE_N

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EI3/WE_N

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P1[12]/SDA1/ 52[1] GPIO 1, pin 12 EXTINT2 I2C1 SDA EXTBUS OE_N
EI2/OE_N
VDD(IO) 53 3.3 V power supply for I/O
P2[2]/MAT2[2]/ 54[1] GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10
TRAP1/D10
P2[3]/MAT2[3]/ 55[1] GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11
TRAP0/D11
P1[11]/SCK1/ 56[1] GPIO 1, pin 11 SPI1 SCK I2C0 SCL EXTBUS CS3
SCL0/CS3
P1[10]/SDI1/ 57[1] GPIO 1, pin 10 SPI1 SDI I2C0 SDA EXTBUS CS2
SDA0/CS2
P3[12]/SCS1[0]/ 58[1] GPIO 3, pin 12 SPI1 SCS0 EXTINT4 -
EI4
VSS(CORE) 59 ground for digital core
VDD(CORE) 60 1.8 V power supply for digital core
P3[13]/SDO1/ 61[1] GPIO 3, pin 13 SPI1 SDO EXTINT5 QEI0 IDX
EI5/IDX0
P2[4]/MAT1[0]/ 62[1] GPIO 2, pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12
EI0/D12
P2[5]/MAT1[1]/ 63[1] GPIO 2, pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13
EI1/D13
P1[9]/SDO1/ 64[1] GPIO 1, pin 9 SPI1 SDO LIN1/UART RXD EXTBUS CS1
RXDL1/CS1
VSS(IO) 65 ground for I/O
P1[8]/SCS1[0]/ 66[1] GPIO 1, pin 8 SPI1 SCS0 LIN1/UART TXD EXTBUS CS0
TXDL1/CS0
P1[7]/SCS1[3]/ 67[1] GPIO 1, pin 7 SPI1 SCS3 UART1 RXD EXTBUS A7
RXD1/A7
P1[6]/SCS1[2]/ 68[1] GPIO 1, pin 6 SPI1 SCS2 UART1 TXD EXTBUS A6
TXD1/A6
P2[6]/MAT1[2]/ 69[1] GPIO 2, pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14
EI2/D14
P1[5]/SCS1[1]/ 70[1] GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5
PMAT3[5]/A5
P1[4]/SCS2[2]/ 71[1] GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4
PMAT3[4]/A4
TRST_N 72[1] IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RST_N 73[1] asynchronous device reset; active LOW; pulled up internally
VSS(OSC) 74 ground for oscillator
XOUT_OSC 75[3] crystal out for oscillator
XIN_OSC 76[3] crystal in for oscillator
UM10316_0 © NXP B.V. 2008. All rights reserved.

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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VDD(OSC) 77 1.8 V supply for oscillator

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VSS(PLL) 78 ground for PLL

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P2[7]/MAT1[3]/ 79[1] GPIO 2, pin 7 TIMER1 MAT3 EXTINT3 EXTBUS D15

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EI3/D15

A
P3[14]/SDI1/ 80[1] GPIO 3, pin 14 SPI1 SDI EXTINT6 CAN0 TXD
EI6/TXDC0
P3[15]/SCK1/ 81[1] GPIO 3, pin 15 SPI1 SCK EXTINT7 CAN0 RXD
EI7/RXDC0
VDD(IO) 82 3.3 V power supply for I/O
P2[8]/ 83[1] GPIO 2, pin 8 CLK_OUT PWM0 MAT0 SPI0 SCS2
CLK_OUT/
PMAT0[0]/
SCS0[2]
P2[9]/PMAT0[1]/ 84[1] GPIO 2, pin 9 - PWM0 MAT1 SPI0 SCS1
SCS0[1]
P1[3]/SCS2[1]/ 85[1] GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 EXTBUS A3
PMAT3[3]/A3
P1[2]/SCS2[3]/ 86[1] GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2
PMAT3[2]/A2
P1[1]/EI1/ 87[1] GPIO 1, pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1
PMAT3[1]/A1
VSS(CORE) 88 ground for digital core
VDD(CORE) 89 1.8 V power supply for digital core
P1[0]/EI0/ 90[1] GPIO 1, pin 0 EXTINT0 PWM3 MAT0 EXTBUS A0
PMAT3[0]/A0
P2[10]/ 91[1] GPIO 2, pin 10 - PWM0 MAT2 SPI0 SCS0
PMAT0[2]/
SCS0[0]
P2[11]/ 92[1] GPIO 2, pin 11 - PWM0 MAT3 SPI0 SCK
PMAT0[3]/SCK0
P0[0]/PHB0/ 93[1] GPIO 0, pin 0 QEI0 PHB CAN0 TXD EXTBUS D24
TXDC0/D24
VSS(IO) 94 ground for I/O
P0[1]/PHA0/ 95[1] GPIO 0, pin 1 QEI 0 PHA CAN0 RXD EXTBUS D25
RXDC0/D25
P0[2]/ 96[1] GPIO 0, pin 2 CLK_OUT PWM0 MAT0 EXTBUS D26
CLK_OUT/
PMAT0[0]/D26
P0[3]/PMAT0[1]/ 97[1] GPIO 0, pin 3 - PWM0 MAT1 EXTBUS D27
D27
P3[0]/PMAT2[0]/ 98[1] GPIO 3, pin 0 - PWM2 MAT0 EXTBUS CS6
CS6
P3[1]/PMAT2[1]/ 99[1] GPIO 3, pin 1 - PWM2 MAT1 EXTBUS CS7
CS7
P2[12]/ 100[1] GPIO 2, pin 12 - PWM0 MAT4 SPI0 SDI
PMAT0[4]/SDI0
UM10316_0 © NXP B.V. 2008. All rights reserved.

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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A

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FT
P2[13]/ 101[1] GPIO 2, pin 13 - PWM0 MAT5 SPI0 SDO

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PMAT0[5]/

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SDO0

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P0[4]/PMAT0[2]/ 102[1] GPIO 0, pin 4 - PWM0 MAT2 EXTBUS D28

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A
D28
P0[5]/PMAT0[3]/ 103[1] GPIO 0, pin 5 - PWM0 MAT3 EXTBUS D29
D29
VDD(IO) 104 3.3 V power supply for I/O
P0[6]/ 105[1] GPIO 0, pin 6 - PWM0 MAT4 EXTBUS D30
PMAT0[4]/D30
P0[7]/ 106[1] GPIO 0, pin 7 - PWM0 MAT5 EXTBUS D31
PMAT0[5]/D31
VDDA(ADC3V3) 107 3.3 V power supply for ADC
JTAGSEL 108[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan and flash programming; pulled up internally.
n.c. 109 not connected to a function, must be tied to 3.3 V power supply for ADC VDDA(ADC3V3).
VREFP 110[3] HIGH reference for ADC
VREFN 111[3] LOW reference for ADC
P0[8]/IN1[0]/TX 112[4] GPIO 0, pin 8 ADC1 IN0 LIN0/UART TXD EXTBUS A20
DL0/A20
P0[9]/IN1[1]/ 113[4] GPIO 0, pin 9 ADC1 IN1 LIN0/UART RXD EXTBUS A21
RXDL0/A21
P0[10]/IN1[2]/ 114[4] GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8
PMAT1[0]/A8
P0[11]/IN1[3]/ 115[4] GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 EXTBUS A9
PMAT1[1]/A9
P2[14]/SDA1/ 116[1] GPIO 2, pin 14 I2C1 SDA PWM0 CAP0 EXTBUS BLS0
PCAP0[0]/BLS0
P2[15]/SCL1/ 117[1] GPIO 2, pin 15 I2C1 SCL PWM0 CAP1 EXTBUS BLS1
PCAP0[1]/BLS1
P3[2]/MAT3[0]/ 118[1] GPIO 3, pin 2 TIMER3 MAT0 PWM2 MAT2 -
PMAT2[2]
VSS(IO) 119 ground for I/O
P3[3]/MAT3[1]/ 120[1] GPIO 3, pin 3 TIMER3 MAT1 PWM2 MAT3 -
PMAT2[3]
P0[12]/IN1[4]/ 121[4] GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 EXTBUS A10
PMAT1[2]/A10
P0[13]/IN1[5]/ 122[4] GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 EXTBUS A11
PMAT1[3]/A11
P0[14]/IN1[6]/ 123[4] GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12
PMAT1[4]/A12
P0[15]/IN1[7]/ 124[4] GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 EXTBUS A13
PMAT1[5]/A13
P0[16]IN2[0]/ 125[4] GPIO 0, pin 16 ADC2 IN0 UART0 TXD EXTBUS A22
TXD0/A22

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Table 100. LPC2917/19/01 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 1 Function 2 Function 3

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A

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FT
P0[17]/IN2[1]/ 126[4] GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23

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RXD0/A23

R
A
FT
VDD(CORE) 127 1.8 V power supply for digital core

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R
VSS(CORE) 128 ground for digital core

A
P2[16]/TXD1/ 129[1] GPIO 2, pin 16 UART1 TXD PWM0 CAP2 EXTBUS BLS2
PCAP0[2]/BLS2
P2[17]/RXD1/ 130[1] GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS BLS3
PCAP1[0]/BLS3
VDD(IO) 131 3.3 V power supply for I/O
P0[18]/IN2[2]/ 132[4] GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
PMAT2[0]/A14
P0[19]/IN2[3]/ 133[4] GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
PMAT2[1]/A15
P3[4]/MAT3[2]/ 134[1] GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXD
PMAT2[4]/
TXDC1
P3[5]/MAT3[3]/ 135[1] GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXD
PMAT2[5]/
RXDC1
P2[18]/SCS2[1]/ 136[1] GPIO 2, pin 18 SPI2 SCS1 PWM1 CAP1 EXTBUS D16
PCAP1[1]/D16
P2[19]/SCS2[0]/ 137[1] GPIO 2, pin 19 SPI2 SCS0 PWM1 CAP2 EXTBUS D17
PCAP1[2]/D17
P0[20]/IN2[4]/ 138[4] GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
PMAT2[2]/A16
P0[21]/IN2[5]/ 139[4] GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
PMAT2[3]/A17
P0[22]/IN2[6]/ 140[4] GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18
PMAT2[4]/A18
VSS(IO) 141 ground for I/O
P0[23]/IN2[7]/ 142[4] GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
PMAT2[5]/A19
P2[20]/ 143[1] GPIO 2, pin 20 SPI2 SDO PWM2 CAP0 EXTBUS D18
PCAP2[0]/D18
TDI 144[1] IEEE 1149.1 data in, pulled up internally

[1] Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up /
Pull Down / Repeater.
[2] Analog Pad; Analog Input Output.
[3] Analog pad, <tbd>.

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3. LPC2921/23/25 pin configuration

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100

76

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1 75

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LPC2921FBD100
LPC2923FBD100
LPC2925FBD100

25 51

26

50
002aae242

Fig 28. Pin configuration for SOT407-1 (LQFP100)

The LPC2921/23/25 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and port 5
with 2 pins. Ports 4/3/2 are not used. The pin to which each function is assigned is
controlled by the SFSP registers in the SCU. The functions combined on each port pin are
shown in the pin description tables in this section.

Table 101. LPC2921/23/25 LQFP100 pin assignment

Pin name Pin Description
Function 0 (default) Function 1 Function 2 Function 3
TDO 1[1] IEEE 1149.1 test data out
P0[24]/TXD1/ 2[1] GPIO 0, pin 24 UART1 TXD CAN1 TXD SPI2 SCS0
TXDC1/SCS2[0]
P0[25]/RXD1/ 3[1] GPIO 0, pin 25 UART1 RXD CAN1 RXD SPI2 SDO
RXDC1/SDO2
P0[26]/TXD1/SDI2 4[1] GPIO 0, pin 26 - UART1 TXD SPI2 SDI
P0[27]/RXD1/SCK2 5[1] GPIO 0, pin 27 - UART1 RXD SPI2 SCK
P0[28]/CAP0[0]/ 6[1] GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0
MAT0[0]
P0[29]/CAP0[1]/ 7[1] GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1
MAT0[1]
VDD(IO) 8 3.3 V power supply for I/O
P0[30]/CAP0[2]/ 9[1] GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
MAT0[2]
P0[31]/CAP0[3]/ 10[1] GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3
MAT0[3]
VSS(IO) 11 ground for I/O
P5[19]/USB_D+ 12[2] GPIO 5, pin 19 USB_D+ - -
P5[18]/USB_D− 13[2] GPIO 5, pin 18 USB_D− - -
VDD(IO) 14 3.3 V power supply for I/O
VDD(CORE) 15 1.8 V power supply for digital core
VSS(CORE) 16 ground for core
VSS(IO) 17 ground for I/O

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Table 101. LPC2921/23/25 LQFP100 pin assignment …continued

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Pin name Pin Description

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FT

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Function 0 (default) Function 1 Function 2 Function 3

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R

A
A

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FT
P1[27]/CAP1[2]/ 18[1] GPIO 1, pin 27 TIMER1 CAP2, PWM TRAP2 PWM3 MAT3

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D
TRAP2/PMAT3[3] ADC2 EXT START

R
A
FT
P1[26]/PMAT2[0]/ 19[1] GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2

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TRAP3/PMAT3[2]

R
A
VDD(IO) 20 3.3 V power supply for I/O
P1[25]/PMAT1[0]/ 21[1] GPIO 1, pin 25 PWM1 MAT0 USB_VBUS PWM3 MAT1
USB_VBUS/
PMAT3[1]
P1[24]/PMAT0[0]/ 22[1] GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT PWM3 MAT0
USB_CONNECT/
PMAT3[0]
P1[23]/RXD0 23[1] GPIO 1, pin 23 UART0 RXD - -
P1[22]/TXD0/ 24[1] GPIO 1, pin 22 UART0 TXD USB_UP_LED -
USB_UP_LED
TMS 25[1] IEEE 1149.1 test mode select, pulled up internally
TCK 26[1] IEEE 1149.1 test clock
P1[21]/CAP3[3]/ 27[1] GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3, -
CAP1[3] MSCSS PAUSE
P1[20]/CAP3[2]/ 28[1] GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 -
SCS0[1]
P1[19]/CAP3[1]/ 29[1] GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 -
SCS0[2]
P1[18]/CAP3[0]/ 30[1] GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO -
SDO0
P1[17]/CAP2[3]/ 31[1] GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI -
SDI0
VSS(IO) 32 ground for I/O
P1[16]/CAP2[2]/ 33[1] GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK -
SCK0
P1[15]/CAP2[1]/ 34[1] GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 -
SCS0[0]
P1[14]/CAP2[0]/ 35[1] GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 -
SCS0[3]
P1[13]/EI3/SCL1 36[1] GPIO 1, pin 13 EXTINT3 I2C1 SCL -
P1[12]/EI2/SDA1 37[1] GPIO 1, pin 12 EXTINT2 I2C1 SDA -

VDD(IO) 38 3.3 V power supply for I/O

P1[11]/SCK1/SCL0 39[1] GPIO 1, pin 11 SPI1 SCK I2C0 SCL -
P1[10]/SDI1/SDA0 40[1] GPIO 1, pin 10 SPI1 SDI I2C0 SDA -
VSS(CORE) 41 ground for digital core
VDD(CORE) 42 1.8 V power supply for digital core
P1[9]/SDO1 43[1] GPIO 1, pin 9 SPI1 SDO - -
VSS(IO) 44 ground for I/O

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Table 101. LPC2921/23/25 LQFP100 pin assignment …continued

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Pin name Pin Description

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Function 0 (default) Function 1 Function 2 Function 3

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R

A
A

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FT
P1[8]/SCS1[0]/ 45[1] GPIO 1, pin 8 SPI1 SCS0 - -

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TXDL1/CS0

R
A
FT
P1[7]/SCS1[3]/RXD1 46[1] GPIO 1, pin 7 SPI1 SCS3 UART1 RXD -

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R
P1[6]/SCS1[2]/TXD1 47[1] GPIO 1, pin 6 SPI1 SCS2 UART1 TXD -

A
P1[5]/SCS1[1]/ 48[1] GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 -
PMAT3[5]
P1[4]/SCS2[2]/ 49[1] GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 -
PMAT3[4]
TRST_N 50[1] IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RST_N 51[1] asynchronous device reset; active LOW; pulled up internally
VSS(OSC) 52 ground for oscillator
XOUT_OSC 53[3] crystal out for oscillator
XIN_OSC 54[3] crystal in for oscillator
VDD(OSC) 55 1.8 V supply for oscillator.
VSS(PLL) 56 ground for PLL
VDD(IO) 57 3.3 V power supply for I/O
P1[3]/SCS2[1]/ 58[1] GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 -
PMAT3[3]
P1[2]/SCS2[3]/ 59[1] GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 -
PMAT3[2]
P1[1]/EI1/PMAT3[1] 60[1] GPIO 1, pin 1 EXTINT1 PWM3 MAT1 -
VSS(CORE) 61 ground for digital core
VDD(CORE) 62 1.8 V power supply for digital core
P1[0]/EI0/PMAT3[0] 63[1] GPIO 1, pin 0 EXTINT0 PWM3 MAT0 -
P0[0]/PHB0/ 64[1] GPIO 0, pin 0 QEI0 PHB CAN0 TXD -
TXDC0/D24
VSS(IO) 65 ground for I/O
P0[1]/PHA0/RXDC0 66[1] GPIO 0, pin 1 QEI0 PHA CAN0 RXD -
P0[2]/CLK_OUT/ 67[1] GPIO 0, pin 2 CLK_OUT PWM0 MAT0 -
PMAT0[0]
P0[3]/USB_UP_LED/ 68[1] GPIO 0, pin 3 USB_UP_LED PWM0 MAT1 -
PMAT0[1]
P0[4]/PMAT0[2] 69[1] GPIO 0, pin 4 - PWM0 MAT2 -
P0[5]/PMAT0[3] 70[1] GPIO 0, pin 5 - PWM0 MAT3 -
VDD(IO) 71 3.3 V power supply for I/O
P0[6]/PMAT0[4] 72[1] GPIO 0, pin 6 - PWM0 MAT4 -
P0[7]/PMAT0[5] 73[1] GPIO 0, pin 7 - PWM0 MAT5 -
VDDA(ADC3V3) 74 3.3 V power supply for ADC
JTAGSEL 75[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan and flash programming; pulled up internally.
n.c. 76 not connected to a function, must be tied to 3.3 V power supply for ADC VDDA(ADC3V3).
VREFP 77[3] HIGH reference for ADC

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Table 101. LPC2921/23/25 LQFP100 pin assignment …continued

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Pin name Pin Description

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Function 0 (default) Function 1 Function 2 Function 3

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A

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FT
VREFN 78[3] LOW reference for ADC

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P0[8]/IN1[0] 79[4] GPIO 0, pin 8 ADC1 IN0 - -

A
FT
P0[9]/IN1[1] 80[4] GPIO 0, pin 9 ADC1 IN1 - -

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R
A
P0[10]/IN1[2]/ 81[4] GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 -
PMAT1[0]
P0[11]/IN1[3]/ 82[4] GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 -
PMAT1[1]
VSS(IO) 83 ground for I/O
P0[12]/IN1[4]/ 84[4] GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 -
PMAT1[2]
P0[13]/IN1[5]/ 85[4] GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 -
PMAT1[3]
P0[14]/IN1[6]/ 86[4] GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 -
PMAT1[4]
P0[15]/IN1[7]/ 87[4] GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 -
PMAT1[5]
P0[16]IN2[0]/TXD0 88[4] GPIO 0, pin 16 ADC2 IN0 UART0 TXD -
P0[17]/IN2[1]/ 89[4] GPIO 0, pin 17 ADC2 IN1 UART0 RXD -
RXD0/A23
VDD(CORE) 90 1.8 V power supply for digital core
VSS(CORE) 91 ground for digital core
VDD(IO) 92 3.3 V power supply for I/O
P0[18]/IN2[2]/ 93[4] GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 -
PMAT2[0]
P0[19]/IN2[3]/ 94[4] GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 -
PMAT2[1]
P0[20]/IN2[4]/ 95[4] GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 -
PMAT2[2]
P0[21]/IN2[5]/ 96[4] GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 -
PMAT2[3]
P0[22]/IN2[6]/ 97[4] GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 -
PMAT2[4]/A18
VSS(IO) 98 ground for I/O

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Table 101. LPC2921/23/25 LQFP100 pin assignment …continued

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Pin name Pin Description

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Function 0 (default) Function 1 Function 2 Function 3

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A

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P0[23]/IN2[7]/ 99[4] GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 -

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PMAT2[5]/A19

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TDI 100[1] IEEE 1149.1 data in, pulled up internally

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[1] Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up /
Pull Down / Repeater.
[2] USB pad, <tbd>.
[3] Analog Pad; Analog Input Output.
[4] Analog I/O pad, <tbd>.

4. LPC2927/29 pin configuration

The LPC2927/29 uses five ports: port 0 with 32 pins, ports 1 and 2 with 26 pins each, port
3 with 16 pins, and port 5 with 2 pins. Port 4 is not used. The pin to which each function is
assigned is controlled by the SFSP registers in the SCU. The functions combined on each
port pin are shown in the pin description tables in this section.
144

109
1 108

LPC2927FBD144
LPC2929FBD144

36 73
37

72

002aae144

Fig 29. Pin configuration for SOT486-1 (LQFP144)

Table 102. LPC2927/29 LQFP144 pin assignment

Pin name Pin Description
Default function Function 0 Function 1 Function 2 Function 3
TDO 1[1] IEEE 1149.1 test data out
P2[21]SDI2/ 2[1] GPIO 2, pin 21 GPIO 2, pin 21 SPI2 SDI PWM2 CAP1 EXTBUS D19
PCAP2[1]/D19
P0[24]/TXD1/ 3[1] GPIO 0, pin 24 GPIO 0, pin 24 UART1 TXD CAN1 TXD SPI2 SCS0
TXDC1/SCS2[0]
P0[25]/RXD1/ 4[1] GPIO 0, pin 25 GPIO 0, pin 25 UART1 RXD CAN1 RXD SPI2 SDO
RXDC1/SDO2
P0[26]/TXD1/ 5[1] GPIO 0, pin 26 GPIO 0, pin 26 - UART1 TXD SPI2 SDI
SDI2
P0[27]/RXD1/ 6[1] GPIO 0, pin 27 GPIO 0, pin 27 - UART1 RXD SPI2 SCK
SCK2

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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A

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P0[28]/CAP0[0]/ 7[1] GPIO 0, pin 28 GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0

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MAT0[0]

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FT
P0[29]/CAP0[1]/ 8[1] GPIO 0, pin 29 GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1

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MAT0[1]

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VDD(IO) 9 3.3 V power supply for I/O
P2[22]/SCK2/ 10[1] GPIO 2, pin 22 GPIO 2, pin 22 SPI2 SCK PWM2 CAP2 EXTBUS D20
PCAP2[2]/D20
P2[23]/SCS1[0]/ 11[1] GPIO 2, pin 23 GPIO 2, pin 23 SPI1 SCS0 PWM3 CAP0 EXTBUS D21
PCAP3[0]/D21
P3[6]/SCS0[3]/ 12[1] GPIO 3, pin 6 GPIO 3, pin 6 SPI0 SCS3 PWM1 MAT0 LIN1/UART
PMAT1[0]/ TXD
TXDL1
P3[7]/SCS2[1]/ 13[1] GPIO 3, pin 7 GPIO 3, pin 7 SPI2 SCS1 PWM1 MAT1 LIN1/UART
PMAT1[1]/ RXD
RXDL1
P0[30]/CAP0[2]/ 14[1] GPIO 0, pin 30 GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
MAT0[2]
P0[31]/CAP0[3]/ 15[1] GPIO 0, pin 31 GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3
MAT0[3]
P2[24]/SCS1[1]/ 16[1] GPIO 2, pin 24 GPIO 2, pin 24 SPI1 SCS1 PWM3 CAP1 EXTBUS D22
PCAP3[1]/D22
P2[25]/SCS1[2]/ 17[1] GPIO 2, pin 25 GPIO 2, pin 25 SPI1 SCS2 PWM3 CAP2 EXTBUS D23
PCAP3[2]/D23
VSS(IO) 18 ground for I/O
USB_D+/P5[19] 19[2] USB_D+ GPIO 5, pin 19 USB_D+ - -
USB_D−/P5[18] 20[2] USB_D− GPIO 5, pin 18 USB_D− - --
VDD(IO) 21 3.3 V power supply for I/O
VDD(CORE) 22 1.8 V power supply for digital core
VSS(CORE) 23 ground for core
VSS(IO) 24 ground for I/O
P3[8]/SCS2[0]/ 25[1] GPIO 3, pin 8 GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 -
PMAT1[2]
P3[9]/SDO2/ 26[1] GPIO 3, pin 9 GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 -
PMAT1[3]
P2[26]/CAP0[2]/ 27[1] GPIO 2, pin 26 GPIO 2, pin 26 TIMER0 CAP2 TIMER0 MAT2 EXTINT6
MAT0[2]/EI6
P2[27]/CAP0[3]/ 28[1] GPIO 2, pin 27 GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7
MAT0[3]/EI7
P1[27]/CAP1[2]/ 29[1] GPIO 1, pin 27 GPIO 1, pin 27 TIMER1 CAP2, PWM TRAP2 PWM3 MAT3
TRAP2/ ADC2 EXT
PMAT3[3] START
P1[26]/ 30[1] GPIO 1, pin 26 GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2
PMAT2[0]/
TRAP3/
PMAT3[2]

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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A

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FT
VDD(IO) 31 3.3 V power supply for I/O

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P1[25]/ 32[1] GPIO 1, pin 25 GPIO 1, pin 25 PWM1 MAT0 VBUS PWM3 MAT1

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FT
PMAT1[0]/VBUS/

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PMAT3[1]

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A
P1[24]/ 33[1] GPIO 1, pin 24 GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT PWM3 MAT0
PMAT0[0]/
USB_CONNECT/
PMAT3[0]
P1[23]/ 34[1] GPIO 1, pin 23 GPIO 1, pin 23 UART0 RXD USB_SSPND EXTBUS CS5
RXD0/
USB_SSPND/
CS5
P1[22]/TXD0/ 35[1] GPIO 1, pin 22 GPIO 1, pin 22 UART0 TXD USB_UP_LED EXTBUS CS4
USB_UP_LED/
CS4
TMS 36[1] IEEE 1149.1 test mode select, pulled up internally
TCK 37[1] IEEE 1149.1 test clock
P1[21]/CAP3[3]/ 38[1] GPIO 1, pin 21 GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3, EXTBUS D7
CAP1[3]/D7 MSCSS PAUSE
P1[20]/CAP3[2]/ 39[1] GPIO 1, pin 20 GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6
SCS0[1]/D6
P1[19]/CAP3[1]/ 40[1] GPIO 1, pin 19 GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5
SCS0[2]/D5
P1[18]/CAP3[0]/ 41[1] GPIO 1, pin 18 GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO EXTBUS D4
SDO0/D4
P1[17]/CAP2[3]/ 42[1] GPIO 1, pin 17 GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI EXTBUS D3
SDI0/D3
VSS(IO) 43 ground for I/O
P1[16]/CAP2[2]/ 44[1] GPIO 1, pin 16 GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK EXTBUS D2
SCK0/D2
P2[0]/MAT2[0]/ 45[1] GPIO 2, pin 0 GPIO 2, pin 0 TIMER2 MAT0 PWM TRAP3 EXTBUS D8
TRAP3/D8
P2[1]/MAT2[1]/ 46[1] GPIO 2, pin 1 GPIO 2, pin 1 TIMER2 MAT1 PWM TRAP2 EXTBUS D9
TRAP2/D9
P3[10]/SDI2/ 47[1] GPIO 3, pin 10 GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 -
PMAT1[4]
P3[11]/SCK2/ 48[1] GPIO 3, pin 11 GPIO 3, pin 11 SPI2 SCK PWM1 MAT5 USB_LS
PMAT1[5]/
USB_LS
P1[15]/CAP2[1]/S 49[1] GPIO 1, pin 15 GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 EXTBUS D1
CS0[0]/D1
P1[14]/CAP2[0]/S 50[1] GPIO 1, pin 14 GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0
CS0[3]/D0
P1[13]/SCL1/ 51[1] GPIO 1, pin 13 GPIO 1, pin 13 EXTINT3 I2C1 SCL EXTBUS
EI3/WE_N WE_N

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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P1[12]/SDA1/ 52[1] GPIO 1, pin 12 GPIO 1, pin 12 EXTINT2 I2C1 SDA EXTBUS

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EI2/OE_N OE_N

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A
FT
VDD(IO) 53 3.3 V power supply for I/O

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P2[2]/MAT2[2]/ 54[1] GPIO 2, pin 2 GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10

A
TRAP1/D10
P2[3]/MAT2[3]/ 55[1] GPIO 2, pin 3 GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11
TRAP0/D11
P1[11]/SCK1/ 56[1] GPIO 1, pin 11 GPIO 1, pin 11 SPI1 SCK I2C0 SCL EXTBUS CS3
SCL0/CS3
P1[10]/SDI1/ 57[1] GPIO 1, pin 10 GPIO 1, pin 10 SPI1 SDI I2C0 SDA EXTBUS CS2
SDA0/CS2
P3[12]/SCS1[0]/ 58[1] GPIO 3, pin 12 GPIO 3, pin 12 SPI1 SCS0 EXTINT4 USB_SSPND
EI4/
USB_SSPND
VSS(CORE) 59 ground for digital core
VDD(CORE) 60 1.8 V power supply for digital core
P3[13]/SDO1/ 61[1] GPIO 3, pin 13 GPIO 3, pin 13 SPI1 SDO EXTINT5 QEI0 IDX
EI5/IDX0
P2[4]/MAT1[0]/ 62[1] GPIO 2, pin 4 GPIO 2, pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12
EI0/D12
P2[5]/MAT1[1]/ 63[1] GPIO 2, pin 5 GPIO 2, pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13
EI1/D13
P1[9]/SDO1/ 64[1] GPIO 1, pin 9 GPIO 1, pin 9 SPI1 SDO LIN1 RXD/UART EXTBUS CS1
RXDL1/CS1 RXD
VSS(IO) 65 ground for I/O
P1[8]/SCS1[0]/ 66[1] GPIO 1, pin 8 GPIO 1, pin 8 SPI1 SCS0 LIN1 TXD/ UART EXTBUS CS0
TXDL1/CS0 TXD
P1[7]/SCS1[3]/RX 67[1] GPIO 1, pin 7 GPIO 1, pin 7 SPI1 SCS3 UART1 RXD EXTBUS A7
D1/A7
P1[6]/SCS1[2]/ 68[1] GPIO 1, pin 6 GPIO 1, pin 6 SPI1 SCS2 UART1 TXD EXTBUS A6
TXD1/A6
P2[6]/MAT1[2]/ 69[1] GPIO 2, pin 6 GPIO 2, pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14
EI2/D14
P1[5]/SCS1[1]/PM 70[1] GPIO 1, pin 5 GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5
AT3[5]/A5
P1[4]/SCS2[2]/PM 71[1] GPIO 1, pin 4 GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4
AT3[4]/A4
TRST_N 72[1] IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RST_N 73[1] asynchronous device reset; active LOW; pulled up internally
VSS(OSC) 74 ground for oscillator
XOUT_OSC 75[3] crystal out for oscillator
XIN_OSC 76[3] crystal in for oscillator
VDD(OSC_PLL) 77 1.8 V supply for oscillator and PLL
VSS(PLL) 78 ground for PLL

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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P2[7]/MAT1[3]/ 79[1] GPIO 2, pin 7 GPIO 2, pin 7 TIMER1 MAT3 EXTINT3 EXTBUS D15

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EI3/D15

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FT
P3[14]/SDI1/ 80[1] GPIO 3, pin 14 GPIO 3, pin 14 SPI1 SDI EXTINT6 CAN0 TXD

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EI6/TXDC0

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A
P3[15]/SCK1/ 81[1] GPIO 3, pin 15 GPIO 3, pin 15 SPI1 SCK EXTINT7 CAN0 RXD
EI7/RXDC0
VDD(IO) 82 3.3 V power supply for I/O
P2[8]/ 83[1] GPIO 2, pin 8 GPIO 2, pin 8 CLK_OUT PWM0 MAT0 SPI0 SCS2
CLK_OUT/
PMAT0[0]/
SCS0[2]
P2[9]/ 84[1] GPIO 2, pin 9 GPIO 2, pin 9 USB_UP_LED PWM0 MAT1 SPI0 SCS1
USB_UP_LED/
PMAT0[1]/
SCS0[1]
P1[3]/SCS2[1]/ 85[1] GPIO 1, pin 3 GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 EXTBUS A3
PMAT3[3]/A3
P1[2]/SCS2[3]/ 86[1] GPIO 1, pin 2 GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2
PMAT3[2]/A2
P1[1]/EI1/ 87[1] GPIO 1, pin 1 GPIO 1, pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1
PMAT3[1]/A1
VSS(CORE) 88 ground for digital core
VDD(CORE) 89 1.8 V power supply for digital core
P1[0]/EI0/ 90[1] GPIO 1, pin 0 GPIO 1, pin 0 EXTINT0 PWM3 MAT0 EXTBUS A0
PMAT3[0]/A0
P2[10]/ 91[1] GPIO 2, pin 10 GPIO 2, pin 10 - PWM0 MAT2 SPI0 SCS0
PMAT0[2]/
SCS0[0]
P2[11]/ 92[1] GPIO 2, pin 11 GPIO 2, pin 11 - PWM0 MAT3 SPI0 SCK
PMAT0[3]/SCK0
P0[0]/PHB0/ 93[1] GPIO 0, pin 0 GPIO 0, pin 0 QEI0 PHB CAN0 TXD EXTBUS D24
TXDC0/D24
VSS(IO) 94 ground for I/O
P0[1]/PHA0/ 95[1] GPIO 0, pin 1 GPIO 0, pin 1 QEI 0 PHA CAN0 RXD EXTBUS D25
RXDC0/D25
P0[2]/ 96[1] GPIO 0, pin 2 GPIO 0, pin 2 CLK_OUT PWM0 MAT0 EXTBUS D26
CLK_OUT/
PMAT0[0]/D26
P0[3]/ 97[1] GPIO 0, pin 3 GPIO 0, pin 3 USB_UP_LED PWM0 MAT1 EXTBUS D27
USB_UP_LED/
PMAT0[1]/D27
P3[0]/IN0[6]/ 98[1] GPIO 3, pin 0 GPIO 3, pin 0 ADC0 IN6 PWM2 MAT0 EXTBUS CS6
PMAT2[0]/CS6
P3[1]/IN0[7/ 99[1] GPIO 3, pin 1 GPIO 3, pin 1 ADC0 IN7 PWM2 MAT1 EXTBUS CS7
PMAT2[1]/CS7

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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A

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FT
P2[12]/IN0[4] 100[1] GPIO 2, pin 12 GPIO 2, pin 12 ADC0 IN4 PWM0 MAT4 SPI0 SDI

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PMAT0[4]/SDI0

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A
FT
P2[13]/IN0[5] 101[1] GPIO 2, pin 13 GPIO 2, pin 13 ADC0 IN5 PWM0 MAT5 SPI0 SDO

D
PMAT0[5]/

R
A
SDO0
P0[4]/IN0[0]/ 102[1] GPIO 0, pin 4 GPIO 0, pin 4 ADC0 IN0 PWM0 MAT2 EXTBUS D28
PMAT0[2]/D28
P0[5]/IN0[1]/ 103[1] GPIO 0, pin 5 GPIO 0, pin 5 ADC0 IN1 PWM0 MAT3 EXTBUS D29
PMAT0[3]/D29
VDD(IO) 104 3.3 V power supply for I/O
P0[6]/IN0[2]/ 105[1] GPIO 0, pin 6 GPIO 0, pin 6 ADC0 IN2 PWM0 MAT4 EXTBUS D30
PMAT0[4]/D30
P0[7]/IN0[3]/ 106[1] GPIO 0, pin 7 GPIO 0, pin 7 ADC0 IN3 PWM0 MAT5 EXTBUS D31
PMAT0[5]/D31
VDDA(ADC3V3) 107 3.3 V power supply for ADC
JTAGSEL 108[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan and flash programming; pulled up internally.
VDDA(ADC5V0) 109 5 V supply voltage for ADC0 and 5 V reference for ADC0.
VREFP 110[3] HIGH reference for ADC
VREFN 111[3] LOW reference for ADC
P0[8]/IN1[0]/TXDL 112[4] GPIO 0, pin 8 GPIO 0, pin 8 ADC1 IN0 LIN0 TXD/ UART EXTBUS A20
0/A20 TXD
P0[9]/IN1[1]/ 113[4] GPIO 0, pin 9 GPIO 0, pin 9 ADC1 IN1 LIN0 RXD/ UART EXTBUS A21
RXDL0/A21 TXD
P0[10]/IN1[2]/ 114[4] GPIO 0, pin 10 GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8
PMAT1[0]/A8
P0[11]/IN1[3]/ 115[4] GPIO 0, pin 11 GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 EXTBUS A9
PMAT1[1]/A9
P2[14]/SDA1/ 116[1] GPIO 2, pin 14 GPIO 2, pin 14 I2C1 SDA PWM0 CAP0 EXTBUS
PCAP0[0]/BLS0 BLS0
P2[15]/SCL1/ 117[1] GPIO 2, pin 15 GPIO 2, pin 15 I2C1 SCL PWM0 CAP1 EXTBUS
PCAP0[1]/BLS1 BLS1
P3[2]/MAT3[0]/ 118[1] GPIO 3, pin 2 GPIO 3, pin 2 TIMER3 MAT0 PWM2 MAT2 USB_SDA
PMAT2[2]/
USB_SDA
VSS(IO) 119 ground for I/O
P3[3]/MAT3[1]/ 120[1] GPIO 3, pin 3 GPIO 3, pin 3 TIMER3 MAT1 PWM2 MAT3 USB_SCL
PMAT2[3]/
USB_SCL
P0[12]/IN1[4]/ 121[4] GPIO 0, pin 12 GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 EXTBUS A10
PMAT1[2]/A10
P0[13]/IN1[5]/ 122[4] GPIO 0, pin 13 GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 EXTBUS A11
PMAT1[3]/A11
P0[14]/IN1[6]/ 123[4] GPIO 0, pin 14 GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12
PMAT1[4]/A12

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Table 102. LPC2927/29 LQFP144 pin assignment …continued

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Pin name Pin Description

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Default function Function 0 Function 1 Function 2 Function 3

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P0[15]/IN1[7]/ 124[4] GPIO 0, pin 15 GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 EXTBUS A13

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PMAT1[5]/A13

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FT
P0[16]IN2[0]/ 125[4] GPIO 0, pin 16 GPIO 0, pin 16 ADC2 IN0 UART0 TXD EXTBUS A22

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TXD0/A22

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P0[17]/IN2[1]/ 126[4] GPIO 0, pin 17 GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23
RXD0/A23
VDD(CORE) 127 1.8 V power supply for digital core
VSS(CORE) 128 ground for digital core
P2[16]/TXD1/ 129[1] GPIO 2, pin 16 GPIO 2, pin 16 UART1 TXD PWM0 CAP2 EXTBUS
PCAP0[2]/BLS2 BLS2
P2[17]/RXD1/ 130[1] GPIO 2, pin 17 GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS
PCAP1[0]/BLS3 BLS3
VDD(IO) 131 3.3 V power supply for I/O
P0[18]/IN2[2]/ 132[4] GPIO 0, pin 18 GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
PMAT2[0]/A14
P0[19]/IN2[3]/ 133[4] GPIO 0, pin 19 GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
PMAT2[1]/A15
P3[4]/MAT3[2]/ 134[1] GPIO 3, pin 4 GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXD
PMAT2[4]/
TXDC1
P3[5]/MAT3[3]/ 135[1] GPIO 3, pin 5 GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXD
PMAT2[5]/
RXDC1
P2[18]/SCS2[1]/ 136[1] GPIO 2, pin 18 GPIO 2, pin 18 SPI2 SCS1 PWM1 CAP1 EXTBUS D16
PCAP1[1]/D16
P2[19]/SCS2[0]/ 137[1] GPIO 2, pin 19 GPIO 2, pin 19 SPI2 SCS0 PWM1 CAP2 EXTBUS D17
PCAP1[2]/D17
P0[20]/IN2[4]/ 138[4] GPIO 0, pin 20 GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
PMAT2[2]/A16
P0[21]/IN2[5]/ 139[4] GPIO 0, pin 21 GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
PMAT2[3]/A17
P0[22]/IN2[6]/ 140[4] GPIO 0, pin 22 GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18
PMAT2[4]/A18
VSS(IO) 141 ground for I/O
P0[23]/IN2[7]/ 142[4] GPIO 0, pin 23 GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
PMAT2[5]/A19
P2[20]/ 143[1] GPIO 2, pin 20 GPIO 2, pin 20 SPI2 SDO PWM2 CAP0 EXTBUS D18
PCAP2[0]/D18
TDI 144[1] IEEE 1149.1 data in, pulled up internally

[1] Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up /
Pull Down / Repeater.
[2] usb11f1
[3] Analog Pad; Analog Input Output.
[4] mco_dio_aio_t5v

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5. LPC2930/30 pin configuration

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LPC2939FBD208

52 105

104
53
002aae253

Fig 30. Pin configuration for LQFP208 package

The LPC2930/29 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each,
port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each
function is assigned is controlled by the SFSP registers in the SCU. The functions
combined on each port pin are shown in the pin description tables in this section.

Table 103. LPC2930/39 LQFP208 pin assignment

Pin name Pin Description
Function 0 Function 1 Function 2 Function 3
(default)
TDO 1[1] IEEE 1149.1 test data out
P2[21]SDI2/ 2[1] GPIO 2, pin 21 SPI2 SDI PWM2 CAP1 EXTBUS D19
PCAP2[1]/D19
P0[24]/TXD1/ 3[1] GPIO 0, pin 24 UART1 TXD CAN1 TXD SPI2 SCS0
TXDC1/SCS2[0]
P0[25]/RXD1/ 4[1] GPIO 0, pin 25 UART1 RXD CAN1 RXD SPI2 SDO
RXDC1/SDO2
P0[26]/TXD1/SDI2 5[1] GPIO 0, pin 26 - UART1 TXD SPI2 SDI
P0[27]/RXD1/SCK2 6[1] GPIO 0, pin 27 - UART1 RXD SPI2 SCK
P0[28]/CAP0[0]/ 7[1] GPIO 0, pin 28 - TIMER0 CAP0 TIMER0 MAT0
MAT0[0]
P0[29]/CAP0[1]/ 8[1] GPIO 0, pin 29 - TIMER0 CAP1 TIMER0 MAT1
MAT0[1]
VDD(IO) 9 3.3 V power supply for I/O
P2[22]/SCK2/ 10[1] GPIO 2, pin 22 SPI2 SCK PWM2 CAP2 EXTBUS D20
PCAP2[2]/D20
P2[23]/SCS1[0]/ 11[1] GPIO 2, pin 23 SPI1 SCS0 PWM3 CAP0 EXTBUS D21
PCAP3[0]/D21
P3[6]/SCS0[3]/ 12[1] GPIO 3, pin 6 SPI0 SCS3 PWM1 MAT0 LIN1/UART TXD
PMAT1[0]/TXDL1
P3[7]/SCS2[1]/ 13[1] GPIO 3, pin 7 SPI2 SCS1 PWM1 MAT1 LIN1/UART RXD
PMAT1[1]/RXDL1
P0[30]/CAP0[2]/ 14[1] GPIO 0, pin 30 - TIMER0 CAP2 TIMER0 MAT2
MAT0[2]

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
(default)

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P0[31]/CAP0[3]/ 15[1] GPIO 0, pin 31 - TIMER0 CAP3 TIMER0 MAT3

R
A
MAT0[3]

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P2[24]/SCS1[1]/ 16[1] GPIO 2, pin 24 SPI1 SCS1 PWM3 CAP1 EXTBUS D22

R
A
PCAP3[1]/D22
P2[25]/SCS1[2]/ 17[1] GPIO 2, pin 25 SPI1 SCS2 PWM3 CAP2 EXTBUS D23
PCAP3[2]/D23
VSS(IO) 18 ground for I/O
P5[19]/USB_D+1 19[2] GPIO 5, pin 19 USB_D+1 - -
P5[18]/USB_D−1 20[2] GPIO 5, pin 18 US_D−1 - -
P5[17]/USB_D+2 21[2] GPIO 5, pin 17 USB_D+2 - -
P5[16]/USB_D−2 22[2] GPIO 5, pin 16 USB_D−2 - -
VDD(IO) 23 3.3 V power supply for I/O
VDD(CORE) 24 1.8 V power supply for digital core
VSS(CORE) 25 ground for core
P1[31]/CAP0[1]/ 26[1] GPIO 1, pin 31 TIMER0 CAP1 TIMER0 MAT1 EXTINT5
MAT0[1]/EI5
VSS(IO) 27 ground for I/O
P4[0]/A8 28[1] GPIO 4, pin 0 EXTBUS A8 - -
P1[31]/CAP0[0]/ 29[1] GPIO 1, pin 31 TIMER0 CAP0 TIMER0 MAT0 EXTINT4
MAT0[0]/EI4
P5[0]/D8 30[1] GPIO 5, pin 0 EXTBUS D8 - -
P3[8]/SCS2[0]/ 31[1] GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 -
PMAT1[2]
P3[9]/SDO2/ 32[1] GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 USB_PPWR1
PMAT1[3]/
USB_PPWR1
P1[29]/CAP1[0]/ 33[1] GPIO 1, pin 29 TIMER1 CAP0/ PWM TRAP0 PWM3 MAT5
TRAP0/ PMAT3[5] ADC0 EXTSTART
VDD(IO) 34 3.3 V power supply for I/O
P4[16]/CS6/ 35[1] GPIO 4, pin 16 EXTBUS CS6 UART1 OUT1 -
U1OUT[1]
P1[28]/CAP1[1]/ 36[1] GPIO 1, pin 28 TIMER1 CAP1/ PWM TRAP1 PWM3 MAT4
TRAP1/PMAT3[4] ADC1 EXTSTART
P2[26]/CAP0[2]/ 37[1] GPIO 2, pin 26 TIMER0 CAP2 TIMER0 MAT2 EXTINT6
MAT0[2]/EI6
P4[8]/A22/DSR1 38 GPIO 4, pin 8 EXTBUS A22 UART1 DSR -
VSS(IO) 39 ground for I/O
P2[27]/CAP0[3]/ 40[1] GPIO 2, pin 27 TIMER0 CAP3 TIMER0 MAT3 EXTINT7
MAT0[3]/EI7
P5[8]/D20/U0OUT2 41[1] GPIO 5, pin 8 EXTBUS D20 UART0 OUT2 -
P1[27]/CAP1[2]/ 42[1] GPIO 1, pin 27 TIMER1 CAP2, ADC2 PWM TRAP2 PWM3 MAT3
TRAP2/PMAT3[3] EXT START

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
A
(default)

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P1[26]/PMAT2[0]/ 43[1] GPIO 1, pin 26 PWM2 MAT0 PWM TRAP3 PWM3 MAT2

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A
TRAP3/PMAT3[2]

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P4[20]/ 44[1] GPIO4, pin 20 USB_VBUS2

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A
USB_VBUS2
VDD(IO) 45 3.3 V power supply for I/O
P1[25]/PMAT1[0]/ 46[1] GPIO 1, pin 25 PWM1 MAT0 USB_VBUS1 PWM3 MAT1
USB_VBUS1/
PMAT3[1]
VSS(CORE) 47 ground for core
VDD(CORE) 48 1.8 V power supply for digital core
P1[24]/PMAT0[0]/ 49[1] GPIO 1, pin 24 PWM0 MAT0 USB_CONNECT1 PWM3 MAT0
USB_CONNECT1/
PMAT3[0]
P1[23]/RXD0/ 50[1] GPIO 1, pin 23 UART0 RXD USB_SSPND1 EXTBUS CS5
USB_SSPND1/
CS5
P1[22]/TXD0/ 51[1] GPIO 1, pin 22 UART0 TXD USB_UP_LED1 EXTBUS CS4
USB_UP_LED1/CS4
TMS 52[1] IEEE 1149.1 test mode select, pulled up internally
TCK 53[1] IEEE 1149.1 test clock
P1[21]/CAP3[3]/ 54[1] GPIO 1, pin 21 TIMER3 CAP3 TIMER1 CAP3, EXTBUS D7
CAP1[3]/D7 MSCSS PAUSE
P1[20]/CAP3[2]/ 55[1] GPIO 1, pin 20 TIMER3 CAP2 SPI0 SCS1 EXTBUS D6
SCS0[1]/D6
P1[19]/CAP3[1]/ 56[1] GPIO 1, pin 19 TIMER3 CAP1 SPI0 SCS2 EXTBUS D5
SCS0[2]/D5
P1[18]/CAP3[0]/ 57[1] GPIO 1, pin 18 TIMER3 CAP0 SPI0 SDO EXTBUS D4
SDO0/D4
P1[17]/CAP2[3]/ 58[1] GPIO 1, pin 17 TIMER2 CAP3 SPI0 SDI EXTBUS D3
SDI0/D3
VSS(IO) 59 ground for I/O
P4[4]/A12 60[1] GPIO 4, pin 4 A12 - -
P1[16]/CAP2[2]/ 61[1] GPIO 1, pin 16 TIMER2 CAP2 SPI0 SCK EXTBUS D2
SCK0/D2
P5[4]/D16 62[1] GPIO 5, pin 4 EXTBUS D16 - -
P2[0]/MAT2[0]/ 63[1] GPIO 2, pin 0 TIMER2 MAT0 PWM TRAP3 EXTBUS D8
TRAP3/D8
P4[12]/BLS0 64[1] GPIO 4, pin 12 EXTBUS BLS0 - -
P2[1]/MAT2[1]/ 65[1] GPIO 2, pin 1 TIMER2 MAT1 PWM TRAP2 EXTBUS D9
TRAP2/D9
P5[12]/D24 66[1] GPIO 5, pin 24 EXTBUS D24 - -
VDD(IO) 67 3.3 V power supply for I/O
P4[1]/A9 68[1] GPIO 4, pin 1 EXTBUS A9 - -

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
(default)

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P3[10]/SDI2/ 69[1] GPIO 3, pin 10 SPI2 SDI PWM1 MAT4 USB_PWRD1

R
A
PMAT1[4]/

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USB_PWRD1

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VSS(CORE) 70 ground for core
VDD(CORE) 71 1.8 V power supply for digital core
P5[1]/D9 72[1] GPIO 5, pin 1 EXTBUS D9 - -
P3[11]/SCK2/ 73[1] GPIO 3, pin 11 SPI2 SCK PWM1 MAT5 USB_LS1
PMAT1[5]/USB_LS1
P4[17]/CS7/U1OUT2 74[1] GPIO 4. pin 17 EXTBUS CS7 UART1 OUT2 -
P1[15]/CAP2[1]/ 75[1] GPIO 1, pin 15 TIMER2 CAP1 SPI0 SCS0 EXTBUS D1
SCS0[0]/D1
P4[9]/A23/DCD1 76[1] GPIO4, pin 9 EXTBUS A23 UART1 DCD -
VSS(IO) 77 ground for I/O
P5[9]/D21/DTR1 78[1] GPIO 5, pin 9 EXTBUS D21 USRT1 DTR -
P1[14]/CAP2[0]/SCS 79[1] GPIO 1, pin 14 TIMER2 CAP0 SPI0 SCS3 EXTBUS D0
0[3]/D0
P4[21]/ 80[1] GPIO 4, pin 21 USB_OVRCR2 - -
USB_OVRCR2
P1[13]/SCL1/ 81[1] GPIO 1, pin 13 EXTINT3 I2C1 SCL EXTBUS WE_N
EI3/WE_N
P4[5]/A13 82[1] GPIO 4, pin 5 EXTBUS A13 - -
P1[12]/SDA1/ 83[1] GPIO 1, pin 12 EXTINT2 I2C1 SDA EXTBUS OE_N
EI2/OE_N
P5[5]/D17 84[1] GPIO 5, pin 5 EXTBUS D17 - -
VDD(IO) 85 3.3 V power supply for I/O
P2[2]/MAT2[2]/ 86[1] GPIO 2, pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10
TRAP1/D10
P2[3]/MAT2[3]/ 87[1] GPIO 2, pin 3 TIMER2 MAT3 PWM TRAP0 EXTBUS D11
TRAP0/D11
P1[11]/SCK1/ 88[1] GPIO 1, pin 11 SPI1 SCK I2C0 SCL EXTBUS CS3
SCL0/CS3
P1[10]/SDI1/ 89[1] GPIO 1, pin 10 SPI1 SDI I2C0 SDA EXTBUS CS2
SDA0/CS2
P3[12]/SCS1[0]/EI4/ 90[1] GPIO 3, pin 12 SPI1 SCS0 EXTINT4 USB_SSPND1
USB_SSPND1
VSS(CORE) 91 ground for digital core
VDD(CORE) 92 1.8 V power supply for digital core
P3[13]/SDO1/ 93[1] GPIO 3, pin 13 SPI1 SDO EXTINT5 QEI0 IDX
EI5/IDX0
P2[4]/MAT1[0]/ 94[1] GPIO 2, pin 4 TIMER1 MAT0 EXTINT0 EXTBUS D12
EI0/D12
P2[5]/MAT1[1]/ 95[1] GPIO 2, pin 5 TIMER1 MAT1 EXTINT1 EXTBUS D13
EI1/D13

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
(default)

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P1[9]/SDO1/ 96[1] GPIO 1, pin 9 SPI1 SDO LIN1 RXD/UART RXD EXTBUS CS1

R
A
RXDL1/CS1

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VSS(IO) 97 ground for I/O

R
A
P1[8]/SCS1[0]/ 98[1] GPIO 1, pin 8 SPI1 SCS0 LIN1 TXD/ UART TXD EXTBUS CS0
TXDL1/CS0
P1[7]/SCS1[3]/RXD1/ 99[1] GPIO 1, pin 7 SPI1 SCS3 UART1 RXD EXTBUS A7
A7
P1[6]/SCS1[2]/ 100[1] GPIO 1, pin 6 SPI1 SCS2 UART1 TXD EXTBUS A6
TXD1/A6
P2[6]/MAT1[2]/ 101[1] GPIO 2, pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14
EI2/D14
P1[5]/SCS1[1]/ 102[1] GPIO 1, pin 5 SPI1 SCS1 PWM3 MAT5 EXTBUS A5
PMAT3[5]/A5
P1[4]/SCS2[2]/ 103[1] GPIO 1, pin 4 SPI2 SCS2 PWM3 MAT4 EXTBUS A4
PMAT3[4]/A4
TRST_N 104[1] IEEE 1149.1 test reset NOT; active LOW; pulled up internally
RST_N 105[1] asynchronous device reset; active LOW; pulled up internally
VSS(OSC) 106 ground for oscillator
XOUT_OSC 107[3] crystal out for oscillator
XIN_OSC 108[3] crystal in for oscillator
VDD(OSC_PLL) 109 1.8 V supply for oscillator and PLL
VSS(PLL) 110 ground for PLL
P2[7]/MAT1[3]/ 111[1] GPIO 2, pin 7 TIMER1 MAT3 EXTINT3 EXTBUS D15
EI3/D15
P3[14]/SDI1/ 112[1] GPIO 3, pin 14 SPI1 SDI EXTINT6 CAN0 TXD
EI6/TXDC0
P3[15]/SCK1/ 113[1] GPIO 3, pin 15 SPI1 SCK EXTINT7 CAN0 RXD
EI7/RXDC0
VDD(IO) 114 3.3 V power supply for I/O
P2[8]/CLK_OUT/ 115[1] GPIO 2, pin 8 CLK_OUT PWM0 MAT0 SPI0 SCS2
PMAT0[0]/SCS0[2]
P2[9]/ 116[1] GPIO 2, pin 9 USB_UP_LED1 PWM0 MAT1 SPI0 SCS1
USB_UP_LED1/
PMAT0[1]/SCS0[1]
P1[3]/SCS2[1]/ 117[1] GPIO 1, pin 3 SPI2 SCS1 PWM3 MAT3 EXTBUS A3
PMAT3[3]/A3
P1[2]/SCS2[3]/ 118[1] GPIO 1, pin 2 SPI2 SCS3 PWM3 MAT2 EXTBUS A2
PMAT3[2]/A2
P1[1]/EI1/PMAT3[1]/ 119[1] GPIO 1, pin 1 EXTINT1 PWM3 MAT1 EXTBUS A1
A1
VSS(CORE) 120 ground for digital core
VDD(CORE) 121 1.8 V power supply for digital core
P1[0]/EI0/ 122[1] GPIO 1, pin 0 EXTINT0 PWM3 MAT0 EXTBUS A0
PMAT3[0]/A0
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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Function 0 Function 1 Function 2 Function 3

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(default)

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P2[10]/USB_INT1/ 123[1] GPIO 2, pin 10 USB_INT1 PWM0 MAT2 SPI0 SCS0

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A
PMAT0[2]/SCS0[0]

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P2[11]/USB_RST1/ 124[1] GPIO 2, pin 11 USB_RST1 PWM0 MAT3 SPI0 SCK

R
A
PMAT0[3]/SCK0
P0[0]/PHB0/ 125[1] GPIO 0, pin 0 QEI0 PHB CAN0 TXD EXTBUS D24
TXDC0/D24
VSS(IO) 126 ground for I/O
P4[13]/BLS1 127[1] GPIO 4, pin 13 EXTBUS BLS1 - -
P0[1]/PHA0/ 128[1] GPIO 0, pin 1 QEI 0 PHA CAN0 RXD EXTBUS D25
RXDC0/D25
P5[13]/D25 129[1] GPIO 5, pin 13 EXTBUS D25 - -
P0[2]/CLK_OUT/ 130[1] GPIO 0, pin 2 CLK_OUT PWM0 MAT0 EXTBUS D26
PMAT0[0]/D26
P4[2]/A10 131[1] GPIO 4, pin 2 EXTBUS A10 - -
VDD(IO) 132 3.3 V power supply for I/O
P5[2]/D10 133[1] GPIO 5, pin 2 EXTBUS D10 - -
P0[3]/ 134[1] GPIO 0, pin 3 USB_UP_LED1 PWM0 MAT1 EXTBUS D27
USB_UP_LED1/
PMAT0[1]/D27
P4[18]/ 135[1] GPIO 4, pin 18 USB_UP_LED2 - -
USB_UP_LED2
P3[0]/IN0[6]/ 136[1] GPIO 3, pin 0 ADC0 IN6 PWM2 MAT0 EXTBUS CS6
PMAT2[0]/CS6
P4[10]/OE_N/CTS1 137[1] GPIO 4, pin 10 EXTBUS OE_N UART1 CTS -
P3[1]/IN0[7/ 138[1] GPIO 3, pin 1 ADC0 IN7 PWM2 MAT1 EXTBUS CS7
PMAT2[1]/CS7
P5[10]/D22/DSR1 139[1] GPIO 5, pin 10 EXTBUS D22 UART1 DSR -
P2[12]/IN0[4] 140[1] GPIO 2, pin 12 ADC0 IN4 PWM0 MAT4 SPI0 SDI
PMAT0[4]/SDI0
VDD(CORE) 141 1.8 V power supply for digital core
VSS(CORE) 142 ground for digital core
P4[22]/ 143[1] GPIO 4, pin 22 USB_PPWR2 - -
USB_PPWR2
VSS(IO) 144 ground for I/O
P2[13]/IN0[5]/ 145[1] GPIO 2, pin 13 ADC0 IN5 PWM0 MAT5 SPI0 SDO
PMAT0[5]/SDO0
P4[6]/A20/RI1 146[1] GPIO 4, pin 6 EXTBUS A20 UART1 RI1 -
P0[4]/IN0[0]/ 147[1] GPIO 0, pin 4 ADC0 IN0 PWM0 MAT2 EXTBUS D28
PMAT0[2]/D28
P5[6]/D18/RI0 148[1] GPIO 5, pin 6 EXTBUS D18 UART0 RI -
P4[14]/BLS2 149[1] GPIO 4, pin 14 BLS2 - -
P0[5]/IN0[1]/ 150[1] GPIO 0, pin 5 ADC0 IN1 PWM0 MAT3 EXTBUS D29
PMAT0[3]/D29

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
(default)

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P5[14]/ 151[1] GPIO 5, pin 14 USB_SSPND1 UART0 RS -

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A
USB_SSPND1/RTS0

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VDD(IO) 152 3.3 V power supply for I/O

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A
P0[6]/IN0[2]/ 153[1] GPIO 0, pin 6 ADC0 IN2 PWM0 MAT4 EXTBUS D30
PMAT0[4]/D30
P0[7]/IN0[3]/ 154[1] GPIO 0, pin 7 ADC0 IN3 PWM0 MAT5 EXTBUS D31
PMAT0[5]/D31
VDDA(ADC3V3) 155 3.3 V power supply for ADC
JTAGSEL 156[1] TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects
boundary scan and flash programming; pulled up internally.
VDDA(ADC5V0) 157 5 V supply voltage for ADC0 and 5 V reference for ADC0.
VREFP 158[3] HIGH reference for ADC
VREFN 159[3] LOW reference for ADC
P0[8]/IN1[0]/TXDL0/ 160[4] GPIO 0, pin 8 ADC1 IN0 LIN0 TXD/ UART TXD EXTBUS A20
A20
P0[9]/IN1[1]/ 161[4] GPIO 0, pin 9 ADC1 IN1 LIN0 RXD/ UART TXD EXTBUS A21
RXDL0/A21
P0[10]/IN1[2]/ 162[4] GPIO 0, pin 10 ADC1 IN2 PWM1 MAT0 EXTBUS A8
PMAT1[0]/A8
P0[11]/IN1[3]/ 163[4] GPIO 0, pin 11 ADC1 IN3 PWM1 MAT1 EXTBUS A9
PMAT1[1]/A9
P2[14]/SDA1/ 164[1] GPIO 2, pin 14 I2C1 SDA PWM0 CAP0 EXTBUS BLS0
PCAP0[0]/BLS0
P2[15]/SCL1/ 165[1] GPIO 2, pin 15 I2C1 SCL PWM0 CAP1 EXTBUS BLS1
PCAP0[1]/BLS1
P3[2]/MAT3[0]/ 166[1] GPIO 3, pin 2 TIMER3 MAT0 PWM2 MAT2 USB_SDA1
PMAT2[2]/
USB_SDA1
VDD(CORE) 167 1.8 V power supply for digital core
VSS(CORE) 168 ground for digital core
VSS(IO) 169 ground for I/O
P4[3]/A11 170[1] GPIO 4, pin 3 EXTBUS A11 - -
P3[3]/MAT3[1]/ 171[1] GPIO 3, pin 3 TIMER3 MAT1 PWM2 MAT3 USB_SCL1
PMAT2[3]/
USB_SCL1
P5[3]/D11 172[1] GPIO 5, pin 3 EXTBUS D11 - -
P0[12]/IN1[4]/ 173[4] GPIO 0, pin 12 ADC1 IN4 PWM1 MAT2 EXTBUS A10
PMAT1[2]/A10
P4[19]/ 174[1] GPIO 4, pin 19 USB_CONNECT2 - -
USB_CONNECT2
P0[13]/IN1[5]/ 175[4] GPIO 0, pin 13 ADC1 IN5 PWM1 MAT3 EXTBUS A11
PMAT1[3]/A11
VDD(IO) 176 3.3 V power supply for I/O
P4[11]/WE_N/CTS1 177[1] GPIO 4, pin 11 EXTBUS WE_N UART1 CTS -
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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
A
(default)

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P0[14]/IN1[6]/ 178[4] GPIO 0, pin 14 ADC1 IN6 PWM1 MAT4 EXTBUS A12

R
A
PMAT1[4]/A12

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P5[11]/D23/DCD0 179[1] GPIO 5, pin 11 EXTBUS D23 UART0 DCD -

R
A
P0[15]/IN1[7]/ 180[4] GPIO 0, pin 15 ADC1 IN7 PWM1 MAT5 EXTBUS A13
PMAT1[5]/A13
P4[23]/ 181[1] GPIO 4, pin 23 USB_PWRD2 - -
USB_PWRD2
P0[16]IN2[0]/ 182[4] GPIO 0, pin 16 ADC2 IN0 UART0 TXD EXTBUS A22
TXD0/A22
P4[7]/A21/DTR1 183[1] GPIO 4, pin 7 EXTBUS A21 UART1 DTR -
VSS(IO) 184 ground for I/O
P5[7]/D19/ 185[1] GPIO 5, pin 7 EXTBUS D19 UART0 OUT1 -
U0OUT1
P0[17]/IN2[1]/ 186[4] GPIO 0, pin 17 ADC2 IN1 UART0 RXD EXTBUS A23
RXD0/A23
P4[15]/BLS3 187[1] GPIO 4, pin 14 BLS3 - -
P5[15]/ 188[1] GPIO 4, pin 14 USB_UP_LED1 UART1 RTS -
USB_UP_LED1/
RTS1
VDD(CORE) 189 1.8 V power supply for digital core
VSS(CORE) 190 ground for digital core
P2[16]/TXD1/ 191[1] GPIO 2, pin 16 UART1 TXD PWM0 CAP2 EXTBUS BLS2
PCAP0[2]/BLS2
P2[17]/RXD1/ 192[1] GPIO 2, pin 17 UART1 RXD PWM1 CAP0 EXTBUS BLS3
PCAP1[0]/BLS3
VDD(IO) 193 3.3 V power supply for I/O
P0[18]/IN2[2]/ 194[4] GPIO 0, pin 18 ADC2 IN2 PWM2 MAT0 EXTBUS A14
PMAT2[0]/A14
P0[19]/IN2[3]/ 195[4] GPIO 0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15
PMAT2[1]/A15
P3[4]/MAT3[2]/ 196[1] GPIO 3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXD
PMAT2[4]/
TXDC1
P3[5]/MAT3[3]/ 197[1] GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXD
PMAT2[5]/
RXDC1
P2[18]/SCS2[1]/ 198[1] GPIO 2, pin 18 SPI2 SCS1 PWM1 CAP1 EXTBUS D16
PCAP1[1]/D16
P2[19]/SCS2[0]/ 199[1] GPIO 2, pin 19 SPI2 SCS0 PWM1 CAP2 EXTBUS D17
PCAP1[2]/D17
P0[20]/IN2[4]/ 200[4] GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16
PMAT2[2]/A16
P0[21]/IN2[5]/ 201[4] GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17
PMAT2[3]/A17

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Table 103. LPC2930/39 LQFP208 pin assignment …continued

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Pin name Pin Description

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Function 0 Function 1 Function 2 Function 3

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A
A
(default)

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P0[22]/IN2[6]/ 202[4] GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18

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A
PMAT2[4]/A18

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VSS(IO) 203 ground for I/O

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A
P0[23]/IN2[7]/ 204[4] GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19
PMAT2[5]/A19
P2[20]/ 205[1] GPIO 2, pin 20 SPI2 SDO PWM2 CAP0 EXTBUS D18
PCAP2[0]/D18
VDD(CORE) 206 1.8 V power supply for digital core
VSS(CORE) 207 ground for digital core
TDI 208[1] IEEE 1149.1 data in, pulled up internally

[1] Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up /
Pull Down / Repeater.
[2] USB pad, <tbd>.
[3] Analog Pad; Analog Input Output.
[4] Analog I/O pad, <tbd>.

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Chapter 12: LPC29xx external Static Memory Controller (SMC)

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Rev. 00.06 — 17 December 2008 User manual

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1. How to read this chapter

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The contents of this chapter apply to parts LPC2917/19/01, LPC2927/29, LPC2930, and

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LPC2939. The LPC2921/23/25 does not have an external static memory controller.

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2. SMC functional description
External memory can be connected to the device. The Static Memory Controller (SMC)
controls timing and configuration of this external memory.

Bank Select
CS n
CS1
ARM CS0

SMC Address (lowest part) External

External
Memory
External
Memory
Memory
Data (8/16/32 bit) Bank n
Bank 1
Bank 0

Fig 31. Schematic representation of the SMC

The SMC provides an interface between a system bus and external (off-chip) memory
devices. It provides support for up to eight independently configurable memory banks
simultaneously. Each memory bank is capable of supporting SRAM, ROM, Flash EPROM,
Burst ROM memory or external I/O devices (memory-mapped).

Each memory bank may be 8, 16, or 32 bits wide.

Table 104. Static-memory bank address range

Bank Address Range
0 0x4000 0000 0x43FF FFFF
1 0x4400 0000 0x47FF FFFF
2 0x4800 0000 0x4BFF FFFF
3 0x4C00 0000 0x4FFF FFFF
4 0x5000 0000 0x53FF FFFF
5 0x5400 0000 0x57FF FFFF
6 0x5800 0000 0x5BFF FFFF
7 0x5C00 0000 0x5FFF FFFF

Memory banks can be set to write-protect state. In this case the memory controller blocks
write access for the specified bank. When an illegal write occurs the WRITEPROTERR bit
in the SMBSR register is set.

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3. External memory interface

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The external memory interface depends on the bank width: 32, 16 or 8 bits selected via

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A

FT
MW bits in the corresponding SMBCR register. Choice of memory chips requires an

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adequate set-up of the RBLE bit in the same register. RBLE = 0 for 8-bit based external

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A
memories, while memory chips capable of accepting 16- or 32-bit wide data will work with

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RBLE = 1. If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can

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A
be used as non-address lines. Memory banks configured to 16 bits wide do not require
A0, while 8-bit wide memory banks require address lines down to A0.

Configuring A1 and/or A0 line(s) to provide address or non-address function is

accomplished by setting up the SCU. Symbol A[x] refers to the highest-order address line
of the memory chip used in the external-memory interface. CS refers to the eight bank-
select lines, and BLS refers to the four byte-lane select lines. WE_N is the write output
enable and OE_N is the output enable. Address pins on the device are shared with other
functions. When connecting external memories, check that the I/O pin is programmed to
the correct function. Control of these settings is handled by the SCU (see Section 6–2).

Figure 12–32 shows configuration of a 32-bit wide memory bank using 8-bit devices.
Figure 12–33 and Figure 12–34 show a 32-bit wide memory using 16- and 32-bit devices.
Figure 12–35 shows configuration of a 16-bit wide memory bank using 8-bit devices.
Figure 12–36 shows configuration of a 16-bit wide memory bank using 16-bit devices.
Figure 12–37 shows an 8-bit wide memory bank. This memory width requires 8-bit
devices.

CS0 .. CS n
OE_N

CE CE CE CE
OE OE OE OE
BLS3 BLS2 BLS1 BLS0
WE WE WE WE
D[31:24] D[23:16] D[15:8] D[7:0]
IO[7:0] IO[7:0] IO[7:0] IO[7:0]
A[x:0] A[x:0] A[x:0] A[x:0]

A[x+2:2]

32-bit bank using 8-bit devices

Fig 32. External memory interface: 32-bit banks with 8-bit devices

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CS0 .. CS n

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A
A
OE_N

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FT
WE_N

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D
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A
FT
CE CE

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OE OE

R
WE WE

A
BLS3 BLS1
UB UB
BLS2 BLS0
LB LB
D[31:16] D[15:0]
IO[15:0] IO[15:0]
A[x:0] A[x:0]

A[x+2:2]

32-bit bank using 16-bit devices

Fig 33. External memory interface: 32-bit banks with 16-bit devices

CS0 .. CS n
OE_N
WE_N

CE
OE
WE
BLS3
B3
BLS2
B2
BLS1
B1
BLS0
B0
D[31:0]
IO[31:0]
A[x:0]

A[x+2:2]

32-bit bank using 32-bit device

Fig 34. External memory interface: 32-bit banks with 32-bit devices

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CS0 .. CS n

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A
A
OE_N

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CE CE

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OE OE

A
BLS1 BLS0
WE WE

LB
D[15:8] D[7:0]
IO[7:0] IO[7:0]
A[x:0] A[x:0]

A[x+1:1]

16-bit bank using 8-bit devices

Fig 35. External memory interface: 16-bit banks with 8-bit devices

CS0 .. CS n
OE_N
WE_N

CE
OE
WE

BLS1
UB
BLS0
LB
D[15:0]
IO[15:0]
A[x:0]

A[x+1:1]

16-bit bank using 16-bit device

Fig 36. External memory interface: 16-bit banks with 16-bit devices

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CS0 .. CS n

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A
A
OE_N

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A
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CE

R
A
OE
BLS0
WE

D[7:0]
IO[7:0]
A[x:0]

A[x:0]

8-bit bank using 8-bit device

Fig 37. External memory interface: 8-bit banks with 8-bit devices

Memory is available in various speeds, so the numbers of wait-states for both read and
write access must be set up. These settings should be reconsidered when the ARM
processor-core clock changes.

In Figure 12–38 a timing diagram for reading external memory is shown. The relationship
between the wait-state settings is indicated with arrows.

CLK(SYS)

CS

OE_N

ADDR

DATA

WSTOEN

WST1

WSTOEN=3, WST1=7
Fig 38. Reading from external memory

In Figure 12–39 a timing diagram for writing external memory is shown. The relationship
between wait-state settings is indicated with arrows.
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CLK(SYS)

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CS

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A
WE_N / BLS

ADDR

DATA

WSTWEN

WST2

WSTWEN=3, WST2=7
Fig 39. Writing to external memory

In Figure 12–40 usage of the idle/turn-around time (IDCY) is demonstrated. Extra

wait-states are added between a read and a write cycle in the same external memory
device.

CLK(SYS)

CS

WE_N / BLS

OE_N

ADDR

DATA

WSTOEN WSTWEN

WST1 IDCY WST2

WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5

Fig 40. Reading/writing external memory

Address pins on the device are shared with other functions. When connecting external
memories, check that the I/O pin is programmed to the correct function. Control of these
settings is handled by the SCU.
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4. External SMC register overview

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The external SMC memory-bank configuration registers are shown in Table 12–105.

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The memory-bank configuration registers have an offset to the base address SMC

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RegBase which can be found in the memory map.

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Table 105. External SMC register overview (base address 6000 0000h)

A
Offset Access Width Reset Symbol Description Reference
Address value
Bank 0
000h R/W 4 Fh SMBIDCYR0 Idle-cycle control register for memory see
bank 0 Table 12–106
004h R/W 5 1Fh SMBWST1R0 Wait-state 1 control register for memory see
bank 0 Table 12–107
008h R/W 5 1Fh SMBWST2R0 Wait-state 2 control register for memory see
bank 0 Table 12–108
00Ch R/W 4 0h SMBWSTOENR0 Output-enable assertion delay control see
register for memory bank 0 Table 12–109
010h R/W 4 1h SMBWSTWENR0 Write-enable assertion delay control see
register for memory bank 0 Table 12–110
014h R/W 8 80h SMBCR0 Configuration register for memory bank 0 see
Table 12–111
018h R/W 2 0h SMBSR0 Status register for memory bank 0 see
Table 12–112
Bank 1
01Ch R/W 4 Fh SMBIDCYR1 Idle-cycle control register for memory see
bank 1 Table 12–106
020h R/W 5 1Fh SMBWST1R1 Wait-state 1 control register for memory see
bank 1 Table 12–107
024h R/W 5 1Fh SMBWST2R1 Wait-state 2 control register for memory see
bank 1 Table 12–108
028h R/W 4 0h SMBWSTOENR1 Output-enable assertion delay control see
register for memory bank 1 Table 12–109
02Ch R/W 4 1h SMBWSTWENR1 Write-enable assertion delay control see
register for memory bank 1 Table 12–110
030h R/W 8 00h SMBCR1 Configuration register for memory bank 1 see
Table 12–111
034h R/W 2 0h SMBSR1 Status register for memory bank 1 see
Table 12–112
Bank 2
038h R/W 4 Fh SMBIDCYR2 Idle-cycle control register for memory see
bank 2 Table 12–106
03Ch R/W 5 1Fh SMBWST1R2 Wait-state 1 control register for memory see
bank 2 Table 12–107
040h R/W 5 1Fh SMBWST2R2 Wait-state 2 control register for memory see
bank 2 Table 12–108
044h R/W 4 0h SMBWSTOENR2 Output-enable assertion delay control see
register for memory bank 2 Table 12–109

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Chapter 12: LPC29xx external Static Memory Controller (SMC)

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Table 105. External SMC register overview …continued(base address 6000 0000h)

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Offset Access Width Reset Symbol Description Reference

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F
Address value

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048h R/W 4 1h SMBWSTWENR2 Write-enable assertion delay control see

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register for memory bank 2 Table 12–110

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A
04Ch R/W 8 40h SMBCR2 Configuration register for memory bank 2 see

FT
Table 12–111

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A
050h R/W 2 0h SMBSR2 Status register for memory bank 2 see
Table 12–112
Bank 3
054h R/W 4h Fh SMBIDCYR3 Idle-cycle control register for memory see
bank 3 Table 12–106
058h R/W 5h 1Fh SMBWST1R3 Wait-state 1 control register for memory see
bank 3 Table 12–107
05Ch R/W 5h 1Fh SMBWST2R3 Wait-state 2 control register for memory see
bank 3 Table 12–108
060h R/W 4h 0h SMBWSTOENR3 Output-enable assertion delay control see
register for memory bank 3 Table 12–109
064h R/W 4h 1h SMBWSTWENR3 Write-enable assertion delay control see
register for memory bank 3 Table 12–110
068h R/W 8h 00h SMBCR3 Configuration register for memory bank 3 see
Table 12–111
06Ch R/W 2h 0h SMBSR3 Status register for memory bank 3 see
Table 12–112
Bank 4
070h R/W 4 Fh SMBIDCYR4 Idle-cycle control register for memory see
bank 4 Table 12–106
074h R/W 5 1Fh SMBWST1R4 Wait-state 1 control register for memory see
bank 4 Table 12–107
078h R/W 5 1Fh SMBWST2R4 Wait-state 2 control register for memory see
bank 4 Table 12–108
07Ch R/W 4 0h SMBWSTOENR4 Output-enable assertion delay control see
register for memory bank 4 Table 12–109
080h R/W 4 1h SMBWSTWENR4 Write-enable assertion delay control see
register for memory bank 4 Table 12–110
084h R/W 8 80h SMBCR4 Configuration register for memory bank 4 see
Table 12–111
088h R/W 2 0h SMBSR4 Status register for memory bank 4 see
Table 12–112
Bank 5
08Ch R/W 4 Fh SMBIDCYR5 Idle-cycle control register for memory see
bank 5 Table 12–106
090h R/W 5 1Fh SMBWST1R5 Wait-state 1 control register for memory see
bank 5 Table 12–107
094h R/W 5 1Fh SMBWST2R5 Wait-state 2 control register for memory see
bank 5 Table 12–108
098h R/W 4 0h SMBWSTOENR5 Output-enable assertion delay control see
register for memory bank 5 Table 12–109

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Table 105. External SMC register overview …continued(base address 6000 0000h)

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Offset Access Width Reset Symbol Description Reference

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Address value

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09Ch R/W 4 1h SMBWSTWENR5 Write-enable assertion delay control see

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register for memory bank 5 Table 12–110

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0A0h R/W 8 80h SMBCR5 Configuration register for memory bank 5 see

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Table 12–111

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0A4h R/W 2 0h SMBSR5 Status register for memory bank 5 see
Table 12–112
Bank 6
0A8h R/W 4 Fh SMBIDCYR6 Idle-cycle control register for memory see
bank 6 Table 12–106
0ACh R/W 5 1Fh SMBWST1R6 Wait-state 1 control register for memory see
bank 6 Table 12–107
0B0h R/W 5 1Fh SMBWST2R6 Wait-state 2 control register for memory see
bank 6 Table 12–108
0B4h R/W 4 0h SMBWSTOENR6 Output-enable assertion delay control see
register for memory bank 6 Table 12–109
0B8h R/W 4 1h SMBWSTWENR6 Write-enable assertion delay control see
register for memory bank 6 Table 12–110
0BCh R/W 8 40h SMBCR6 Configuration register for memory bank 6 see
Table 12–111
0C0h R/W 2 0h SMBSR6 Status register for memory bank 6 see
Table 12–112
Bank 7
0C4h R/W 4 Fh SMBIDCYR7 Idle-cycle control register for memory see
bank 7 Table 12–106
0C8h R/W 5 1Fh SMBWST1R7 Wait-state 1 control register for memory see
bank 7 Table 12–107
0CCh R/W 5 1Fh SMBWST2R7 Wait-state 2 control register for memory see
bank 7 Table 12–108
0D0h R/W 4 0h SMBWSTOENR7 Output enable assertion delay control see
register for memory bank 7 Table 12–109
0D4h R/W 4 1h SMBWSTWENR7 Write-enable assertion delay control see
register for memory bank 7 Table 12–110
0D8h R/W 8 00h SMBCR7 Configuration register for memory bank 7 see
Table 12–111
0DCh R/W 2 0h SMBSR7 Status register for memory bank 7 see
Table 12–112

4.1 Bank idle-cycle control registers

The bank idle-cycle control register configures the external bus turnaround cycles
between read and write memory accesses to avoid bus contention on the external-
memory data bus. The bus turnaround wait-time is inserted between external bus
transfers in the case of:

• Read-to-read, to different memory banks

• Read-to-write, to the same memory bank
• Read-to-write, to different memory banks
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Table 12–106 shows the bit assignment of the SMBIDCYR0 to SMBIDCYR7 registers.

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Table 106. SMBIDCYRn register bit description (SMBIDCYR0 to 7, addresses 0x6000 0000,

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0x6000 001C, 0x6000 0038, 0x6000 0054, 0x6000 0070, 0x6000 008C, 0x6000 00A8,

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0x6000 00C4)

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* = reset value

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Bit Symbol Access Value Description

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31 to 4 reserved R - Reserved; do not modify. Read as logic 0, write

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as logic 0
3 to 0 IDCY[3:0] R/W Idle or turnaround cycles. This register contains
the number of bus turnaround cycles added
between read and write accesses. The
turnaround time is the programmed number of
cycles multiplied by the system clock period
Fh*

4.2 Bank wait-state 1 control registers

The bank wait-state 1 control register configures the external transfer wait-states in read
accesses. The bank configuration register contains the enable and polarity setting for the
external wait.

The minimum wait-states value WST1 can be calculated from the following formula:
t a ( R )int + t emd ( read )
WST1 = ---------------------------------------------
-–1
t clk ( sys )
Where:

ta(R)int = internal read delay. For more information see Ref. 32–1 Dynamic characteristics.

temd(read) = external-memory read delay in ns.

Table 12–107 shows the bit assignment of the SMBWST1R0 to SMBWST1R7 registers.

Table 107. SMBWST1Rn register bit description (SMBWRST1R0 to SMBWRST1R7,

addresses 0x6000 0004, 0x6000 0020, 0x6000 003C, 0x6000 0058, 0x6000 0074,
0x6000 0090, 0x6000 00AC, 0x6000 00C8)
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
4 to 0 WST1[4:0] R/W Wait-state 1. This register contains the length of
read accesses, except for burst ROM where it
defines the length of the first read access only.
The read-access time is the programmed
number of wait-states multiplied by the system
clock period
1Fh*

4.3 Bank wait-state 2 control registers

The bank wait-state 2 control register configures the external transfer wait-states in write
accesses or in burst-read accesses. The bank configuration register contains the enable
and polarity settings for the external wait.

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Sequential-access burst-reads from burst-flash devices of the same type as for burst

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ROM are supported. Due to sharing of the SMBWST2R register between write and burst-

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read transfers it is only possible to have one setting at a time for burst flash; either write

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delay or the burst-read delay. This means that for write transfer the SMBWST2R register

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must be programmed with the write-delay value, and for a burst-read transfer it must be

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programmed with the burst-access delay.

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The minimum wait-states value WST2 can be calculated from the following formula:

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t a ( W )int + t emd ( write )
WST2 = -----------------------------------------------
-–1
t clk ( sys )
Where:

ta(W)int = internal write delay. For more information see Ref. 32–1 Dynamic characteristics.

temd(write) = external-memory write delay in ns.

Table 12–108 shows the bit assignment of the SMBWST2R0 to SMBWST2R7 registers.

Table 108. SMBWST2Rn register bit description (SMBWRST1R0 to SMBWRST1R7,

addresses 0x6000 0008, 0x6000 0024, 0x6000 0040, 0x6000 005C, 0x6000 0078,
0x6000 0094, 0x6000 00B0, 0x6000 00CC)
* = reset value
Bit Symbol Access Value Description
31 to 5 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
4 to 0 WST2[4:0] R/W Wait-state 2. This register contains the length of
write accesses, except for burst ROM where it
defines the length of the burst-read accesses.
The write-access time c.q. the burst ROM read
access time is the programmed number of wait-
states multiplied by the system clock period
1Fh*

4.4 Bank output enable assertion-delay control register

The bank output-enable assertion-delay 1 control register configures the delay between
the assertion of the chip-select and the output enable. This delay is used to reduce the
power consumption for memories that are unable to provide valid data immediately after
the chip-select is asserted. Since the access is timed by the wait-states, the programmed
value must be equal to or less than the bank wait-state 1 programmed value. The output
enable is always deasserted at the same time as the chip-select at the end of the transfer.
The bank configuration register contains the enable for output assertion delay.

Table 12–109 shows the bit assignment of the SMBWSTOENR0 to SMBWSTOENR7

registers.

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Table 109. SMBWSTOENRn register bit description (SMBWSTOENR0 to SMBWSTOENR7,

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addresses 0x6000 000C, 0x6000 0028, 0x6000 0044, 0x6000 0060, 0x6000 007C,

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0x6000 0098, 0x6000 00B4, 0x6000 00D0)

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* = reset value

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Bit Symbol Access Value Description

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31 to 4 reserved R - Reserved; do not modify. Read as logic 0, write

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as logic 0.

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3 to 0 WSTOEN R/W Output-enable assertion delay. This register
contains the length of the output-enable delay
after the chip-select assertion. The output-
enable assertion-delay time is the programmed
number of wait-states multiplied by the system
clock period
0h*

4.5 Bank write-enable assertion-delay control register

The bank write-enable assertion-delay 1 control register configures the delay between the
assertion of the chip-select and the write enable. This delay is used to reduce power
consumption for memories. Since the access is timed by the wait-states the programmed
value must be equal to or less than the bank wait-state 2 programmed value. The write
enable is asserted half a system-clock cycle after assertion of the chip-select for logic 0
wait-states. The write enable is deasserted half a system-clock cycle before the
chip-select, at the end of the transfer. The byte-lane select outputs have the same timing
as the write-enable output for writes to 8-bit devices that use the byte-lane selects instead
of the write enables. The bank configuration register contains the enable for output
assertion delay.

Table 12–110 shows the bit assignment of the SMBWSTWENR0 to SMBWSTWENR7

registers.

Table 110. SMBWSTWENRn register bit description (SMBWSTWENR0 toSMBWSTWENR7,

addresses 0x6000 0010, 0x6000 002C, 0x6000 0048, 0x6000 0064, 0x6000 0080,
0x6000 009C, 0x6000 00B8, 0x6000 00D4)
* = reset value
Bit Symbol Access Value Description
31 to 4 reserved R - Reserved; do not modify. Read as logic 0, write
as logic 0
3 to 0 WSTWEN R/W Write-enable assertion delay. This register
contains the length of the write enable delay
after the chip-select assertion. The write-enable
assertion-delay time is the programmed
number of wait-states multiplied by the system
clock period
1h*

4.6 Bank configuration register

The bank configuration register defines bank access for the connected memory device.

A data transfer can be initiated to the external memory greater than the width of the
external-memory data bus. In this case the external transfer is automatically split up into
several separate transfers.

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Table 12–111 shows the bit assignment of the SMBCR0 to SMBCR7 registers.

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Table 111. SMBCRn register bit description (SMBCR0 toSMBCR7, addresses 0x6000 0014,

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0x6000 0030, 0x6000 004C, 0x6000 0068, 0x6000 0084, 0x6000 00A0, 0x6000 00BC,

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0x6000 00D8)

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* = reset value

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Bit Symbol Access Value Description

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31 to 8 reserved R - Reserved; do not modify. Read as logic 0, write as

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logic 0
7 and 6 MW[1:0] R/W Memory-width configuration
00* 8-bit; reset value for memory banks 1, 3 and 7
01* 16-bit; reset value for memory banks 2 and 6
10* 32-bit; reset value for memory banks 0, 4 and 5
11 Reserved
5 BM R/W Burst mode
1 Sequential access burst-reads to a maximum of four
consecutive locations is supported to increase the
bandwidth by using reduced access time. However,
bursts crossing quad boundaries are split up so that
the first transfer after the boundary uses the slow
wait-state 1 read timing
0* The memory bank is configured for non-burst
memory
4 WP R/W Write-protect; e.g. (burst) ROM, read-only flash or
SRAM
1 The connected device is write-protected
0* No write-protection is required
3 CSPOL R/W Chip-select polarity
1 The chip-select input is active HIGH
0* The chip-select input is active LOW
2 and 1 reserved R - Reserved; do not modify. Read as logic 0, write as
logic 0
0 RBLE R/W Read-byte lane enable
1 The byte-lane select pins are held asserted (logic 0)
during a read access. This is for 16-bit or 32-bit
devices where the separate write-enable signal is
used and the byte-lane selects must be held
asserted during a read. The write-enable pin WEN is
used as the write-enable in this configuration.
0* The byte-lane select pins BLSn are all deasserted
(logic 1) during a read access. This is for 8-bit
devices if the byte-lane enable is connected to the
write-enable pin, so must be deasserted during a
read access (default at reset). The byte-lane select
pins are used as write-enables in this configuration

4.7 Bank status register

The bank status register reflects the status flags of each memory bank.

Table 12–112 shows the bit assignment of the SMBSR0 to SMBSR7 registers.
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Table 112. SMBSRn register bit description (SMBSR0 toSMBSR7, addresses 0x6000 0018,

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0x6000 0034, 0x6000 0050, 0x6000 006C, 0x6000 0088, 0x6000 00A4, 0x6000 00C0,

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0x6000 00DC)

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* = reset value

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Bit Symbol Access Value Description

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31 to 2 reserved R - Reserved; do not modify. Read as logic 0, write

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as logic 0

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1 WRITEPROTERR R/W Write-protect error
1 A write access to a write-protected memory
device was initiated. Writing logic 1 to this
register clears the write-protect status flag
0* Writing a logic 0 has no effect
0 reserved R - reserved; do not modify. Read as logic 0, write
as logic 0

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1. How to read this chapter

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The USB device controller is used in parts LPC2921/23/25, LPC2927/29, LPC2930, and

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LPC2939.

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2. Introduction
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.

The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame

(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 16 logical or 32 physical endpoints. There are four types of
transfers defined for the endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the
rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no
error correction.

For more information on the Universal Serial Bus, see the USB Implementers Forum
website.

The USB device controller on the LPC29xx enables full-speed (12 Mb/s) data exchange
with a USB host controller.

Table 113. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation Description
AHB Advanced High-performance bus
ATLE Auto Transfer Length Extraction
ATX Analog Transceiver
DD DMA Descriptor
DDP DMA Description Pointer
DMA Direct Memory Access
EOP End-Of-Packet
EP Endpoint
EP_RAM Endpoint RAM
FS Full Speed
LED Light Emitting Diode
LS Low Speed
MPS Maximum Packet Size
NAK Negative Acknowledge
PLL Phase Locked Loop

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Table 113. USB related acronyms, abbreviations, and definitions used in this chapter

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Acronym/abbreviation Description

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RAM Random Access Memory

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SOF Start-Of-Frame

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SIE Serial Interface Engine

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SRAM Synchronous RAM

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UDCA USB Device Communication Area
USB Universal Serial Bus

3. Features
• Fully compliant with the USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• Supports DMA transfers on all non-control endpoints.
• Allows dynamic switching between CPU controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.

4. Fixed endpoint configuration

Table 13–114 shows the supported endpoint configurations. Endpoints are realized and
configured at run time using the Endpoint realization registers, documented in Section
13–9.4 “Endpoint realization registers”.

Table 114. Fixed endpoint configuration

Logical Physical Endpoint type Direction Packet size (bytes) Double buffer
endpoint endpoint
0 0 Control Out 8, 16, 32, 64 No
0 1 Control In 8, 16, 32, 64 No
1 2 Interrupt Out 1 to 64 No
1 3 Interrupt In 1 to 64 No
2 4 Bulk Out 8, 16, 32, 64 Yes
2 5 Bulk In 8, 16, 32, 64 Yes
3 6 Isochronous Out 1 to 1023 Yes
3 7 Isochronous In 1 to 1023 Yes
4 8 Interrupt Out 1 to 64 No
4 9 Interrupt In 1 to 64 No
5 10 Bulk Out 8, 16, 32, 64 Yes
5 11 Bulk In 8, 16, 32, 64 Yes
6 12 Isochronous Out 1 to 1023 Yes
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Table 114. Fixed endpoint configuration

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Logical Physical Endpoint type Direction Packet size (bytes) Double buffer

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endpoint endpoint

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6 13 Isochronous In 1 to 1023 Yes

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7 14 Interrupt Out 1 to 64 No

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7 15 Interrupt In 1 to 64 No

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8 16 Bulk Out 8, 16, 32, 64 Yes

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8 17 Bulk In 8, 16, 32, 64 Yes
9 18 Isochronous Out 1 to 1023 Yes
9 19 Isochronous In 1 to 1023 Yes
10 20 Interrupt Out 1 to 64 No
10 21 Interrupt In 1 to 64 No
11 22 Bulk Out 8, 16, 32, 64 Yes
11 23 Bulk In 8, 16, 32, 64 Yes
12 24 Isochronous Out 1 to 1023 Yes
12 25 Isochronous In 1 to 1023 Yes
13 26 Interrupt Out 1 to 64 No
13 27 Interrupt In 1 to 64 No
14 28 Bulk Out 8, 16, 32, 64 Yes
14 29 Bulk In 8, 16, 32, 64 Yes
15 30 Bulk Out 8, 16, 32, 64 Yes
15 31 Bulk In 8, 16, 32, 64 Yes

5. Functional description
The architecture of the USB device controller is shown below in Figure 13–41.

BUS VBUS
MASTER DMA
USB_CONNECT
INTERFACE ENGINE
DMA interface
(AHB master)

USB_D+
AHB BUS

USB ATX

EP_RAM SERIAL
REGISTER
ACCESS INTERFACE
INTERFACE
CONTROL ENGINE
USB_D-

USB_UP_LED

register
interface EP_RAM
(AHB slave) USB DEVICE (4K)
BLOCK

Fig 41. USB device controller block diagram

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5.1 Analog transceiver

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The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX

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sends/receives the bi-directional D+ and D- signals of the USB bus.

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5.2 Serial Interface Engine (SIE)

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The SIE implements the full USB protocol layer. It is completely hardwired for speed and

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needs no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.

5.3 Endpoint RAM (EP_RAM)

Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for
this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the
EP_RAM. The total EP_RAM space required depends on the number of realized
endpoints, the maximum packet size of the endpoint, and whether the endpoint supports
double buffering.

5.4 EP_RAM access control

The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the
three sources that can access it: the CPU (via the Register Interface), the SIE, and the
DMA Engine.

5.5 DMA engine and bus master interface

When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB
bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all
endpoints. When transferring data, the DMA Engine functions as a master on the AHB
bus through the bus master interface.

5.6 Register interface

The Register Interface allows the CPU to control the operation of the USB Device
Controller. It also provides a way to write transmit data to the controller and read receive
data from the controller.

5.7 SoftConnect
The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH
through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow
software to finish its initialization sequence before deciding to establish connection to the
USB. Re-initialization of the USB bus connection can also be performed without having to
unplug the cable.

To use the SoftConnect feature, the CONNECT signal should control an external switch
that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the
CONNECT signal by writing to the CON bit using the SIE Set Device Status command.

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5.8 GoodLink

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Good USB connection indication is provided through GoodLink technology. When the

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device is successfully enumerated and configured, the LED indicator will be permanently

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ON. During suspend, the LED will be OFF.

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This feature provides a user-friendly indicator on the status of the USB device. It is a

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To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED
signal is controlled using the SIE Configure Device command.

6. Operational overview
Transactions on the USB bus transfer data between device endpoints and the host. The
direction of a transaction is defined with respect to the host. OUT transactions transfer
data from the host to the device. IN transactions transfer data from the device to the host.
All transactions are initiated by the host controller.

For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of the
USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and
converts it into a parallel data stream. The parallel data is written to the corresponding
endpoint buffer in the EP_RAM.

For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,
converts it into serial data, and transmits it onto the USB bus using the USB ATX.

Once data has been received or sent, the endpoint buffer can be read or written. How this
is accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.

In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface. See Section 13–13 “Slave mode operation” for a detailed description of
this mode.

In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 13–14 “DMA operation” for a detailed description of this mode.

7. Pin description
Table 115. USB external interface
Name Direction Description
VBUS I VBUS status input. When this function is not enabled
via its corresponding PINSEL register, it is driven
HIGH internally.
USB_CONNECT O SoftConnect control signal.
USB_UP_LED O GoodLink LED control signal.
USB_D+ I/O Positive differential data.
USB_D- I/O Negative differential data.

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This section describes the clocking and power management features of the USB Device

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Controller.

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8.1 Power requirements
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:

1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
3. A suspended device can draw a maximum of 500 μA.

8.2 Clocks
The USB device controller clocks are shown in Table 13–116

Table 116. USB device controller clock sources

Clock source Description
AHB master clock Clock for the AHB master bus interface and DMA
AHB slave clock Clock for the AHB slave interface
usbclk Dedicated 48 MHz clock from CGU1 (BASE_USB_CLK)

8.3 Power management support

To help conserve power, the USB device controller automatically disables the AHB master
clock and usbclk when not in use.

When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the
usbclk input to the device controller is automatically disabled, helping to conserve power.
However, if software wishes to access the device controller registers, usbclk must be
active. To allow access to the device controller registers while in the suspend state, the
USBClkCtrl and USBClkSt registers are provided.

When software wishes to access the device controller registers, it should first ensure
usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the
corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain
enabled until DEV_CLK_EN is cleared by software.

When a DMA transfer occurs, the device controller automatically turns on the AHB master
clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure
that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the
last DMA access, the AHB master clock is automatically disabled to help conserve power.
If desired, software also has the capability of forcing this clock to remain enabled using the
USBClkCtrl register.

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set. When the device controller is not in use, all of the device controller clocks may be

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disabled by clearing PCUSB.

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The USB_NEED_CLK signal is used to facilitate going into and waking up from chip

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Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt

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register are asserted.

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After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the
DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.
When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put
into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK
can be read from the USBIntSt register.

Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be
asserted. When the USB is configured to be a wakeup source from Power-down
(USBWAKE bit set in the INTWAKE register), the assertion of USB_NEED_CLK causes
the chip to wake up from Power-down mode.

8.4 Remote wake-up

The USB device controller supports software initiated remote wake-up. Remote wake-up
involves resume signaling on the USB bus initiated from the device. This is done by
clearing the SUS bit in the SIE Set Device Status register. Before writing into the register,
all the clocks to the device controller have to be enabled using the USBClkCtrl register.

9. Register description
Table 13–117 shows the USB Device Controller registers directly accessible by the CPU.
The Serial Interface Engine (SIE) has other registers that are indirectly accessible via the
SIE command registers. See Section 13–11 “Serial interface engine command
description” for more info.

Table 117. USB device register map

Name Description Access Reset value[1] Address
Clock control registers
USBClkCtrl USB Clock Control R/W 0x0000 0000 0xE010 CFF4
USBClkSt USB Clock Status RO 0x0000 0000 0xE010 CFF8
Device interrupt registers
USBIntSt USB Interrupt Status R/W 0x8000 0000 <tbd>
USBDevIntSt USB Device Interrupt Status RO 0x0000 0010 0xE010 C200
USBDevIntEn USB Device Interrupt Enable R/W 0x0000 0000 0xE010 C204
USBDevIntClr USB Device Interrupt Clear WO 0x0000 0000 0xE010 C208
USBDevIntSet USB Device Interrupt Set WO 0x0000 0000 0xE010 C20C
USBDevIntPri USB Device Interrupt Priority WO 0x00 0xE010 C22C
Endpoint interrupt registers
USBEpIntSt USB Endpoint Interrupt Status RO 0x0000 0000 0xE010 C230
USBEpIntEn USB Endpoint Interrupt Enable R/W 0x0000 0000 0xE010 C234
USBEpIntClr USB Endpoint Interrupt Clear WO 0x0000 0000 0xE010 C238

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Table 117. USB device register map

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Name Description Access Reset value[1] Address

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USBEpIntSet USB Endpoint Interrupt Set WO 0x0000 0000 0xE010 C23C

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USBEpIntPri USB Endpoint Priority WO[2] 0x0000 0000 0xE010 C240

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Endpoint realization registers

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USBReEp USB Realize Endpoint R/W 0x0000 0003 0xE010 C244

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USBEpInd USB Endpoint Index WO[2] 0x0000 0000 0xE010 C248
USBMaxPSize USB MaxPacketSize R/W 0x0000 0008 0xE010 C24C
USB transfer registers
USBRxData USB Receive Data RO 0x0000 0000 0xE010 C218
USBRxPLen USB Receive Packet Length RO 0x0000 0000 0xE010 C220
USBTxData USB Transmit Data WO[2] 0x0000 0000 0xE010 C21C
USBTxPLen USB Transmit Packet Length WO[2] 0x0000 0000 0xE010 C224
USBCtrl USB Control R/W 0x0000 0000 0xE010 C228
SIE Command registers
USBCmdCode USB Command Code WO[2] 0x0000 0000 0xE010 C210
USBCmdData USB Command Data RO 0x0000 0000 0xE010 C214
DMA registers
USBDMARSt USB DMA Request Status RO 0x0000 0000 0xE010 C250
USBDMARClr USB DMA Request Clear WO[2] 0x0000 0000 0xE010 C254
USBDMARSet USB DMA Request Set WO[2] 0x0000 0000 0xE010 C258
USBUDCAH USB UDCA Head R/W 0x0000 0000 0xE010 C280
USBEpDMASt USB Endpoint DMA Status RO 0x0000 0000 0xE010 C284
USBEpDMAEn USB Endpoint DMA Enable WO[2] 0x0000 0000 0xE010 C288
USBEpDMADis USB Endpoint DMA Disable WO[2] 0x0000 0000 0xE010 C28C
USBDMAIntSt USB DMA Interrupt Status RO 0x0000 0000 0xE010 C290
USBDMAIntEn USB DMA Interrupt Enable R/W 0x0000 0000 0xE010 C294
USBEoTIntSt USB End of Transfer Interrupt Status RO 0x0000 0000 0xE010 C2A0
USBEoTIntClr USB End of Transfer Interrupt Clear WO[2] 0x0000 0000 0xE010 C2A4
USBEoTIntSet USB End of Transfer Interrupt Set WO[2] 0x0000 0000 0xE010 C2A8
USBNDDRIntSt USB New DD Request Interrupt Status RO 0x0000 0000 0xE010 C2AC
USBNDDRIntClr USB New DD Request Interrupt Clear WO[2] 0x0000 0000 0xE010 C2B0
USBNDDRIntSet USB New DD Request Interrupt Set WO[2] 0x0000 0000 0xE010 C2B4
USBSysErrIntSt USB System Error Interrupt Status RO 0x0000 0000 0xE010 C2B8
USBSysErrIntClr USB System Error Interrupt Clear WO[2] 0x0000 0000 0xE010 C2BC
USBSysErrIntSet USB System Error Interrupt Set WO[2] 0x0000 0000 0xE010 C2C0

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
[2] Reading WO register will return an invalid value.

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9.1 Clock control registers

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9.1.1 USB Clock Control register (USBClkCtrl - 0xE010 CFF4)

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This register controls the clocking of the USB Device Controller. Whenever software

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must be set. The PORTSEL_CLK_EN bit need only be set when accessing the

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USBPortSel register.

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The software does not have to repeat this exercise for every register access, provided that
the corresponding USBClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. USBClkCtrl is a
read/write register.

Table 118. USBClkCtrl register (USBClkCtrl - address 0xE010 CFF4) bit description
Bit Symbol Description Reset
value
0 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.
1 DEV_CLK_EN Device clock enable. Enables the usbclk input to the 0
device controller
2 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.
3 PORTSEL_CLK_EN Port select register clock enable. NA
4 AHB_CLK_EN AHB clock enable 0
31:5 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.

9.1.2 USB Clock Status register (USBClkSt - 0xE010 CFF8)

This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with
the register access. Software does not have to repeat this exercise for every access,
provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read only register.

Table 119. USB Clock Status register (USBClkSt - 0xE010 CFF8) bit description
Bit Symbol Description Reset
value
0 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.
1 DEV_CLK_ON Device clock on. The usbclk input to the device 0
controller is active.
2 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.

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Bit Symbol Description Reset

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value

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3 PORTSEL_CLK_ON Port select register clock on. NA

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4 AHB_CLK_ON AHB clock on. 0

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31:5 - Reserved, user software should not write ones to NA

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reserved bits. The value read from a reserved bit is

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not defined.

9.2 Device interrupt registers

9.2.1 USB Interrupt Status register (USBIntSt - 0xE01F C1C0)

The USB Device Controller has three interrupt lines. This register allows software to
determine their status with a single read operation. All three interrupt lines are ORed
together to a single channel of the vectored interrupt controller. This register also contains
the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write
register.

Table 120. USB Interrupt Status register (USBIntSt - address <tbd>) bit description
Bit Symbol Description Reset
value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read only. 0
7:3 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a 1
change of state on the USB data pins is detected, and it indicates that a
PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK
becomes one, it it resets to zero 5 ms after the last packet has been
received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt
has occurred. A change of this bit from 0 to 1 can wake up the
microcontroller if activity on the USB bus is selected to wake up the part
from the Power-down mode This bit is read only.
30:9 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the Vectored 1
Interrupt Controller does not see the ORed output of the USB interrupt
lines.

9.2.2 USB Device Interrupt Status register (USBDevIntSt - 0xE010 C200)

The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and
1 indicates the presence of the interrupt. USBDevIntSt is a read only register.

Table 121. USB Device Interrupt Status register (USBDevIntSt - address 0xE010 C200) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -

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Bit 23 22 21 20 19 18 17 16

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Symbol - - - - - - - -

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Bit 15 14 13 12 11 10 9 8

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Symbol - - - - - - ERR_INT EP_RLZED

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Bit 7 6 5 4 3 2 1 0

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Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME

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ENDPKT

Table 122. USB Device Interrupt Status register (USBDevIntSt - address 0xE010 C200) bit description
Bit Symbol Description Reset value
0 FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0
1 EP_FAST Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is 0
set, the corresponding endpoint interrupt will be routed to this bit.
2 EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is 0
not set, the corresponding endpoint interrupt will be routed to this bit.
3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs. 0
Refer to Section 13–11.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on
page 187.
4 CCEMPTY The command code register (USBCmdCode) is empty (New command can be written). 1
5 CDFULL Command data register (USBCmdData) is full (Data can be read now). 0
6 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0
7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of 0
bytes programmed in the TxPacket length register (USBTxPLen).
8 EP_RLZED Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0
register (USBMaxPSize) is updated and the corresponding operation is completed.
9 ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13–11.9 0
“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 189
31:10 - Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

9.2.3 USB Device Interrupt Enable register (USBDevIntEn - 0xE010 C204)

Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an interrupt on one of the interrupt lines when set. By default, the interrupt is
routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME
interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of
USBDevIntPri. USBDevIntEn is a read/write register.

Table 123. USB Device Interrupt Enable register (USBDevIntEn - address 0xE010 C204) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED

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Bit 7 6 5 4 3 2 1 0

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Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME

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ENDPKT

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Table 124. USB Device Interrupt Enable register (USBDevIntEn - address 0xE010 C204) bit description

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Bit Symbol Value Description Reset value

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31:0 See 0 No interrupt is generated. 0

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USBDevIntEn 1 An interrupt will be generated when the corresponding bit in the Device
bit allocation Interrupt Status (USBDevIntSt) register (Table 13–121) is set. By default,
table above the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally,
either the EP_FAST or FRAME interrupt may be routed to the
USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.

9.2.4 USB Device Interrupt Clear register (USBDevIntClr - 0xE010 C208)

Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect.

Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.

USBDevIntClr is a write only register.

Table 125. USB Device Interrupt Clear register (USBDevIntClr - address 0xE010 C208) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol - - - - - - - -
Bit 23 22 21 20 19 18 17 16
Symbol - - - - - - - -
Bit 15 14 13 12 11 10 9 8
Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT

Table 126. USB Device Interrupt Clear register (USBDevIntClr - address 0xE010 C208) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No effect. 0
USBDevIntClr 1 The corresponding bit in USBDevIntSt (Section 13–9.2.2) is cleared.
bit allocation
table above

9.2.5 USB Device Interrupt Set register (USBDevIntSet - 0xE010 C20C)

Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a
zero has no effect

USBDevIntSet is a write only register.

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Table 127. USB Device Interrupt Set register (USBDevIntSet - address 0xE010 C20C) bit allocation

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Reset value: 0x0000 0000

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Bit 31 30 29 28 27 26 25 24

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Symbol - - - - - - - -

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Bit 23 22 21 20 19 18 17 16

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Symbol - - - - - - - -

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Bit 15 14 13 12 11 10 9 8

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Symbol - - - - - - ERR_INT EP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol TxENDPKT Rx CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
ENDPKT

Table 128. USB Device Interrupt Set register (USBDevIntSet - address 0xE010 C20C) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No effect. 0
USBDevIntSet 1 The corresponding bit in USBDevIntSt (Section 13–9.2.2) is set.
bit allocation
table above

9.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0xE010 C22C)

Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no
interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write only register.

Table 129. USB Device Interrupt Priority register (USBDevIntPri - address 0xE010 C22C) bit description
Bit Symbol Value Description Reset value
0 FRAME 0 FRAME interrupt is routed to USB_INT_REQ_LP. 0
1 FRAME interrupt is routed to USB_INT_REQ_HP.
1 EP_FAST 0 EP_FAST interrupt is routed to USB_INT_REQ_LP. 0
1 EP_FAST interrupt is routed to USB_INT_REQ_HP.
7:2 - - Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.

9.3 Endpoint interrupt registers

The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are
used in Slave mode operation.

9.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0xE010 C230)

Each physical non-isochronous endpoint is represented by a bit in this register to indicate
that it has generated an interrupt. All non-isochronous OUT endpoints generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section
13–11.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 186). A bit set to one in

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this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set

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depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a read

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only register.

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Note that for Isochronous endpoints, handling of packet data is done when the FRAME

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interrupt occurs.

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Table 130. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE010 C230) bit allocation

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Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

Table 131. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE010 C230) bit description
Bit Symbol Description Reset value
0 EP0RX Endpoint 0, Data Received Interrupt bit. 0
1 EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. 0
2 EP1RX Endpoint 1, Data Received Interrupt bit. 0
3 EP1TX Endpoint 1, Data Transmitted Interrupt bit or sent a NAK. 0
4 EP2RX Endpoint 2, Data Received Interrupt bit. 0
5 EP2TX Endpoint 2, Data Transmitted Interrupt bit or sent a NAK. 0
6 EP3RX Endpoint 3, Isochronous endpoint. NA
7 EP3TX Endpoint 3, Isochronous endpoint. NA
8 EP4RX Endpoint 4, Data Received Interrupt bit. 0
9 EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK. 0
10 EP5RX Endpoint 5, Data Received Interrupt bit. 0
11 EP5TX Endpoint 5, Data Transmitted Interrupt bit or sent a NAK. 0
12 EP6RX Endpoint 6, Isochronous endpoint. NA
13 EP6TX Endpoint 6, Isochronous endpoint. NA
14 EP7RX Endpoint 7, Data Received Interrupt bit. 0
15 EP7TX Endpoint 7, Data Transmitted Interrupt bit or sent a NAK. 0
16 EP8RX Endpoint 8, Data Received Interrupt bit. 0
17 EP8TX Endpoint 8, Data Transmitted Interrupt bit or sent a NAK. 0
18 EP9RX Endpoint 9, Isochronous endpoint. NA
19 EP9TX Endpoint 9, Isochronous endpoint. NA
20 EP10RX Endpoint 10, Data Received Interrupt bit. 0
21 EP10TX Endpoint 10, Data Transmitted Interrupt bit or sent a NAK. 0
22 EP11RX Endpoint 11, Data Received Interrupt bit. 0
23 EP11TX Endpoint 11, Data Transmitted Interrupt bit or sent a NAK. 0
24 EP12RX Endpoint 12, Isochronous endpoint. NA

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Table 131. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE010 C230) bit description

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Bit Symbol Description Reset value

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25 EP12TX Endpoint 12, Isochronous endpoint. NA

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26 EP13RX Endpoint 13, Data Received Interrupt bit. 0

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27 EP13TX Endpoint 13, Data Transmitted Interrupt bit or sent a NAK. 0

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28 EP14RX Endpoint 14, Data Received Interrupt bit. 0

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29 EP14TX Endpoint 14, Data Transmitted Interrupt bit or sent a NAK. 0
30 EP15RX Endpoint 15, Data Received Interrupt bit. 0
31 EP15TX Endpoint 15, Data Transmitted Interrupt bit or sent a NAK. 0

9.3.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xE010 C234)

Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the
corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated
endpoint. USBEpIntEn is a read/write register.

Table 132. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xE010 C234) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

Table 133. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xE010 C234) bit description
Bit Symbol Value Description Reset value
31:0 See 0 The corresponding bit in USBDMARSt is set when an interrupt occurs for 0
USBEpIntEn this endpoint.
bit allocation 1 The corresponding bit in USBEpIntSt is set when an interrupt occurs
table above for this endpoint. Implies Slave mode for this endpoint.

9.3.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xE010 C238)

Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt
command to be executed (Table 13–177) for the corresponding physical endpoint. Writing
zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the
CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the
CDFULL bit is set, USBCmdData contains the status of the endpoint, and the
corresponding bit in USBEpIntSt is cleared.

Notes:

• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.

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• While setting multiple bits in USBEpIntClr simultaneously is possible, it is not

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recommended; only the status of the endpoint corresponding to the least significant

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interrupt bit cleared will be available at the end of the operation.

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• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly

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invoked using the SIE command registers, but using USBEpIntClr is recommended

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because of its ease of use.

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Each physical endpoint has its own reserved bit in this register. The bit field definition is

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the same as that of USBEpIntSt shown in Table 13–130 . USBEpIntClr is a write only
register.

Table 134. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xE010 C238) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

Table 135. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xE010 C238) bit description
Bit Symbol Value Description Reset value
31:0 See 0 No effect. 0
USBEpIntClr 1 Clears the corresponding bit in USBEpIntSt, by executing the SIE Select
bit allocation Endpoint/Clear Interrupt command for this endpoint.
table above

9.3.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0xE010 C23C)

Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero
has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write only
register.

Table 136. USB Endpoint Interrupt Set register (USBEpIntSet - address 0xE010 C23C) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX EP14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

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Table 137. USB Endpoint Interrupt Set register (USBEpIntSet - address 0xE010 C23C) bit description

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Bit Symbol Value Description Reset value

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31:0 See 0 No effect. 0

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USBEpIntSet 1 Sets the corresponding bit in USBEpIntSt.

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bit allocation

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table above

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9.3.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xE010 C240)

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This register determines whether an endpoint interrupt is routed to the EP_FAST or
EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed
to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST
or EP_SLOW is possible.

Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed
to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line.

USBEpIntPri is a write only register.

Table 138. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xE010 C240) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol EP15TX EP15RX EP14TX E14RX EP13TX EP13RX EP12TX EP12RX
Bit 23 22 21 20 19 18 17 16
Symbol EP11TX EP11RX EP10TX EP10RX EP9TX EP9RX EP8TX EP8RX
Bit 15 14 13 12 11 10 9 8
Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX
Bit 7 6 5 4 3 2 1 0
Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX

Table 139. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xE010 C240) bit description
Bit Symbol Value Description Reset value
31:0 See 0 The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 0
USBEpIntPri 1 The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
bit allocation
table above

9.4 Endpoint realization registers

The registers in this group allow realization and configuration of endpoints at run time.

9.4.1 EP RAM requirements

The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM
dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has
space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends
on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by
the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the
MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next
word boundary. Also, each buffer has one word header showing the size of the packet
length received.

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The EP_ RAM space (in words) required for the physical endpoint can be expressed as

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EPRAMspace = ⎛ -------------------------------------------------- + 1⎞ × dbstatus
MaxPacketSize + 3

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⎝ ⎠

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where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.

Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is

TotalEPRAMspace = 32 + ∑ EPRAMspace ( n )
n=0

where N is the number of realized endpoints. Total EP_RAM space should not exceed
2048 bytes.

9.4.2 USB Realize Endpoint register (USBReEp - 0xE010 C244)

Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.

Table 140. USB Realize Endpoint register (USBReEp - address 0xE010 C244) bit allocation
Reset value: 0x0000 0003
Bit 31 30 29 28 27 26 25 24
Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24
Bit 23 22 21 20 19 18 17 16
Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16
Bit 15 14 13 12 11 10 9 8
Symbol EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Bit 7 6 5 4 3 2 1 0
Symbol EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0

Table 141. USB Realize Endpoint register (USBReEp - address 0xE010 C244) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint EP0 is not realized. 1
1 Control endpoint EP0 is realized.
1 EP1 0 Control endpoint EP1 is not realized. 1
1 Control endpoint EP1 is realized.
31:2 EPxx 0 Endpoint EPxx is not realized. 0
1 Endpoint EPxx is realized.

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On reset, only the control endpoints are realized. Other endpoints, if required, are realized

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by programming the corresponding bits in USBReEp. To calculate the required EP_RAM

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space for the realized endpoints, see Section 13–9.4.1.

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Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is

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shown below.

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Clear EP_RLZED bit in USBDevIntSt;

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for every endpoint to be realized,
{
/* OR with the existing value of the Realize Endpoint register */
USBReEp |= (UInt32) ((0x1 << endpt));
/* Load Endpoint index Reg with physical endpoint no.*/
USBEpIn = (UInt32) endpointnumber;

/* load the max packet size Register */

USBEpMaxPSize = MPS;

/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
/* wait until endpoint realization is complete */
}
/* Clear the EP_RLZED bit */
Clear EP_RLZED bit in USBDevIntSt;
}

The device will not respond to any transactions to unrealized endpoints. The SIE
Configure Device command will only cause realized and enabled endpoints to respond to
transactions. For details see Table 13–172.

9.4.3 USB Endpoint Index register (USBEpIn - 0xE010 C248)

Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is
in fact a register array. Hence before writing, this register is addressed through the
USBEpIn register.

The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize
will set the array element pointed to by USBEpIn. USBEpIn is a write only register.

Table 142. USB Endpoint Index register (USBEpIn - address 0xE010 C248) bit description
Bit Symbol Description Reset value
4:0 PHY_EP Physical endpoint number (0-31) 0
31:5 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

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9.4.4 USB MaxPacketSize register (USBMaxPSize - 0xE010 C24C)

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On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other

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endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer

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addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At the

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end, the EP_RLZED bit will be set in USBDevIntSt (Table 13–121). USBMaxPSize array

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indexing is shown in Figure 13–42. USBMaxPSize is a read/write register.

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Table 143. USB MaxPacketSize register (USBMaxPSize - address 0xE010 C24C) bit
description
Bit Symbol Description Reset value
9:0 MPS The maximum packet size value. 0x008[1]
31:10 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

[1] Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.

MPS_EP0
ENDPOINT INDEX

MPS_EP31

The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the
USBMaxPSize register.
Fig 42. USB MaxPacketSize register array indexing

9.5 USB transfer registers

The registers in this group are used for transferring data between endpoint buffers and
RAM in Slave mode operation. See Section 13–13 “Slave mode operation”.

9.5.1 USB Receive Data register (USBRxData - 0xE010 C218)

For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before
reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register
should be set appropriately. On reading this register, data from the selected endpoint
buffer is fetched. The data is in little endian format: the first byte received from the USB
bus will be available in the least significant byte of USBRxData. USBRxData is a read only
register.

Table 144. USB Receive Data register (USBRxData - address 0xE010 C218) bit description
Bit Symbol Description Reset value
31:0 RX_DATA Data received. 0x0000 0000

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9.5.2 USB Receive Packet Length register (USBRxPLen - 0xE010 C220)

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This register contains the number of bytes remaining in the endpoint buffer for the current

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packet being read via the USBRxData register, and a bit indicating whether the packet is

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valid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the

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USBCtrl register should be set appropriately. This register is updated on each read of the

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USBRxData register. USBRxPLen is a read only register.

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Table 145. USB Receive Packet Length register (USBRxPlen - address 0xE010 C220) bit
description
Bit Symbol Value Description Reset
value
9:0 PKT_LNGTH - The remaining number of bytes to be read from the 0
currently selected endpoint’s buffer. When this field
decrements to 0, the RxENDPKT bit will be set in
USBDevIntSt.
10 DV Data valid. This bit is useful for isochronous endpoints. 0
Non-isochronous endpoints do not raise an interrupt when
an erroneous data packet is received. But invalid data
packet can be produced with a bus reset. For isochronous
endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the
packet.
0 Data is invalid.
1 Data is valid.
11 PKT_RDY - The PKT_LNGTH field is valid and the packet is ready for 0
reading.
31:12 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

9.5.3 USB Transmit Data register (USBTxData - 0xE010 C21C)

For an IN transaction, the CPU writes the endpoint data into this register. Before writing to
this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be
set appropriately, and the packet length should be written to the USBTxPlen register. On
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write only register.

Table 146. USB Transmit Data register (USBTxData - address 0xE010 C21C) bit description
Bit Symbol Description Reset value
31:0 TX_DATA Transmit Data. 0x0000 0000

9.5.4 USB Transmit Packet Length register (USBTxPLen - 0xE010 C224)

This register contains the number of bytes transferred from the CPU to the selected
endpoint buffer. Before writing data to USBTxData, software should first write the packet
length (≤ MaxPacketSize) to this register. After each write to USBTxData, hardware
decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl
register should be set to select the desired endpoint buffer before starting this process.

For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in
packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For
example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of
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length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes

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in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write only

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register.

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Table 147. USB Transmit Packet Length register (USBTxPLen - address 0xE010 C224) bit

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description

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Bit Symbol Value Description Reset

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value

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9:0 PKT_LNGTH - The remaining number of bytes to be written to the 0x000
selected endpoint buffer. This field is decremented by 4 by
hardware after each write to USBTxData. When this field
decrements to 0, the TxENDPKT bit will be set in
USBDevIntSt.
31:10 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

9.5.5 USB Control register (USBCtrl - 0xE010 C228)

This register controls the data transfer operation of the USB device. It selects the endpoint
buffer that is accessed by the USBRxData and USBTxData registers, and enables
reading and writing them. USBCtrl is a read/write register.

Table 148. USB Control register (USBCtrl - address 0xE010 C228) bit description
Bit Symbol Value Description Reset
value
0 RD_EN Read mode control. Enables reading data from the OUT 0
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBRxData register.
This bit is cleared by hardware when the last word of
the current packet is read from USBRxData.
0 Read mode is disabled.
1 Read mode is enabled.
1 WR_EN Write mode control. Enables writing data to the IN 0
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBTxData register.
This bit is cleared by hardware when the number of
bytes in USBTxLen have been sent.
0 Write mode is disabled.
1 Write mode is enabled.
5:2 LOG_ENDPOINT - Logical Endpoint number. 0x0
31:6 - - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.

9.6 SIE command code registers

The SIE command code registers are used for communicating with the Serial Interface
Engine. See Section 13–11 “Serial interface engine command description” for more
information.

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9.6.1 USB Command Code register (USBCmdCode - 0xE010 C210)

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This register is used for sending the command and write data to the SIE. The commands

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written here are propagated to the SIE and executed there. After executing the command,

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the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See

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Section 13–11 for details. USBCmdCode is a write only register.

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Table 149. USB Command Code register (USBCmdCode - address 0xE010 C210) bit description

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Bit Symbol Value Description Reset value
7:0 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
15:8 CMD_PHASE The command phase: 0x00

0x01 Read
0x02 Write
0x05 Command
23:16 CMD_CODE/ This is a multi-purpose field. When CMD_PHASE is 0x00
CMD_WDATA Command or Read, this field contains the code for the
command (CMD_CODE). When CMD_PHASE is Write,
this field contains the command write data (CMD_WDATA).
31:24 - - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

9.6.2 USB Command Data register (USBCmdData - 0xE010 C214)

This register contains the data retrieved after executing a SIE command. When the data is
ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 13–121
for details. USBCmdData is a read only register.

Table 150. USB Command Data register (USBCmdData - address 0xE010 C214) bit
description
Bit Symbol Description Reset value
7:0 CMD_RDATA Command Read Data. 0x00
31:8 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

9.7 DMA registers

The registers in this group are used for the DMA mode of operation (see Section 13–14
“DMA operation”)

9.7.1 USB DMA Request Status register (USBDMARSt - 0xE010 C250)

A bit in this register associated with a non-isochronous endpoint is set by hardware when
an endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding
bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when the
corresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves as a
flag for the DMA engine to start the data transfer if the DMA is enabled for the
corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for
control endpoints (EP0 and EP1). USBDMARSt is a read only register.

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Table 151. USB DMA Request Status register (USBDMARSt - address 0xE010 C250) bit allocation

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Reset value: 0x0000 0000

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Bit 31 30 29 28 27 26 25 24

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Symbol EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24

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Bit 23 22 21 20 19 18 17 16

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Symbol EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16

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Bit 15 14 13 12 11 10 9 8

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Symbol EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Bit 7 6 5 4 3 2 1 0
Symbol EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0

Table 152. USB DMA Request Status register (USBDMARSt - address 0xE010 C250) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 0
bit must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit 0
must be 0).
31:2 EPxx Endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 DMA not requested by endpoint xx.
1 DMA requested by endpoint xx.

[1] DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.

9.7.2 USB DMA Request Clear register (USBDMARClr - 0xE010 C254)

Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.

This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.

USBDMARClr is a write only register.

The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 13–151).

Table 153. USB DMA Request Clear register (USBDMARClr - address 0xE010 C254) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the 0
EP0 bit must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 0
bit must be 0).
31:2 EPxx Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 No effect.
1 Clear the corresponding bit in USBDMARSt.

9.7.3 USB DMA Request Set register (USBDMARSet - 0xE010 C258)

Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
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This register allows software to raise a DMA request. This can be useful when switching

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from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA

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mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is

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not raised by hardware. Software can then use this register to manually start the DMA

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transfer.

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Software can also use this register to initiate a DMA transfer to proactively fill an IN

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endpoint buffer before an IN token packet is received from the host.

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USBDMARSet is a write only register.

The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 13–151).

Table 154. USB DMA Request Set register (USBDMARSet - address 0xE010 C258) bit
description
Bit Symbol Value Description Reset
value
0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint 0
and the EP0 bit must be 0).
1 EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and 0
the EP1 bit must be 0).
31:2 EPxx Set the endpoint xx (2 ≤ xx ≤ 31) DMA request. 0
0 No effect.
1 Set the corresponding bit in USBDMARSt.

9.7.4 USB UDCA Head register (USBUDCAH - 0xE010 C280)

The UDCA (USB Device Communication Area) Head register maintains the address
where the UDCA is located in the USB RAM. Refer to Section 13–14.2 “USB device
communication area” and Section 13–14.4 “The DMA descriptor” for more details on the
UDCA and DMA descriptors. USBUDCAH is a read/write register.

Table 155. USB UDCA Head register (USBUDCAH - address 0xE010 C280) bit description
Bit Symbol Description Reset value
6:0 - Reserved. Software should not write ones to reserved bits. The UDCA is 0x00
aligned to 128-byte boundaries.
31:7 UDCA_ADDR Start address of the UDCA. 0

9.7.5 USB EP DMA Status register (USBEpDMASt - 0xE010 C284)

Bits in this register indicate whether DMA operation is enabled for the corresponding
endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in
this register. USBEpDMASt is a read only register.

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Table 156. USB EP DMA Status register (USBEpDMASt - address 0xE010 C284) bit

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description

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Bit Symbol Value Description Reset

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value

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0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for 0

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this endpoint and the EP0_DMA_ENABLE bit must

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be 0).

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1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this 0
endpoint and the EP1_DMA_ENABLE bit must be
0).
31:2 EPxx_DMA_ENABLE endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit. 0
0 The DMA for endpoint EPxx is disabled.
1 The DMA for endpoint EPxx is enabled.

9.7.6 USB EP DMA Enable register (USBEpDMAEn - 0xE010 C288)

Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. USBEpDMAEn is a write only register.

Table 157. USB EP DMA Enable register (USBEpDMAEn - address 0xE010 C288) bit
description
Bit Symbol Value Description Reset
value
0 EP0_DMA_ENABLE 0 Control endpoint OUT (DMA cannot be enabled for 0
this endpoint and the EP0_DMA_ENABLE bit value
must be 0).
1 EP1_DMA_ENABLE 0 Control endpoint IN (DMA cannot be enabled for this 0
endpoint and the EP1_DMA_ENABLE bit must be 0).
31:2 EPxx_DMA_ENABLE Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit. 0
0 No effect.
1 Enable the DMA operation for endpoint EPxx.

9.7.7 USB EP DMA Disable register (USBEpDMADis - 0xE010 C28C)

Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing
zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register
clears the internal DMA_PROCEED flag. Refer to Section 13–14.5.4 “Optimizing
descriptor fetch” for more information on the DMA_PROCEED flag. If a DMA transfer is in
progress for an endpoint when its corresponding bit is cleared, the transfer is completed
before the DMA is disabled. When an error condition is detected during a DMA transfer,
the corresponding bit is cleared by hardware. USBEpDMADis is a write only register.

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Table 158. USB EP DMA Disable register (USBEpDMADis - address 0xE010 C28C) bit

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description

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Bit Symbol Value Description Reset

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value

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0 EP0_DMA_DISABLE 0 Control endpoint OUT (DMA cannot be enabled for 0

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this endpoint and the EP0_DMA_DISABLE bit value

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must be 0).

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1 EP1_DMA_DISABLE 0 Control endpoint IN (DMA cannot be enabled for 0
this endpoint and the EP1_DMA_DISABLE bit value
must be 0).
31:2 EPxx_DMA_DISABLE Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit. 0
0 No effect.
1 Disable the DMA operation for endpoint EPxx.

9.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0xE010 C290)

Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. USBDMAIntSt is a read only register.

Table 159. USB DMA Interrupt Status register (USBDMAIntSt - address 0xE010 C290) bit
description
Bit Symbol Value Description Reset
value
0 EOT End of Transfer Interrupt bit. 0
0 All bits in the USBEoTIntSt register are 0.
1 At least one bit in the USBEoTIntSt is set.
1 NDDR New DD Request Interrupt bit. 0
0 All bits in the USBNDDRIntSt register are 0.
1 At least one bit in the USBNDDRIntSt is set.
2 ERR System Error Interrupt bit. 0
0 All bits in the USBSysErrIntSt register are 0.
1 At least one bit in the USBSysErrIntSt is set.
31:3 - - Reserved, user software should not write NA
ones to reserved bits. The value read from a
reserved bit is not defined.

9.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xE010 C294)

Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to
generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.

Table 160. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xE010 C294) bit
description
Bit Symbol Value Description Reset
value
0 EOT End of Transfer Interrupt enable bit. 0
0 The End of Transfer Interrupt is disabled.
1 The End of Transfer Interrupt is enabled.

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Table 160. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xE010 C294) bit

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description

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Bit Symbol Value Description Reset

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value

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1 NDDR New DD Request Interrupt enable bit. 0

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0 The New DD Request Interrupt is

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disabled.

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1 The New DD Request Interrupt is
enabled.
2 ERR System Error Interrupt enable bit. 0
0 The System Error Interrupt is disabled.
1 The System Error Interrupt is enabled.
31:3 - - Reserved, user software should not write NA
ones to reserved bits. The value read
from a reserved bit is not defined.

9.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xE010 C2A0)
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read only register.

Table 161. USB End of Transfer Interrupt Status register (USBEoTIntSt - address
0xE010 C2A0s) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
0 There is no End of Transfer interrupt request for endpoint xx.
1 There is an End of Transfer Interrupt request for endpoint xx.

9.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xE010 C2A4)
Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt
register. Writing zero has no effect. USBEoTIntClr is a write only register.

Table 162. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address
0xE010 C2A4) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0
0 No effect.
1 Clear the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.

9.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xE010 C2A8)
Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.
Writing zero has no effect. USBEoTIntSet is a write only register.

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Table 163. USB End of Transfer Interrupt Set register (USBEoTIntSet - address

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0xE010 C2A8) bit description

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Bit Symbol Value Description Reset

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value

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Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0

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31:0 EPxx

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0 No effect.

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1 Set the EPxx End of Transfer Interrupt request in the

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USBEoTIntSt register.

9.7.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0xE010

C2AC)
A bit in this register is set when a transfer is requested from the USB device and no valid
DD is detected for the corresponding endpoint. USBNDDRIntSt is a read only register.

Table 164. USB New DD Request Interrupt Status register (USBNDDRIntSt - address
0xE010 C2AC) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 There is no new DD interrupt request for endpoint xx.
1 There is a new DD interrupt request for endpoint xx.

9.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xE010

C2B0)
Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntClr is a write only register.

Table 165. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0xE010
C2B0) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 No effect.
1 Clear the EPxx new DD interrupt request in the
USBNDDRIntSt register.

9.7.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0xE010

C2B4)
Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntSet is a write only register

Table 166. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0xE010
C2B4) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0
0 No effect.
1 Set the EPxx new DD interrupt request in the
USBNDDRIntSt register.

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9.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0xE010 C2B8)

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If a system error (AHB bus error) occurs when transferring the data or when fetching or

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updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read only

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register.

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Table 167. USB System Error Interrupt Status register (USBSysErrIntSt - address

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0xE010 C2B8) bit description

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Bit Symbol Value Description Reset
value
31:0 EPxx Endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 There is no System Error Interrupt request for endpoint xx.
1 There is a System Error Interrupt request for endpoint xx.

9.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0xE010 C2BC)
Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntClr is a write only register.

Table 168. USB System Error Interrupt Clear register (USBSysErrIntClr - address
0xE010 C2BC) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 No effect.
1 Clear the EPxx System Error Interrupt request in the
USBSysErrIntSt register.

9.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xE010 C2C0)
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write only register.

Table 169. USB System Error Interrupt Set register (USBSysErrIntSet - address 0xE010
C2C0) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
0 No effect.
1 Set the EPxx System Error Interrupt request in the
USBSysErrIntSt register.

10. Interrupt handling

This section describes how an interrupt event on any of the endpoints is routed to the
Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event
handling, see Figure 13–43.

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All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an

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interrupt when they receive a packet without an error. All non-isochronous IN endpoints

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generate an interrupt when a packet has been successfully transmitted or when a NAK

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signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see

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Section 13–11.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.

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The interrupt handling is different for Slave and DMA mode.

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Slave mode

If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the
USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For
non-isochronous endpoints, all endpoint interrupt events are divided into two types by the
corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint
interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the
EP_SLOW bit in USBDevIntSt.

For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.

The USBDevIntSt register holds the status of all endpoint interrupt events as well as the
status of various other interrupts (see Section 13–9.2.2). By default, all interrupts (if
enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt
register to request low priority interrupt handling. However, the USBDevIntPri register can
route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt
register.

Only one of the EP_FAST and FRAME interrupt events can be routed to the
USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both
interrupt events are routed to USB_INT_REQ_LP.

Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for
low priority interrupt handling by software.

The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the USBIntSt
register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set.

DMA mode

If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not
enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is
set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer
is enabled for the corresponding endpoint in the USBEpDMASt register.

Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End
of transfer interrupt , new DD request interrupt, and system error interrupt. These interrupt
events set a bit for each endpoint in the respective registers USBEoTIntSt,
USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints
are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request
interrupts and system error interrupt events are routed to the NDDR and ERR bits
respectively in the USBDMAStInt register.

The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the
USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in
USBIntSt, the interrupt is routed to the NVIC.
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interrupt
event on

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EPn

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Slave mode

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from other

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USBEpIntSt Endpoints
. USBDevIntSt
.
.
. FRAME
. EP_FAST
n . EP_SLOW
.
. USBDevIntPri[0] .
.
.
.
. .
. .
. .
USBEpIntEn[n] . .
.
USBEpIntPri[n] .. USBDevIntPri[1]
.
ERR_INT

USBDMARSt USBIntSt
USB_INT_REQ_HP
USB_INT_REQ_LP to NVIC
USB_INT_REQ_DMA
n to DMA engine

EN_USB_INTS

USBEoTIntST
DMA Mode
0

.
.
.
.

31

USBNDDRIntSt
0 USBDMAIntSt
. EOT
.
. NDDR
.
ERR

31

USBSysErrIntSt
0

.
.
.
.

31

For simplicity, USBDevIntEn and USBDMAIntEn are not shown.

Fig 43. Interrupt event handling

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11. Serial interface engine command description

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The functions and registers of the Serial Interface Engine (SIE) are accessed using

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commands, which consist of a command code followed by optional data bytes (read or

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write action). The USBCmdCode (Table 13–149) and USBCmdData (Table 13–150)

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registers are used for these accesses.

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A complete access consists of two phases:

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1. Command phase: the USBCmdCode register is written with the CMD_PHASE field
set to the value 0x05 (Command), and the CMD_CODE field set to the desired
command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is
set.
2. Data phase (optional): for writes, the USBCmdCode register is written with the
CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with
the desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt
is set. For reads, USBCmdCode register is written with the CMD_PHASE field set to
the value 0x02 (Read), and the CMD_CODE field set with command code the read
corresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set,
indicating the data is available for reading in the USBCmdData register. In the case of
multi-byte registers, the least significant byte is accessed first.

An overview of the available commands is given in Table 13–170.

Here is an example of the Read Current Frame Number command (reading 2 bytes):

USBDevIntClr = 0x30; // Clear both CCEMPTY & CDFULL

USBCmdCode = 0x00F50500; // CMD_CODE=0xF5, CMD_PHASE=0x05(Command)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10; // Clear CCEMPTY interrupt bit.
USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
while (!(USBDevIntSt & 0x20)); // Wait for CDFULL.
USBDevIntClr = 0x20; // Clear CDFULL.
CurFrameNum = USBCmdData; // Read Frame number LSB byte.
USBCmdCode = 0x00F50200; // CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
while (!(USBDevIntSt & 0x20)); // Wait for CDFULL.
Temp = USBCmdData; // Read Frame number MSB byte
USBDevIntClr = 0x20; // Clear CDFULL interrupt bit.
CurFrameNum = CurFrameNum | (Temp << 8);

Here is an example of the Set Address command (writing 1 byte):

USBDevIntClr = 0x10; // Clear CCEMPTY.

USBCmdCode = 0x00D00500; // CMD_CODE=0xD0, CMD_PHASE=0x05(Command)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10; // Clear CCEMPTY.
USBCmdCode = 0x008A0100; // CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA),
// CMD_PHASE=0x01(Write)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10; // Clear CCEMPTY.

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Table 170. SIE command code table

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Command name Recipient Code (Hex) Data phase

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Device commands

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Set Address Device D0 Write 1 byte

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Configure Device Device D8 Write 1 byte

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Set Mode Device F3 Write 1 byte

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Read Current Frame Number Device F5 Read 1 or 2 bytes
Read Test Register Device FD Read 2 bytes
Set Device Status Device FE Write 1 byte
Get Device Status Device FE Read 1 byte
Get Error Code Device FF Read 1 byte
Read Error Status Device FB Read 1 byte
Endpoint Commands
Select Endpoint Endpoint 0 00 Read 1 byte (optional)
Endpoint 1 01 Read 1 byte (optional)
Endpoint xx xx Read 1 byte (optional)
Select Endpoint/Clear Interrupt Endpoint 0 40 Read 1 byte
Endpoint 1 41 Read 1 byte
Endpoint xx xx + 40 Read 1 byte
Set Endpoint Status Endpoint 0 40 Write 1 byte
Endpoint 1 41 Write 1 byte
Endpoint xx xx + 40 Write 1 byte
Clear Buffer Selected Endpoint F2 Read 1 byte (optional)
Validate Buffer Selected Endpoint FA None

11.1 Set Address (Command: 0xD0, Data: write 1 byte)

The Set Address command is used to set the USB assigned address and enable the
(embedded) function. The address set in the device will take effect after the status stage
of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is
set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default
endpoint).

Table 171. Device Set Address Register bit description

Bit Symbol Description Reset value
6:0 DEV_ADDR Device address set by the software. After a bus reset this field is set to 0x00
0x00.
7 DEV_EN Device Enable. After a bus reset this bit is set to 1. 0
0: Device will not respond to any packets.
1: Device will respond to packets for function address DEV_ADDR.

11.2 Configure Device (Command: 0xD8, Data: write 1 byte)

A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled and
respond even if the device is not configured, in the default state.

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Table 172. Configure Device Register bit description

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Bit Symbol Description Reset value

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0 CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This

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bit is cleared by hardware when a bus reset occurs. When set, the

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UP_LED signal is driven LOW if the device is not in the suspended state

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(SUS=0).

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7:1 - Reserved, user software should not write ones to reserved bits. The value NA

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read from a reserved bit is not defined.

11.3 Set Mode (Command: 0xF3, Data: write 1 byte)

Table 173. Set Mode Register bit description
Bit Symbol Value Description Reset
value
0 AP_CLK Always PLL Clock. 0
0 USB_NEED_CLK is functional; the 48 MHz clock can be
stopped when the device enters suspend state.
1 USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be
stopped when the device enters suspend state.
1 INAK_CI Interrupt on NAK for Control IN endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed IN transactions generate interrupts.
2 INAK_CO Interrupt on NAK for Control OUT endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed OUT transactions generate
interrupts.
3 INAK_II Interrupt on NAK for Interrupt IN endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed IN transactions generate interrupts.
4 INAK_IO[1] Interrupt on NAK for Interrupt OUT endpoints. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed OUT transactions generate
interrupts.
5 INAK_BI Interrupt on NAK for Bulk IN endpoints. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed IN transactions generate interrupts.
6 INAK_BO[2] Interrupt on NAK for Bulk OUT endpoints. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed OUT transactions generate
interrupts.
7 - - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

[1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.
[2] This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.

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11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2

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bytes)

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F
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Returns the frame number of the last successfully received SOF. The frame number is

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eleven bits wide. The frame number returns least significant byte first. In case the user is

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only interested in the lower 8 bits of the frame number, only the first byte needs to be read.

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• In case no SOF was received by the device at the beginning of a frame, the frame

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number returned is that of the last successfully received SOF.
• In case the SOF frame number contained a CRC error, the frame number returned will
be the corrupted frame number as received by the device.

11.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)

The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk
and AHB slave clock) are running.

11.6 Set Device Status (Command: 0xFE, Data: write 1 byte)

The Set Device Status command sets bits in the Device Status Register.

Table 174. Set Device Status Register bit description

Bit Symbol Value Description Reset
value
0 CON The Connect bit indicates the current connect status of the 0
device. It controls the CONNECT output pin, used for
SoftConnect. Reading the connect bit returns the current connect
status. This bit is cleared by hardware when the VBUS status input
is LOW for more than 3 ms. The 3 ms delay filters out temporary
dips in the VBUS voltage.
0 Writing a 0 will make the CONNECT pin go HIGH.
1 Writing a 1 will make the CONNECT pin go LOW..
1 CON_CH Connect Change. 0
0 This bit is cleared when read.
1 This bit is set when the device’s pull-up resistor is disconnected
because VBUS disappeared. The DEV_STAT interrupt is
generated when this bit is 1.
2 SUS Suspend: The Suspend bit represents the current suspend state. 0
When the device is suspended (SUS = 1) and the CPU writes a 0
into it, the device will generate a remote wakeup. This will only
happen when the device is connected (CON = 1). When the
device is not connected or not suspended, writing a 0 has no
effect. Writing a 1 to this bit has no effect.
0 This bit is reset to 0 on any activity.
1 This bit is set to 1 when the device hasn’t seen any activity on its
upstream port for more than 3 ms.

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Table 174. Set Device Status Register bit description

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Bit Symbol Value Description Reset

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value

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3 SUS_CH Suspend (SUS) bit change indicator. The SUS bit can toggle 0

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because:

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• The device goes into the suspended state.

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•

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The device is disconnected.

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• The device receives resume signalling on its upstream port.
This bit is cleared when read.
0 SUS bit not changed.
1 SUS bit changed. At the same time a DEV_STAT interrupt is
generated.
4 RST Bus Reset bit. On a bus reset, the device will automatically go to 0
the default state. In the default state:
• Device is unconfigured.
• Will respond to address 0.
• Control endpoint will be in the Stalled state.
• All endpoints are unrealized except control endpoints EP0
and EP1.
• Data toggling is reset for all endpoints.
• All buffers are cleared.
• There is no change to the endpoint interrupt status.
• DEV_STAT interrupt is generated.
Note: Bus resets are ignored when the device is not connected
(CON=0).
0 This bit is cleared when read.
1 This bit is set when the device receives a bus reset. A DEV_STAT
interrupt is generated.
7:5 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

11.7 Get Device Status (Command: 0xFE, Data: read 1 byte)

The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in Table 13–174.

Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.

11.8 Get Error Code (Command: 0xFF, Data: read 1 byte)

Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.

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Table 175. Get Error Code Register bit description

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Bit Symbol Value Description Reset

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value

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3:0 EC Error Code. 0x0

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0000 No Error.

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0001 PID Encoding Error.

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0010 Unknown PID.

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0011 Unexpected Packet - any packet sequence violation from the
specification.
0100 Error in Token CRC.
0101 Error in Data CRC.
0110 Time Out Error.
0111 Babble.
1000 Error in End of Packet.
1001 Sent/Received NAK.
1010 Sent Stall.
1011 Buffer Overrun Error.
1100 Sent Empty Packet (ISO Endpoints only).
1101 Bitstuff Error.
1110 Error in Sync.
1111 Wrong Toggle Bit in Data PID, ignored data.
4 EA - The Error Active bit will be reset once this register is read.
7:5 - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

11.9 Read Error Status (Command: 0xFB, Data: read 1 byte)

This command reads the 8-bit Error register from the USB device. This register records
which error events have recently occurred in the SIE. If any of these bits are set, the
ERR_INT bit of USBDevIntSt is set. The error bits are cleared after reading this register.

Table 176. Read Error Status Register bit description

Bit Symbol Description Reset value
0 PID_ERR PID encoding error or Unknown PID or Token CRC. 0
1 UEPKT Unexpected Packet - any packet sequence violation from the 0
specification.
2 DCRC Data CRC error. 0
3 TIMEOUT Time out error. 0
4 EOP End of packet error. 0
5 B_OVRN Buffer Overrun. 0
6 BTSTF Bit stuff error. 0
7 TGL_ERR Wrong toggle bit in data PID, ignored data. 0

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11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))

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The Select Endpoint command initializes an internal pointer to the start of the selected

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buffer in EP_RAM. Optionally, this command can be followed by a data read, which

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returns some additional information on the packet(s) in the endpoint buffer(s). The

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command code of the Select Endpoint command is equal to the physical endpoint

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number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.

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Table 177. Select Endpoint Register bit description
Bit Symbol Value Description Reset
value
0 FE Full/Empty. This bit indicates the full or empty status of the 0
endpoint buffer(s). For IN endpoints, the FE bit gives the
ANDed result of the B_1_FULL and B_2_FULL bits. For OUT
endpoints, the FE bit gives ORed result of the B_1_FULL and
B_2_FULL bits. For single buffered endpoints, this bit simply
reflects the status of B_1_FULL.
0 For an IN endpoint, at least one write endpoint buffer is empty.
1 For an OUT endpoint, at least one endpoint read buffer is full.
1 ST Stalled endpoint indicator. 0
0 The selected endpoint is not stalled.
1 The selected endpoint is stalled.
2 STP SETUP bit: the value of this bit is updated after each 0
successfully received packet (i.e. an ACKed package on that
particular physical endpoint).
0 The STP bit is cleared by doing a Select Endpoint/Clear
Interrupt on this endpoint.
1 The last received packet for the selected endpoint was a
SETUP packet.
3 PO Packet over-written bit. 0
0 The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’
command.
1 The previously received packet was over-written by a SETUP
packet.
4 EPN EP NAKed bit indicates sending of a NAK. If the host sends an 0
OUT packet to a filled OUT buffer, the device returns NAK. If
the host sends an IN token packet to an empty IN buffer, the
device returns NAK.
0 The EPN bit is reset after the device has sent an ACK after an
OUT packet or when the device has seen an ACK after sending
an IN packet.
1 The EPN bit is set when a NAK is sent and the interrupt on NAK
feature is enabled.
5 B_1_FULL The buffer 1 status. 0
0 Buffer 1 is empty.
1 Buffer 1 is full.

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Table 177. Select Endpoint Register bit description

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Bit Symbol Value Description Reset

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value

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6 B_2_FULL The buffer 2 status. 0

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0 Buffer 2 is empty.

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1 Buffer 2 is full.

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7 - - Reserved, user software should not write ones to reserved bits. NA

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The value read from a reserved bit is not defined.

11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1

byte)
Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the
following differences:

• They clear the bit corresponding to the endpoint in the USBEpIntSt register.
• In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
• Reading one byte is obligatory.
Remark: This command may be invoked by using the USBCmdCode and USBCmdData
registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the
USBEpIntClr register is recommended.

11.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.

Table 178. Set Endpoint Status Register bit description

Bit Symbol Value Description Reset
value
0 ST Stalled endpoint bit. A Stalled control endpoint is automatically 0
unstalled when it receives a SETUP token, regardless of the
content of the packet. If the endpoint should stay in its stalled
state, the CPU can stall it again by setting this bit. When a stalled
endpoint is unstalled - either by the Set Endpoint Status
command or by receiving a SETUP token - it is also re-initialized.
This flushes the buffer: in case of an OUT buffer it waits for a
DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID. There
is no change of the interrupt status of the endpoint. When
already unstalled, writing a zero to this bit initializes the endpoint.
When an endpoint is stalled by the Set Endpoint Status
command, it is also re-initialized.
0 The endpoint is unstalled.
1 The endpoint is stalled.
4:1 - - Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

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Bit Symbol Value Description Reset

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value

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5 DA Disabled endpoint bit. 0

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0 The endpoint is enabled.

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1 The endpoint is disabled.

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6 RF_MO Rate Feedback Mode. 0

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0 Interrupt endpoint is in the Toggle mode.
1 Interrupt endpoint is in the Rate Feedback mode. This means
that transfer takes place without data toggle bit.
7 CND_ST Conditional Stall bit. 0
0 Unstalls both control endpoints.
1 Stall both control endpoints, unless the STP bit is set in the
Select Endpoint register. It is defined only for control OUT
endpoints.

11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))

When an OUT packet sent by the host has been received successfully, an internal
hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by
returning a NAK. When the device software has read the data, it should free the buffer by
issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the
buffer is cleared, new packets will be accepted.

When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and
again check the status of the PO bit.

See Section 13–13 “Slave mode operation” for a description of when this command is
used.

Table 179. Clear Buffer Register bit description

Bit Symbol Value Description Reset
value
0 PO Packet over-written bit. This bit is only applicable to the control 0
endpoint EP0.
0 The previously received packet is intact.
1 The previously received packet was over-written by a later SETUP
packet.
7:1 - - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

11.14 Validate Buffer (Command: 0xFA, Data: none)

When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
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Validate Buffer command and cleared when the data has been sent on the USB bus and

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the buffer is empty.

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A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet

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Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP

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packet. For the control endpoint the validated buffer will be invalidated when a SETUP

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packet is received.

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See Section 13–13 “Slave mode operation” for a description of when this command is
used.

12. USB device controller initialization

The LPC29xx USB device controller initialization includes the following steps:

1. Enable the USB device block through the PMU, <tbd>.

2. Configure and enable the USB PLL in the CGU1, see Table 3–14.
3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits
in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until
they are set.
4. Enable the USB pin functions by writing to the corresponding port configuration
register, see Table 6–57.
5. Disable the pull-up resistor on the USB_VBUS pin using the corresponding port
configuration register, see Table 6–58.
6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the
EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.
7. Enable endpoint interrupts (Slave mode):
– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
USBEpIntEn.
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,
and possibly EP_FAST).
8. Configure the DMA (DMA mode):
– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
USBSysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0
0000).
– Enable the desired endpoints for DMA operation using USBEpDMAEn.

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– Set EOT, DDR, and ERR bits in USBDMAIntEn.

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9. Install USB interrupt handler in the NVIC by writing its address to the appropriate

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vector table location and enabling the USB interrupt in the NVIC.

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10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address

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command. A bus reset will also cause this to happen.

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11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status

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command.

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The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.

13. Slave mode operation

In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.

13.1 Interrupt generation

In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the
USBEpIntEn register, and are observable in the USBEpIntSt register.

All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.

For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.

13.2 Data transfer for OUT endpoints

When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,
and set the PKT_RDY bit (Table 13–145 ).

Software can now start reading the data from the USBRxData register (Table 13–144).
When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is
set in the USBDevSt register. Software now issues a Clear Buffer (refer to Table 13–179)
command. The endpoint is now ready to accept the next packet. For OUT isochronous
endpoints, the next packet will be received irrespective of whether the buffer has been
cleared. Any data not read from the buffer before the end of the frame is lost. See Section
13–15 “Double buffered endpoint operation” for more details.

If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.

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13.3 Data transfer for IN endpoints

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When writing data to an endpoint buffer, WR_EN (Section 13–9.5.5 “USB Control register

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(USBCtrl - 0xE010 C228)”) is set and software writes to the number of bytes it is going to

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send in the packet to the USBTxPLen register (Section 13–9.5.4). It can then write data

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continuously in the USBTxData register.

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When the the number of bytes programmed in USBTxPLen have been written to

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USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt
register. Software issues a Validate Buffer (Section 13–11.14 “Validate Buffer (Command:
0xFA, Data: none)”) command. The endpoint is now ready to send the packet. For IN
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.

Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.

14. DMA operation

In DMA mode, the DMA transfers data between RAM and the endpoint buffer.

The following sections discuss DMA mode operation. Background information is given in
sections Section 13–14.2 “USB device communication area” and Section 13–14.3
“Triggering the DMA engine”. The fields of the DMA Descriptor are described in section
Section 13–14.4 “The DMA descriptor”. The last three sections describe DMA operation:
Section 13–14.5 “Non-isochronous endpoint operation”, Section 13–14.6 “Isochronous
endpoint operation”, and Section 13–14.7 “Auto Length Transfer Extraction (ATLE) mode
operation”.

14.1 Transfer terminology

Within this section three types of transfers are mentioned:

1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
(RAM).
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.

14.2 USB device communication area

The CPU and DMA controller communicate through a common area of memory, called the
USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA
Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP

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points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs

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for unrealized endpoints and endpoints disabled for DMA operation are ignored and can

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be set to a NULL (0x0) value.

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The start address of the UDCA is stored in the USBUDCAH register. The UDCA can

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reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA

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controller.

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Figure 36 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH)
register and DMA Descriptors.

UDCA NULL
0
NULL
NULL
1 Next_DD_pointer Next_DD_pointer Next_DD_pointer

2
DDP-EP2
DD-EP2-a DD-EP2-b DD-EP2-c

NULL
UDCA HEAD
REGISTER NULL
Next_DD_pointer Next_DD_pointer
16
DDP-EP16

DD-EP16-a DD-EP16-b

31
DDP-EP31

Fig 44. UDCA Head register and DMA Descriptors

14.3 Triggering the DMA engine

An endpoint raises a DMA request when Slave mode is disabled by setting the
corresponding bit in the USBEpIntEn register to 0 (Section 13–9.3.2) and an endpoint
interrupt occurs (see Section 13–9.7.1 “USB DMA Request Status register (USBDMARSt
- 0xE010 C250)”).

A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for
the endpoint.

All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint
number is processed first.

In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section 13–11.3).

14.4 The DMA descriptor

DMA transfers are described by a data structure called the DMA Descriptor (DD).
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DDs are placed in the USB RAM. These descriptors can be located anywhere in the USB

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RAM at word-aligned addresses. USB RAM is part of the system memory that is used for

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the USB purposes. It is located at address 0x7FD0 0000 and is 8 kB in size.

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DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints

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are five words long.

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The parameters associated with a DMA transfer are:

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• The start address of the DMA buffer
• The length of the DMA buffer
• The start address of the next DMA descriptor
• Control information
• Count information (number of bytes transferred)
• Status information

Table 13–180 lists the DMA descriptor fields.

Table 180. DMA descriptor

Word Access Access Bit Description
position (H/W) (S/W) position
0 R R/W 31:0 Next_DD_pointer (USB RAM address)
1 R R/W 1:0 DMA_mode (00 -Normal; 01 - ATLE)
R R/W 2 Next_DD_valid (1 - valid; 0 - invalid)
- - 3 Reserved
R R/W 4 Isochronous_endpoint (1 - isochronous;
0 - non-isochronous)
R R/W 15:5 Max_packet_size
R/W[1] R/W 31:16 DMA_buffer_length
This value is specified in bytes for non-isochronous
endpoints and in number of packets for isochronous
endpoints.
2 R/W R/W 31:0 DMA_buffer_start_addr

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Table 180. DMA descriptor

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Word Access Access Bit Description

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position (H/W) (S/W) position

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3 R/W R/I 0 DD_retired (To be initialized to 0)

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W R/I 4:1 DD_status (To be initialized to 0000):

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0000 - NotServiced

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0001 - BeingServiced

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0010 - NormalCompletion
0011 - DataUnderrun (short packet)
1000 - DataOverrun
1001 - SystemError
W R/I 5 Packet_valid (To be initialized to 0)
W R/I 6 LS_byte_extracted (ATLE mode) (To be initialized to 0)
W R/I 7 MS_byte_extracted (ATLE mode) (To be initialized to 0)
R W 13:8 Message_length_position (ATLE mode)
- - 15:14 Reserved
R/W R/I 31:16 Present_DMA_count (To be initialized to 0)
4 R/W R/W 31:0 Isochronous_packetsize_memory_address

[1] Write only in ATLE mode

Legend: R - Read; W - Write; I - Initialize

14.4.1 Next_DD_pointer
Pointer to the memory location from where the next DMA descriptor will be fetched.

14.4.2 DMA_mode
Specifies the DMA mode of operation. Two modes have been defined: Normal and
Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes
the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is
extracted from the incoming data. See Section 13–14.7 “Auto Length Transfer Extraction
(ATLE) mode operation” on page 204 for more details.

14.4.3 Next_DD_valid
This bit indicates whether the software has prepared the next DMA descriptor. If set, the
DMA engine fetches the new descriptor when it is finished with the current one.

14.4.4 Isochronous_endpoint
When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence
5 words have to be read when fetching it.

14.4.5 Max_packet_size
The maximum packet size of the endpoint. This parameter is used while transferring the
data for IN endpoints from the memory. It is used for OUT endpoints to detect the short
packet. This is applicable to non-isochronous endpoints only. This field should be set to
the same MPS value that is assigned for the endpoint using the USBMaxPSize register.

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14.4.6 DMA_buffer_length

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This indicates the depth of the DMA buffer allocated for transferring the data. The DMA

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engine will stop using this descriptor when this limit is reached and will look for the next

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descriptor.

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In Normal mode operation, software sets this value for both IN and OUT endpoints. In

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ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints,

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hardware sets this value using the extracted length of the data stream.

For isochronous endpoints, DMA_buffer_length is specified in number of packets, for

non-isochronous endpoints in bytes.

14.4.7 DMA_buffer_start_addr
The address where the data is read from or written to. This field is updated each time the
DMA engine finishes transferring a packet.

14.4.8 DD_retired
This bit is set by hardware when the DMA engine finishes the current descriptor. This
happens when the end of the buffer is reached, a short packet is transferred
(non-isochronous endpoints), or an error condition is detected.

14.4.9 DD_status
The status of the DMA transfer is encoded in this field. The following codes are defined:

• NotServiced - No packet has been transferred yet.

• BeingServiced - At least one packet is transferred.
• NormalCompletion - The DD is retired because the end of the buffer is reached and
there were no errors. The DD_retired bit is also set.
• DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is
terminated because a short packet is received. The DD_retired bit is also set.
• DataOverrun - The end of the DMA buffer is reached in the middle of a packet
transfer. This is an error situation. The DD_retired bit is set. The present DMA count
field is equal to the value of DMA_buffer_length. The packet must be re-transmitted
from the endpoint buffer in another DMA transfer. The corresponding
EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.
• SystemError - The DMA transfer being serviced is terminated because of an error on
the AHB bus. The DD_retired bit is not set in this case. The corresponding
EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen
while updating the DD, the DD fields in RAM may be unreliable.

14.4.10 Packet_valid
This bit is used for isochronous endpoints. It indicates whether the last packet transferred
to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was
received without errors. See Section 13–14.6 “Isochronous endpoint operation” on page
202 for isochronous endpoint operation.

This bit is unnecessary for non-isochronous endpoints because a DMA request is

generated only for packets without errors, and thus Packet_valid will always be set when
the request is generated.

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14.4.11 LS_byte_extracted

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Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of

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the transfer length has been extracted. The extracted size is reflected in the

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DMA_buffer_length field, bits 23:16.

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14.4.12 MS_byte_extracted

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Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of

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the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.

14.4.13 Present_DMA_count
The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.

For isochronous endpoints, Present_DMA_count is the number of packets transferred; for

non-isochronous endpoints, Present_DMA_count is the number of bytes.

14.4.14 Message_length_position
Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.

14.4.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See Figure 13–45. This is applicable to
isochronous endpoints only.

14.5 Non-isochronous endpoint operation

14.5.1 Setting up DMA transfers

Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled
for DMA transfer. These DDs are present in the USB RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the USBEpDMAEn register (Section 13–9.7.6).The DMA_mode bit field in the descriptor
is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in
Table 13–180.

DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).

14.5.2 Finding DMA Descriptor

When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first
determine whether a new descriptor has to the fetched or not. A new descriptor does not
have to be fetched if the last packet transferred was for the same endpoint and the DD is
not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this
condition (see Section 13–14.5.4 “Optimizing descriptor fetch” on page 201).

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If a new descriptor has to be read, the DMA engine will calculate the location of the DDP

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for this endpoint and will fetch the start address of the DD from this location. A DD start

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address at location zero is considered invalid. In this case the NDDR interrupt is raised.

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All other word-aligned addresses are considered valid.

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When the DD is fetched, the DD status word (word 3) is read first and the status of the

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DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the

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DMA engine will read the control word (word 1) of the DD.

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If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)
of the DD and load it to the DDP. The new DDP is written to the UDCA area.

The full DD (4 words) will then be fetched from the address in the DDP. The DD will give
the details of the DMA transfer to be done. The DMA engine will load its hardware
resources with the information fetched from the DD (start address, DMA count etc.).

If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR
interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.

14.5.3 Transferring the data

For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and
transferred to the USB RAM memory locations starting from DMA_buffer_start_addr. For
IN endpoints, the data is fetched from the USB RAM at DMA_buffer_start_addr and
written to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are
updated after each packet is transferred.

14.5.4 Optimizing descriptor fetch

A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a
new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet
transfer, hardware sets an an internal flag called DMA_PROCEED.

The DMA_PROCEED flag is cleared after the required number of bytes specified in the
DMA_buffer_length field is transferred. It is also cleared when the software writes into the
USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to
to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the
USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation
for any endpoint.

14.5.5 Ending the packet transfer

On completing a packet transfer, the DMA engine writes back the DD with updated status
information to the same memory location from where it was read. The
DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are
updated.

A DD can have the following types of completion:

Normal completion - If the current packet is fully transferred and the

Present_DMA_count field equals the DMA_buffer_length, the DD has completed
normally. The DD will be written back to memory with DD_retired set and DD_status set
to NormalCompletion. The EOT interrupt is raised for this endpoint.

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USB transfer end completion - If the current packet is fully transferred and its size is

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less than the Max_packet_size field, and the end of the DMA buffer is still not reached,

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the USB transfer end completion occurs. The DD will be written back to the memory

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with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT

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interrupt is raised for this endpoint.

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Error completion - If the current packet is partially transferred i.e. the end of the DMA

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buffer is reached in the middle of the packet transfer, an error situation occurs. The DD

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is written back with DD_retired set and DD_status set to the DataOverrun status code.
The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt
register is cleared. The packet will be re-sent from the endpoint buffer to memory when
the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn
register.

14.5.6 No_Packet DD
For an IN transfer, if the system does not have any data to send for a while, it can respond
to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the
Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a
No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt
corresponding to the endpoint without transferring a packet. The DD is retired with a
status code of NormalCompletion. This can be repeated as often as necessary. The
device will respond to IN token packets on the USB bus with a NAK until a DD with a data
packet is programmed and the DMA transfers the packet into the endpoint buffer.

14.6 Isochronous endpoint operation

For isochronous endpoints, the packet size can vary for each packet. There is one packet
per isochronous endpoint for each frame.

14.6.1 Setting up DMA transfers

Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of
the Isochronous_packetsize_memory_address field. All other fields are initialized the
same as for non-isochronous endpoints.

For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in

frames rather than bytes.

14.6.2 Finding the DMA Descriptor

Finding the descriptors is done in the same way as that for a non-isochronous endpoint.

A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME
interrupt. On processing the request, the DMA engine will fetch the descriptor and if
Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address
from the fifth word of the DD.

14.6.3 Transferring the Data

The data is transferred to or from the memory location DMA_buffer_start_addr. After the
end of the packet transfer the Present_DMA_count value is incremented by 1.

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The isochronous packet size is stored in memory as shown in figure 32. Each word in the

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packet size memory shown is divided into fields: Frame_number (bits 31 to 17),

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Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet

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size memory for a given DD should be DMA_buffer_length words in size – one word for

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each packet to transfer.

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OUT endpoints

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At the completion of each frame, the packet size is written to the address location in
Isochronous_packet_size_memory_address, and
Isochronous_packet_size_memory_address is incremented by 4.

IN endpoints

Only the Packet_length field of the isochronous packet size word is used. For each frame,
an isochronous data packet of size specified by this field is transferred from the USB
device to the host, and Isochronous_packet_size_memory_address is incremented by 4
at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by
the USB device.

14.6.4 DMA descriptor completion

DDs for isochronous endpoints can only end with a status code of NormalCompletion
since there is no short packet on Isochronous endpoints, and the USB transfer continues
indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous
endpoints.

14.6.5 Isochronous OUT Endpoint Operation Example

Assume that an isochronous endpoint is programmed for the transfer of 10 frames and
that the transfer begins when the frame number is 21. After transferring four frames with
packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map
appear as shown in Figure 13–45.

The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35.

The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.

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Next_DD_Pointer
W0

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DMA_buffer_length Max_packet_size Isochronous_endpoint Next_DD_Valid DMA_mode

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0x000A 0x0 1 0 0

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DMA_buffer_start_addr

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W2
0x80000000
Present_DMA_Count ATLE settings Packet_Valid DD_Status DD_Retired
W3
0x0 NA NA 0x0 0

Isocronous_packetsize_memory_address
W4
0x60000000

after 4 packets

W0 0x0

W1 0x000A0010
FULL
W2 0x80000035

W3 0x4 - - 0x1 0
frame_ number Packet_Valid Packet_Length
EMPTY
W4 0x60000010 31 16 15 0
21 1 10
22 1 15
23 1 8
24 1 20

data memory

packet size memory

Fig 45. Isochronous OUT endpoint operation example

14.7 Auto Length Transfer Extraction (ATLE) mode operation

Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are
capable of concatenating small USB transfers (delta transfers) to form a single large USB
transfer. For OUT USB transfers, the device hardware has to break up this concatenated
transfer back into the original delta transfers and transfer them to separate DMA buffers.
This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE)
mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only.

OUT transfers in ATLE mode

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data to be sent data in packets data to be stored in USB

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by host driver as seen on USB RAM by DMA engine

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160 bytes DMA_buffer_start_addr

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64 bytes
of DD1

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160 bytes

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64 bytes

32 bytes

32 bytes
100 bytes
100 bytes
64 bytes DMA_buffer_start_addr
of DD2

4 bytes

Fig 46. Data transfer in ATLE mode

Figure 13–46 shows a typical OUT USB transfer in ATLE mode, where the host
concatenates two USB transfers of 160 bytes and 100 bytes, respectively. Given a
MaxPacketSize of 64, the device hardware interprets this USB transfer as four packets of
64 bytes and a short packet of 4 bytes. The third and fourth packets are concatenated.
Note that in Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32,
and 64 and 36 bytes.

It is now the responsibility of the DMA engine to separate these two USB transfers and put
them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1
(DD1) and DMA Descriptor 2 (DD2).

Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the
USB transfer) specified by Message_length_position from the incoming data packets and
writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the
DMA_buffer_length are extracted in the event they are split between two packets, the
flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective
byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the
normal mode.

The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when

preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again
for the next DD.

If DD1 is retired during the transfer of a concatenated packet (such as the third packet in
Figure 13–46), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1
is retired with DD_status set to the DataOverrun status code. This is treated as an error
condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared by
hardware.

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In ATLE mode, the last buffer length to be transferred always ends with a short or empty

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packet indicating the end of the USB transfer. If the concatenated transfer lengths are

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such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host

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will send an empty packet to mark the end of the USB transfer.

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IN transfers in ATLE mode

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For IN USB transfers from the device to the host, DMA_buffer_length is set by the device

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software as in normal mode.

In ATLE mode, the device concatenates data from multiple DDs to form a single USB
transfer. If a DD is retired in the middle of a packet (packet size is less than
MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the
remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s
buffer.

If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer
length for the current DD has completed before the MaxPacketSize packet boundary, then
the available bytes from current DD are sent as a short packet on USB, which marks the
end of the USB transfer for the host.

If the last buffer length completes on a MaxPacketSize packet boundary, the device
software must program the next DD with DMA_buffer_length field 0, so that an empty
packet is sent by the device to mark the end of the USB transfer for the host.

14.7.1 Setting up the DMA transfer

For OUT endpoints, the host hardware needs to set the field Message_length_position in
the DD. This indicates the start location of the message length in the incoming data
packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT
endpoints because this field is updated by the device hardware after the extraction of the
buffer length.

For IN endpoints, descriptors are set in the same way as in normal mode operation.

Since a single packet can be split between two DDs, software should always keep two
DDs ready, except for the last DMA transfer which ends with a short or empty packet.

14.7.2 Finding the DMA Descriptor

DMA descriptors are found in the same way as the normal mode operation.

14.7.3 Transferring the Data

OUT endpoints

If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the
hardware will extract the transfer length from the data stream and program
DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and
MS_byte_extracted bits will be set.

IN endpoints

The DMA transfer proceeds as in normal mode and continues until the number of bytes
transferred equals the DMA_buffer_length.

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14.7.4 Ending the packet transfer

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The DMA engine proceeds with the transfer until the number of bytes specified in the field

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DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be

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generated. If this happens in the middle of the packet, the linked DD will get loaded and

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the remaining part of the packet gets transferred to or from the address pointed by the

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new DD.

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OUT endpoints

If the linked DD is not valid and the packet is partially transferred to memory, the DD ends
with DataOverrun status code set, and the DMA will be disabled for this endpoint.
Otherwise DD_status will be updated with the NormalCompletion status code.

IN endpoints

If the linked DD is not valid and the packet is partially transferred to USB, the DD ends
with a status code of NormalCompletion in the DD_status field. This situation corresponds
to the end of the USB transfer, and the packet will be sent as a short packet. Also, when
the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the
end of the USB transfer.

15. Double buffered endpoint operation

The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to
increase data throughput.

When a double-buffered endpoint is realized, enough space for both endpoint buffers is
automatically allocated in the EP_RAM. See Section 13–9.4.1.

For the following discussion, the endpoint buffer currently accessible to the CPU or DMA
engine for reading or writing is said to be the active buffer.

15.1 Bulk endpoints

For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or
Validate Buffer commands.

The following example illustrates how double buffering works for a Bulk OUT endpoint in
Slave mode:

Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is
B_1.

1. The host sends a data packet to the endpoint. The device hardware puts the packet
into B_1, and generates an endpoint interrupt.
2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
While B_1 is still being read, the host sends a second packet, which device hardware
places in B_2, and generates an endpoint interrupt.
3. Software is still reading from B_1 when the host attempts to send a third packet. Since
both B_1 and B_2 are full, the device hardware responds with a NAK.
4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.

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5. Software sends the SIE Select Endpoint command to read the Select Endpoint

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Register and test the FE bit. Software finds that the active buffer (B_2) has data

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(FE=1). Software clears the endpoint interrupt and begins reading the contents of

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B_2.

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6. The host resends the third packet which device hardware places in B_1. An endpoint

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interrupt is generated.

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7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer

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command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
packet from B_1.
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.

The following example illustrates how double buffering works for a Bulk IN endpoint in
Slave mode:

Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.

1. The host requests a data packet by sending an IN token packet. The device responds
with a NAK and generates an endpoint interrupt.
2. Software clears the endpoint interrupt. The device has three packets to send.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the
second packet. Software sends a SIE Validate Buffer command, and the active buffer
is switched to B_1.
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint
interrupt occurs.
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and
validates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
7. The device successfully sends the second packet from B_2 and generates an
endpoint interrupt.
8. Software has no more packets to send, so it simply clears the interrupt.
9. The device successfully sends the third packet from B_1 and generates an endpoint
interrupt.
10. Software has no more packets to send, so it simply clears the interrupt.

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11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by

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software will go into B_2.

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In DMA mode, switching of the active buffer is handled automatically in hardware. For

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Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double

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buffering can be accomplished by manually starting a packet transfer using the

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USBDMARSet register.

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15.2 Isochronous endpoints
For isochronous endpoints, the active data buffer is switched by hardware when the
FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do not
cause the active buffer to be switched.

Double buffering allows the software to make full use of the frame interval writing or
reading a packet to or from the active buffer, while the packet in the other buffer is being
sent or received on the bus.

For an OUT isochronous endpoint, any data not read from the active buffer before the end
of the frame is lost when it switches.

For an IN isochronous endpoint, if the active buffer is not validated before the end of the
frame, an empty packet is sent on the bus when the active buffer is switched, and its
contents will be overwritten when it becomes active again.

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1. How to read this chapter

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The USB host controller is available on LPC2030 and LPC2939 only.

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2. Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller and I2C. The I2C
interface controls the external OTG ATX.

The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.

The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.

Table 181. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
AHB Advanced High-Performance Bus
ATX Analog Transceiver
DMA Direct Memory Access
FS Full Speed
LS Low Speed
OHCI Open Host Controller Interface
USB Universal Serial Bus

2.1 Features
• OHCI compliant.
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wakeup activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.

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2.2 Architecture

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The architecture of the USB host controller is shown below in Figure 14–47.

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register

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interface

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(AHB slave)

A
REGISTER
U1
INTERFACE
port
USB
ATX
port 1 ATX
HOST CONTROL
AHB bus

CONTROLLER port 2 LOGIC/

DMA interface
(AHB master) BUS PORT
MASTER MUX USB
INTERFACE ATX
U2
port

USB HOST BLOCK

Fig 47. USB Host controller block diagram

3. Interfaces
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.

3.1 Pin description

Table 182. USB OTG port pins
Pin name Direction Description Pin category
USB_VBUS I VBUS status input. When this function is not enabled USB Connector
via its corresponding PINSEL register, it is driven
HIGH internally.
Port U1
USB_D+1 I/O Positive differential data USB Connector
USB_D−1 I/O Negative differential data USB Connector
USB_CONNECT1 O SoftConnect control signal Control
USB_UP_LED1 O GoodLink LED control signal Control
USB_PPWR1 O Port power enable Host power switch
USB_PWRD1 I Port power status Host power switch
USB_OVRCR1 I Over-current status Host power switch
USB_HSTEN1 O Host enabled status
Port U2
USB_D+2 I/O Positive differential data USB Connector
USB_D−2 I/O Negative differential data USB Connector
USB_CONNECT2 O SoftConnect control signal Control
USB_UP_LED2 O GoodLink LED control signal Control
USB_PPWR2 O Port power enable Host power switch

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Table 182. USB OTG port pins

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Pin name Direction Description Pin category

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U2PWRD2 I Port power status Host power switch

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USB_OVRCR2 I Over-current status Host power switch

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USB_HSTEN2 O Host enabled status Control

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3.1.1 USB host usage note

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Both ports can be configured as USB hosts. For details on how to connect the USB ports,
see the USB OTG chapter, Section 15–5.

3.2 Software interface

The software interface of the USB host block consists of a register view and the format
definitions for the endpoint descriptors. For details on these two aspects see the OHCI
specification. The register map is shown in the next subsection.

3.2.1 Register map

The following registers are located in the AHB clock ‘cclk’ domain. They can be accessed
directly by the processor. All registers are 32 bit wide and aligned in the word address
boundaries.

Table 183. USB Host register address definitions

Name Address R/W[1] Function Reset value
HcRevision 0xE010 C000 R BCD representation of the version of the HCI 0x10
specification that is implemented by the Host Controller.
HcControl 0xE010 C004 R/W Defines the operating modes of the HC. 0x0
HcCommandStatus 0xE010 C008 R/W This register is used to receive the commands from the 0x0
Host Controller Driver (HCD). It also indicates the status
of the HC.
HcInterruptStatus 0xE010 C00C R/W Indicates the status on various events that cause 0x0
hardware interrupts by setting the appropriate bits.
HcInterruptEnable 0xE010 C010 R/W Controls the bits in the HcInterruptStatus register and 0x0
indicates which events will generate a hardware
interrupt.
HcInterruptDisable 0xE010 C014 R/W The bits in this register are used to disable 0x0
corresponding bits in the HCInterruptStatus register and
in turn disable that event leading to hardware interrupt.
HcHCCA 0xE010 C018 R/W Contains the physical address of the host controller 0x0
communication area.
HcPeriodCurrentED 0xE010 C01C R Contains the physical address of the current isochronous 0x0
or interrupt endpoint descriptor.
HcControlHeadED 0xE010 C020 R/W Contains the physical address of the first endpoint 0x0
descriptor of the control list.
HcControlCurrentED 0xE010 C024 R/W Contains the physical address of the current endpoint 0x0
descriptor of the control list
HcBulkHeadED 0xE010 C028 R/W Contains the physical address of the first endpoint 0x0
descriptor of the bulk list.
HcBulkCurrentED 0xE010 C02C R/W Contains the physical address of the current endpoint 0x0
descriptor of the bulk list.

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Table 183. USB Host register address definitions …continued

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Name Address R/W[1] Function Reset value

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HcDoneHead 0xE010 C030 R Contains the physical address of the last transfer 0x0

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descriptor added to the ‘Done’ queue.

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HcFmInterval 0xE010 C034 R/W Defines the bit time interval in a frame and the full speed 0x2EDF

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maximum packet size which would not cause an

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overrun.

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HcFmRemaining 0xE010 C038 R A 14-bit counter showing the bit time remaining in the 0x0
current frame.
HcFmNumber 0xE010 C03C R Contains a 16-bit counter and provides the timing 0x0
reference among events happening in the HC and the
HCD.
HcPeriodicStart 0xE010 C040 R/W Contains a programmable 14-bit value which determines 0x0
the earliest time HC should start processing a periodic
list.
HcLSThreshold 0xE010 C044 R/W Contains 11-bit value which is used by the HC to 0x628h
determine whether to commit to transfer a maximum of
8-byte LS packet before EOF.
HcRhDescriptorA 0xE010 C048 R/W First of the two registers which describes the 0xFF000902
characteristics of the root hub.
HcRhDescriptorB 0xE010 C04C R/W Second of the two registers which describes the 0x60000h
characteristics of the Root Hub.
HcRhStatus 0xE010 C050 R/W This register is divided into two parts. The lower D-word 0x0
represents the hub status field and the upper word
represents the hub status change field.
HcRhPortStatus[1] 0xE010 C054 R/W Controls and reports the port events on a per-port basis. 0x0
HcRhPortStatus[2] 0xE010 C058 R/W Controls and reports the port events on a per port basis. 0x0
Module_ID/Ver_Rev_ID 0xE010 C0FC R IP number, where yy (0x00) is unique version number 0x3505yyzz
and zz (0x00) is a unique revision number.

[1] The R/W column in Table 14–183 lists the accessibility of the register:
a) Registers marked ‘R’ for access will return their current value when read.
b) Registers marked ‘R/W’ allow both read and write.

3.2.2 USB Host Register Definitions

Refer to the OHCI specification document for register definitions.

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1. How to read this chapter

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The USB device controller is available in LPC2927/29, LPC2930, and LPC2939 only.

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Note that the host controller is not implemented on the LPC2927 and LPC2929.

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Depending on the LPC29xx part, different USB port configurations are available.

Table 184. LPC29xx USB port configurations

Part Port 1 device Port 1 host Port 1 OTG Port 2 host Port 2 device
LPC2921/23/25 yes no no - -
LPC2917/19/01 - - - - -
LPC2927/29 yes no yes - -
LPC2930 no yes yes yes yes
LPC2939 no yes yes yes yes

2. Introduction
This chapter describes the OTG and I2C portions of the USB 2.0 OTG dual role device
controller which integrates the (OHCI) host controller, device controller, and I2C. The I2C
interface (Master only) controls an external OTG transceiver.

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals. The specification and more information on USB OTG can
be found on the USB Implementers Forum web site.

3. Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and SRP.
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.

4. Architecture
The architecture of the USB OTG controller is shown below in the block diagram.

The host, device, OTG, and I2C controllers can be programmed through the register
interface. The OTG controller enables dynamic switching between host and device roles
through the HNP protocol. One port may be connected to an external OTG transceiver to
support an OTG connection. The communication between the register interface and an
external OTG transceiver is handled through an I2C interface and through the external
OTG transceiver interrupt signal.

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For USB connections that use the device or host controller only (not OTG), the ports use

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an embedded USB Analog Transceiver (ATX).

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OTG

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TRANSCEIVER

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register I2C
interface CONTROLLER
(AHB slave) REGISTER
USB
INTERFACE
port
OTG
CONTROLLER USB
ATX
ATX
CONTROL
AHB bus

DMA interface DEVICE LOGIC/

(AHB master) BUS CONTROLLER PORT
MASTER MUX
INTERFACE
HOST
CONTROLLER

USB OTG BLOCK

EP_RAM

Fig 48. USB OTG controller block diagram

5. Pin configuration
See Table 15–184 for port configurations for the different LPC29xx parts.

Table 185. USB OTG port pins

Pin name Direction Description Interfacing
Port 1
USB_VBUS1 I VBUS status input. When this function is not enabled -
via its corresponding SFSP register, it is driven HIGH
internally.<tbd>
USB_D+1 I/O Positive differential data -
USB_D−1 I/O Negative differential data -
USB_CONNECT1 O SoftConnect control signal -
USB_UP_LED1 O GoodLink LED control signal -
USB_SCL1 I/O I2C serial clock External OTG transceiver
USB_SDA1 I/O I2C serial data External OTG transceiver
USB_LS1 O Low speed status (applies to host functionality only) External OTG transceiver
USB_RST1 O USB reset status External OTG transceiver
USB_INT1 O USB transceiver interrupt External OTG transceiver
USB_SSPND1 O Bus suspend status External OTG transceiver
USB_PWRD1 I Port power status USB host
USB_PPWR1 O Port power enable USB host

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Table 185. USB OTG port pins

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Pin name Direction Description Interfacing

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USB_OVRCR1 I Over-current status USB host

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A
A

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Port 2

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USB_VBUS2 I VBUS status input. When this function is not enabled -

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via its corresponding SFSP register, it is driven HIGH

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internally. <tbd>

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USB_D+2 I/O Positive differential data -
USB_D−2 I/O Negative differential data -
USB_CONNECT2 O SoftConnect control signal -
USB_UP_LED2 O GoodLink LED control signal -
USB_PWRD2 I Port power status USB host
USB_PPWR2 O Port power enable USB host
USB_OVRCR2 I Over-current status USB host

The following figures show different ways to realize connections to an USB device. The
example described here uses an ISP1302 (NXP) for the external OTG transceiver and the
USB Host power switch LM3526-L (National Semiconductors).

Remark: To select the USB functions, see the SPSP registers in Table 6–58, Table 6–59,
and Table 6–60. For input only pins (e.g. USB_OVRCR), select PAD_TYPE in the
corresponding SFSP register to digital input without pullup or pulldown enabled.

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5.1 Suggested USB interface solutions

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VDD(IO)

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R1 R2 R3 R4

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USB_RST1 RESET_N VBUS

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ADR/PSW ID
OE_N/INT_N DP 33 Ω
VDD(IO) Mini-AB
SPEED 33 Ω connector
DM
SUSPEND ISP1302
R4 R5 R6 VSS(IO),
USB_SCL1 SCL VSS(CORE)
USB_SDA1 SDA
USB_INT1 INT_N

USB_D+1
USB_D−1

VDD(IO)
USB_UP_LED1 R7

LPC293X 5V VDD(IO)
IN
OUTA
LM3526-L
USB_PPWR2 ENA
FLAGA
USB_OVRCR2

USB_PWRD2 VBUS

USB_D+2 33 Ω D+
USB-A
USB_D−2 33 Ω D− connector

VSS(IO),
15 kΩ 15 kΩ
VSS(CORE)

VDD(IO)
USB_UP_LED2 R8

002aae261

Fig 49. LPC29xx USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host

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VDD(IO)

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USB_UP_LED1

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VSS(IO),

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VSS(CORE)

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USB_D+1 33 Ω D+

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USB_D−1 33 Ω D−

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USB-A

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15 kΩ 15 kΩ connector
VDD(IO)
USB_PWRD1 VBUS

USB_OVRCR1

USB_PPWR1 ENA FLAGA

5V OUTA VDD(IO)
IN
LM3526-L OUTB
LPC293X
USB_PPWR2 ENB
FLAGB
USB_OVRCR2

USB_PWRD2 VBUS

USB_D+2 33 Ω D+ USB-A
connector
USB_D−2 33 Ω D−

15 kΩ 15 kΩ VSS(IO),
VSS(CORE)

VDD(IO)
USB_UP_LED2

002aae262

Fig 50. LPC29xx USB OTG port configuration: USB port 1 host, USB port 2 host

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VDD(IO)

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USB_UP_LED1

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VSS(IO),

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VSS(CORE)

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USB_D+1 33 Ω D+

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USB_D−1 33 Ω D−

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USB-A

R
connector

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15 kΩ 15 kΩ
VDD(IO)
USB_PWRD1 VBUS

USB_OVRCR1

USB_PPWR1 ENA FLAGA

5V OUTA
LM3526-L
IN
LPC293X
VDD
USB_UP_LED2

VDD(IO)
USB_CONNECT2

VSS(IO),
VSS(CORE)
USB_D+2 33 Ω D+

33 Ω
USB-B
USB_D−2 D−
connector

USB_VBUS2 VBUS

002aae263

Fig 51. LPC29xx USB OTG port configuration: USB port 2 device, USB port 1 host

6. Register description
The OTG and I2C registers are summarized in the following table.

The Device and Host registers are explained in Table 13–117 and <tbd> in the USB
Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide
and aligned to word address boundaries.

Table 186. USB OTG and I2C register address definitions

Name Address Access Function
Interrupt register
USBIntSt <tbd> R/W USB Interrupt Status
OTG registers
OTGIntSt 0xE010 C100 RO OTG Interrupt Status
OTGIntEn 0xE010 C104 R/W OTG Interrupt Enable
OTGIntSet 0xE010 C108 WO OTG Interrupt Set
OTGIntClr 0xE010 C10C WO OTG Interrupt Clear
OTGStCtrl 0xE010 C110 R/W OTG Status and Control
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Table 186. USB OTG and I2C register address definitions

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Name Address Access Function

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OTGTmr 0xE010 C114 R/W OTG Timer

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I2C registers

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I2C_RX 0xE010 C300 RO I2C Receive

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I2C_TX 0xE010 C300 WO I2C Transmit

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I2C_STS 0xE010 C304 RO I2C Status
I2C_CTL 0xE010 C308 R/W I2C Control
I2C_CLKHI 0xE010 C30C R/W I2C Clock High
I2C_CLKLO 0xE010 C310 WO I2C Clock Low
Clock control registers
OTGClkCtrl 0xE010 CFF4 R/W OTG clock controller
OTGClkSt 0xE010 CFF8 RO OTG clock status

6.1 USB Interrupt Status Register (USBIntSt - <tbd>)

The USB OTG controller has seven interrupt lines. This register allows software to
determine their status with a single read operation.

The interrupt lines are ORed together to a single channel of the vectored interrupt
controller.

Table 187. USB Interrupt Status register - (USBIntSt - address 0xE01F C1) bit description
Bit Symbol Description Reset
Value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read only. 0
3 USB_HOST_INT USB host interrupt line status. This bit is read only. 0
4 USB_ATX_INT External ATX interrupt line status. This bit is read only. 0
5 USB_OTG_INT OTG interrupt line status. This bit is read only. 0
6 USB_I2C_INT I2C module interrupt line status. This bit is read only. 0
7 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
8 USB_NEED_CLK USB need clock indicator. This bit is read only. 1
30:9 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the 1
NVIC does not see the ORed output of the USB interrupt
lines.

6.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)

Bits in this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See Section 15–7 for more information on when these bits are set.
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Table 188. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description

R
R

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A
A

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FT
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F
Bit Symbol Description Reset

D
D
Value

R
R

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A

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0 TMR Timer time-out. 0

D
D
R
1 REMOVE_PU Remove pull-up. 0

A
FT
This bit is set by hardware to indicate that software

D
needs to disable the D+ pull-up resistor.

R
A
2 HNP_FAILURE HNP failed. 0
This bit is set by hardware to indicate that the HNP
switching has failed.
3 HNP_SUCCESS HNP succeeded. 0
This bit is set by hardware to indicate that the HNP
switching has succeeded.
31:4 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.

6.3 OTG Interrupt Enable Register (OTGIntEn - 0xE010 C104)

Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.

The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.

6.4 OTG Interrupt Set Register (OTGIntSet - 0xE010 C20C)

Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.

6.5 OTG Interrupt Clear Register (OTGIntClr - 0xE010 C10C)

Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.

6.6 OTG Status and Control Register (OTGStCtrl - 0xE010 C110)

The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.

Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:

1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section

15–6.7 “OTG Timer Register (OTGTmr - 0xE010 C114)”), the TMR bit is set in
OTGIntSt, and the timer will be disabled.
2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 15–6.7 “OTG Timer Register (OTGTmr - 0xE010 C114)”), the TMR bit is set,
and the timer value is reloaded into the counter. The timer is not disabled in this
mode.
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Table 189. OTG Status Control register (OTGStCtrl - address 0xE010 C110) bit description

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A
A

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FT
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F
Bit Symbol Description Reset

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D
Value

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R

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A

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1:0 PORT_FUNC Controls port function. Bit 0 is set or cleared by hardware -

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when B_HNP_TRACK or A_HNP_TRACK is set and

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HNP succeeds. See Section 15–7. Bit 1 is reserved.

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3:2 TMR_SCALE Timer scale selection. This field determines the duration 0x0

R
A
of each timer count.
00: 10 μs (100 KHz)
01: 100 μs (10 KHz)
10: 1000 μs (1 KHz)
11: Reserved
4 TMR_MODE Timer mode selection. 0
0: monoshot
1: free running
5 TMR_EN Timer enable. When set, TMR_CNT increments. When 0
cleared, TMR_CNT is reset to 0.
6 TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0. 0
This provides a single bit control for the software to
restart the timer when the timer is enabled.
7 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
8 B_HNP_TRACK Enable HNP tracking for B-device (peripheral), see 0
Section 15–7. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
9 A_HNP_TRACK Enable HNP tracking for A-device (host), see 0
Section 15–7. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
10 PU_REMOVED When the B-device changes its role from peripheral to 0
host, software sets this bit when it removes the D+
pull-up, see Section 15–7. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
15:11 - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is not
defined.
31:16 TMR_CNT Current timer count value. 0x0

6.7 OTG Timer Register (OTGTmr - 0xE010 C114)

Table 190. OTG Timer register (OTGTmr - address 0xE010 C114) bit description
Bit Symbol Description Reset
Value
15:0 TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value. 0xFFFF
31:16 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

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6.8 OTG Clock Control Register (OTGClkCtrl - 0xE010 CFF4)

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FT

F
This register controls the clocking of the OTG controller. Whenever software wants to

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access the registers, the corresponding clock control bit needs to be set. The software

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FT
does not have to repeat this exercise for every register access, provided that the

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corresponding OTGClkCtrl bits are already set.

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Table 191. OTG_clock_control register (OTG_clock_control - address 0xE010 CFF4) bit

D
R
A
description
Bit Symbol Value Description Reset
Value
0 HOST_CLK_EN Host clock enable 0
0 Disable the Host clock.
1 Enable the Host clock.
1 DEV_CLK_EN Device clock enable 0
0 Disable the Device clock.
1 Enable the Device clock.
2 I2C_CLK_EN I2C clock enable 0
0 Disable the I2C clock.
1 Enable the I2C clock.
3 OTG_CLK_EN OTG clock enable 0
0 Disable the OTG clock.
1 Enable the OTG clock.
4 AHB_CLK_EN AHB master clock enable 0
0 Disable the AHB clock.
1 Enable the AHB clock.
31:5 - NA Reserved, user software should not write ones NA
to reserved bits. The value read from a
reserved bit is not defined.

6.9 OTG Clock Status Register (OTGClkSt - 0xE010 CFF8)

This register holds the clock availability status. When enabling a clock via OTGClkCtrl,
software should poll the corresponding bit in this register. If it is set, then software can go
ahead with the register access. Software does not have to repeat this exercise for every
access, provided that the OTGClkCtrl bits are not disturbed.

Table 192. OTG_clock_status register (OTGClkSt - address 0xE010 CFF8) bit description
Bit Symbol Value Description Reset
Value
0 HOST_CLK_ON Host clock status. 0
0 Host clock is not available.
1 Host clock is available.
1 DEV_CLK_ON Device clock status. 0
0 Device clock is not available.
1 Device clock is available.

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Table 192. OTG_clock_status register (OTGClkSt - address 0xE010 CFF8) bit description

D
D

D
R
R

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A
A

A
Bit Symbol Value Description Reset

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FT

F
Value

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R
R

A
A
2 I2C_CLK_ON I2C clock status. 0

FT
FT

D
D
0 I2C clock is not available.

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A
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1 I2C clock is available.

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3 OTG_CLK_ON OTG clock status. 0

A
0 OTG clock is not available.
1 OTG clock is available.
4 AHB_CLK_ON AHB master clock status. 0
0 AHB clock is not available.
1 AHB clock is available.
31:5 - NA Reserved, user software should not write ones NA
to reserved bits. The value read from a
reserved bit is not defined.

6.10 I2C Receive Register (I2C_RX - 0xE010 C300)

This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx
FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO
gives unpredictable data results.

Table 193. I2C Receive register (I2C_RX - address 0xE010 C300) bit description
Bit Symbol Description Reset
Value
7:0 RX Data Receive data. -

6.11 I2C Transmit Register (I2C_TX - 0xE010 C300)

This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.

The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.

I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]
are ignored for master-receive operations. The master-receiver must write a dummy byte
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is
set or the START bit is set to cause a RESTART condition on a byte written to the TX
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,
the last byte of a master-receive operation is not acknowledged.

Table 194. I2C Transmit register (I2C_TX - address 0xE010 C300) bit description
Bit Symbol Description Reset
Value
7:0 TX Data Transmit data. -
8 START When 1, issue a START condition before transmitting this byte. -
9 STOP When 1, issue a STOP condition after transmitting this byte. -
31:10 - Reserved. User software should not write ones to reserved bits. The -
value read from a reserved bit is not defined.

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6.12 I2C Status Register (I2C_STS - 0xE010 C304)

D
D

D
R
R

R
A
A

A
FT
FT

F
The I2C_STS register provides status information on the TX and RX blocks as well as the

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R
current state of the external buses. Individual bits are enabled as interrupts by the

A
A

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FT
I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.

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D
R
A
Table 195. I2C status register (I2C_STS - address 0xE010 C304) bit description

FT
D
Bit Symbol Value Description Reset

R
A
Value
0 TDI Transaction Done Interrupt. This flag is set if a transaction 0
completes successfully. It is cleared by writing a one to bit 0 of
the status register. It is unaffected by slave transactions.
0 Transaction has not completed.
1 Transaction completed.
1 AFI Arbitration Failure Interrupt. When transmitting, if the SDA is low 0
when SDAOUT is high, then this I2C has lost the arbitration to
another device on the bus. The Arbitration Failure bit is set when
this happens. It is cleared by writing a one to bit 1 of the status
register.
0 No arbitration failure on last transmission.
1 Arbitration failure occurred on last transmission.
2 NAI No Acknowledge Interrupt. After every byte of data is sent, the 0
transmitter expects an acknowledge from the receiver. This bit is
set if the acknowledge is not received. It is cleared when a byte
is written to the master TX FIFO.
0 Last transmission received an acknowledge.
1 Last transmission did not receive an acknowledge.
3 DRMI Master Data Request Interrupt. Once a transmission is started, 0
the transmitter must have data to transmit as long as it isn’t
followed by a stop condition or it will hold SCL low until more
data is available. The Master Data Request bit is set when the
master transmitter is data-starved. If the master TX FIFO is
empty and the last byte did not have a STOP condition flag, then
SCL is held low until the CPU writes another byte to transmit.
This bit is cleared when a byte is written to the master TX FIFO.
0 Master transmitter does not need data.
1 Master transmitter needs data.
4 DRSI Slave Data Request Interrupt. Once a transmission is started, 0
the transmitter must have data to transmit as long as it isn’t
followed by a STOP condition or it will hold SCL low until more
data is available. The Slave Data Request bit is set when the
slave transmitter is data-starved. If the slave TX FIFO is empty
and the last byte transmitted was acknowledged, then SCL is
held low until the CPU writes another byte to transmit. This bit is
cleared when a byte is written to the slave Tx FIFO.
0 Slave transmitter does not need data.
1 Slave transmitter needs data.
5 Active Indicates whether the bus is busy. This bit is set when a START 0
condition has been seen. It is cleared when a STOP condition is
seen..
6 SCL The current value of the SCL signal. -

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Table 195. I2C status register (I2C_STS - address 0xE010 C304) bit description

D
D

D
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R

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A
A

A
Bit Symbol Value Description Reset

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FT

F
Value

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D

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R

A
A
7 SDA The current value of the SDA signal. -

FT
FT

D
D
8 RFF Receive FIFO Full (RFF). This bit is set when the RX FIFO is full 0

R
A
and cannot accept any more data. It is cleared when the RX

FT
FIFO is not full. If a byte arrives when the Receive FIFO is full,

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A
the SCL is held low until the CPU reads the RX FIFO and makes
room for it.
0 RX FIFO is not full
1 RX FIFO is full
9 RFE Receive FIFO Empty. RFE is set when the RX FIFO is empty 1
and is cleared when the RX FIFO contains valid data.
0 RX FIFO contains data.
1 RX FIFO is empty
10 TFF Transmit FIFO Full. TFF is set when the TX FIFO is full and is 0
cleared when the TX FIFO is not full.
0 TX FIFO is not full.
1 TX FIFO is full
11 TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty 1
and is cleared when the TX FIFO contains valid data.
0 TX FIFO contains valid data.
1 TX FIFO is empty
31:12 - NA Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

6.13 I2C Control Register (I2C_CTL - 0xE010 C308)

The I2C_CTL register is used to enable interrupts and reset the I2C state machine.
Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set.

Table 196. I2C Control register (I2C_CTL - address 0xE010 C308) bit description
Bit Symbol Value Description Reset
Value
0 TDIE Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C 0
issued a STOP condition.
0 Disable the TDI interrupt.
1 Enable the TDI interrupt.
1 AFIE Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is 0
asserted during transmission when trying to set SDA high, but the bus is driven low by
another device.
0 Disable the AFI.
1 Enable the AFI.
2 NAIE Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling 0
that transmitted byte was not acknowledged.
0 Disable the NAI.
1 Enable the NAI.

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Table 196. I2C Control register (I2C_CTL - address 0xE010 C308) bit description

D
D

D
R
R

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A
A

A
Bit Symbol Value Description Reset

FT
FT

F
Value

D
D

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R

A
A
3 DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which 0

FT
FT

D
signals that the master transmitter has run out of data, has not issued a STOP, and is

D
R
A
holding the SCL line low.

FT
0 Disable the DRMI interrupt.

D
R
A
1 Enable the DRMI interrupt.
4 DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which 0
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
0 Disable the DRSI interrupt.
1 Enable the DRSI interrupt.
5 REFIE Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to 0
indicate that the receive FIFO cannot accept any more data.
0 Disable the RFFI.
1 Enable the RFFI.
6 RFDAIE Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that 0
data is available in the receive FIFO (i.e. not empty).
0 Disable the DAI.
1 Enable the DAI.
7 TFFIE Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt 0
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I2C block only when there is room in the FIFO
and do this without polling the status register.
0 Disable the TFFI.
1 Enable the TFFI.
8 SRST Soft reset. This is only needed in unusual circumstances. If a device issues a start 0
condition without issuing a stop condition. A system timer may be used to reset the I2C if
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
0 See the text.
1 Reset the I2C to idle state. Self clearing.
31:9 - NA Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

6.14 I2C Clock High Register (I2C_CLKHI - 0xE010 C30C)

The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
high period of the slower I2C serial clock, SCL.

Table 197. I2C_CLKHI register (I2C_CLKHI - address 0xE010 C30C) bit description
Bit Symbol Description Reset
Value
7:0 CDHI Clock divisor high. This value is the number of 48 MHz 0xB9
clocks the serial clock (SCL) will be high.

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6.15 I2C Clock Low Register (I2C_CLKLO - 0xE010 C310)

D
D

D
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R

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A
A

A
FT
FT

F
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the

D
D
low period of the slower I2C serial clock, SCL.

R
R

A
A

FT
FT

D
D
Table 198. I2C_CLKLO register (I2C_CLKLO - address 0xE010 C310) bit description

R
A
Bit Symbol Description Reset

FT
D
Value

R
A
7:0 CDLO Clock divisor low. This value is the number of 48 MHz 0xB9
clocks the serial clock (SCL) will be low.

6.16 Interrupt handling

The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All
OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt
register.

I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL,
to the USB_I2C_INT bit.

For more details on the interrupts created by device controller, see the USB device
chapter. For interrupts created by the host controllers, see the OHCI specification.

The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB
related interrupts to the NVIC controller (see Figure 15–52).

Remark: During the HNP switching between host and device with the OTG stack active,
an action may raise several levels of interrupts. It is advised to let the OTG stack initiate
any actions based on interrupts and ignore device and host level interrupts. This means
that during HNP switching, the OTG stack provides the communication to the host and
device controllers.

USBIntSt
USB_INT_REQ_HP
USB DEVICE USB_INT_REQ_LP
INTERRUPTS to NVIC
USB_INT_REQ_DMA
USB_HOST_INT
USB_OTG_INT
USB HOST
INTERRUPTS USB_I2C_INT

OTGIntSt
TMR
REMOVE_PU
HNP_SUCCESS
HNP_FAILURE
USB_NEED_CLOCK

USB I2C EN_USB_INTS

INTERRUPTS

Fig 52. USB OTG interrupt handling

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7. HNP support

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F
D
D
This section describes the hardware support for the Host Negotiation Protocol (HNP)

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A
A

FT
provided by the OTG controller.

FT

D
D
R
A
When two dual-role OTG devices are connected to each other, the plug inserted into the

FT
mini-AB receptacle determines the default role of each device. The device with the mini-A

D
R
plug inserted becomes the default Host (A-device), and the device with the mini-B plug

A
inserted becomes the default Peripheral (B-device).

Once connected, the default Host (A-device) and the default Peripheral (B-device) can
switch Host and Peripheral roles using HNP.

The context of the OTG controller operation is shown in Figure 15–53. Each controller
(Host, Device, or OTG) communicates with its software stack through a set of status and
control registers and interrupts. In addition, the OTG software stack communicates with
the external OTG transceiver through the I2C interface and the external transceiver
interrupt signal.

The OTG software stack is responsible for implementing the HNP state machines as
described in the On-The-Go Supplement to the USB 2.0 Specification.

The OTG controller hardware provides support for some of the state transitions in the
HNP state machines as described in the following subsections.

The USB state machines, the HNP switching, and the communications between the USB
controllers are described in more detail in the following documentation:

• USB OHCI specification

• USB OTG supplement, version 1.2
• USB 2.0 specification
• ISP1301 datasheet and usermanual

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OHCI HOST

D
D
STACK CONTROLLER

R
A
FT
D
R
A
OTG USB BUS
OTG MUX
CONTROLLER
STACK

DEVICE DEVICE
STACK CONTROLLER

I2C
CONTROLLER ISP1301

Fig 53. USB OTG controller with software stack

7.1 B-device: peripheral to host switching

In this case, the default role of the OTG controller is peripheral (B-device), and it switches
roles from Peripheral to Host.

The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role B-Device State Diagram.

The OTG controller hardware provides support for the state transitions between the states
b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting
B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device
switching from peripheral to host. The hardware actions after setting this bit are shown in
Figure 15–54.

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idle

D
B_HNP_TRACK = 0

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A

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FT

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D
R
no

A
B_HNP_TRACK = 1 ?

FT
D
set HNP_FAILURE,

R
clear B_HNP_TRACK,

A
clear PU_REMOVED
no
bus suspended ?

no
disconnect device controller from U1 PU_REMOVED set?
set REMOVE_PU

yes
PU_REMOVED set?
reconnect port U1 to the
device controller

yes
bus reset/resume detected?

no

reconnect port U1 to the

device controller

wait 25 μs for bus to settle

yes yes
connect from A-device detected? bus reset/resume detected?

no no

set HNP_SUCCESS yes

set PORT_FUNC[0] connect U1 to host controller
SE0 sent by host? clear B_HNP_TRACK
drive J on internal host controller port
and SE0 on U1 clear PU_REMOVED
no

Fig 54. Hardware support for B-device switching from peripheral state to host state

Figure 15–55 shows the actions that the OTG software stack should take in response to
the hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The
relationship of the software actions to the Dual-Role B-Device states is also shown.
B-device states are in bold font with a circle around them.

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F
b_peripheral

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D

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A
A
when host sends SET_FEATURE

FT
FT
with b_hnp_enable,

D
D
set B_HNP_TRACK

R
A
FT
D
R
A
no
REMOVE_PU set?

yes

remove D+ pull-up,
set PU_REMOVED

go to go to
b_wait_acon b_peripheral

yes
HNP_FAILURE set? add D+ pull-up

no

no
HNP_SUCCESS set?

yes

go to

b_host

Fig 55. State transitions implemented in software during B-device switching from peripheral to host

Note that only the subset of B-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.

Figure 15–55 may appear to imply that the interrupt bits such as REMOVE_PU should be
polled, but this is not necessary if the corresponding interrupt is enabled.

Following are code examples that show how the actions in Figure 15–55 are
accomplished. The examples assume that ISP1301 is being used as the external OTG
transceiver.

Remove D+ pull-up

/* Remove D+ pull-up through ISP1301 */

OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0
OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address
OTG_I2C_TX = 0x201; // Clear DP_PULLUP bit, send STOP condition
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/* Wait for TDI to be set */

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while (!(OTG_I2C_STS & TDI));

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/* Clear TDI */

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OTG_I2C_STS = TDI;

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Add D+ pull-up

A
/* Add D+ pull-up through ISP1301 */
OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0
OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address
OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS & TDI));

/* Clear TDI */
OTG_I2C_STS = TDI;

7.2 A-device: host to peripheral HNP switching

In this case, the role of the OTG controller is host (A-device), and the A-device switches
roles from host to peripheral.

The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role A-Device State Diagram.

The OTG controller hardware provides support for the state transitions between a_host,
a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram.
Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching
the A-device from the host state to the device state. The hardware actions after setting
this bit are shown in Figure 15–56.

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A_HNP_TRACK = 0

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no

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A_HNP_TRACK = 1 ? set HNP_FAILURE,

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clear A_HNP_TRACK

A
disconnect host controller from U1

no no
bus suspended ? resume detected ?

yes yes connnect host controller back to U1

yes yes
bus reset detected? resume detected?

no no

no OTG timer expired?

(TMR =1 )

yes

clear A_HNP_TRACK
set HNP_SUCCESS
connect device to U1 by clearing
PORT_FUNC[0]

Fig 56. Hardware support for A-device switching from host state to peripheral state

Figure 15–57 shows the actions that the OTG software stack should take in response to
the hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The
relationship of the software actions to the Dual-Role A-Device states is also shown.
A-device states are shown in bold font with a circle around them.

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a_host

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when host sends SET_FEATURE

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with a_hnp_enable,

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set A_HNP_TRACK

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FT
D
R
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set BDIS_ACON_EN
in external OTG transceiver

load and enable OTG timer

suspend host on port 1

go to

a_suspend

no
no no
TMR set? HNP_SUCCESS set? HNP_FAILURE set?

yes yes
yes
clear BDIS_ACON_EN
stop the OTG timer stop OTG timer
bit in external OTG transceiver
discharge VBUS

go to
clear BDIS_ACON_EN
a_peripheral bit in external OTG transceiver

go to

a_wait_vfall go to

a_host

Fig 57. State transitions implemented in software during A-device switching from host to peripheral

Note that only the subset of A-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.

Figure 15–57 may appear to imply that the interrupt bits such as TMR should be polled,
but this is not necessary if the corresponding interrupt is enabled.

Following are code examples that show how the actions in Figure 15–57 are
accomplished. The examples assume that ISP1301 is being used as the external OTG
transceiver.

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Set BDIS_ACON_EN in external OTG transceiver

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/* Set BDIS_ACON_EN in ISP1301 */

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OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0

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A

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OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address

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OTG_I2C_TX = 0x210; // Set BDIS_ACON_EN bit, send STOP condition

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D
R
/* Wait for TDI to be set */

A
while (!(OTG_I2C_STS & TDI));

/* Clear TDI */
OTG_I2C_STS = TDI;

Clear BDIS_ACON_EN in external OTG transceiver

/* Set BDIS_ACON_EN in ISP1301 */

OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0
OTG_I2C_TX = 0x005; // Send Mode Control 1 (Clear) register address
OTG_I2C_TX = 0x210; // Clear BDIS_ACON_EN bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS & TDI));

/* Clear TDI */
OTG_I2C_STS = TDI;

Discharge VBUS

/* Clear the VBUS_DRV bit in ISP1301 */

OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0
OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address
OTG_I2C_TX = 0x220; // Clear VBUS_DRV bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS & TDI));

/* Clear TDI */
OTG_I2C_STS = TDI;

/* Set the VBUS_DISCHRG bit in ISP1301 */

OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0
OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address
OTG_I2C_TX = 0x240; // Set VBUS_DISCHRG bit, send STOP condition

/* Wait for TDI to be set */

while (!(OTG_I2C_STS & TDI));

/* Clear TDI */
OTG_I2C_STS = TDI;

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Load and enable OTG timer

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/* The following assumes that the OTG timer has previously been */

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/* configured for a time scale of 1 ms (TMR_SCALE = “10”) */

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/* and monoshot mode (TMR_MODE = 0) */

R
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FT
D
/* Load the timeout value to implement the a_aidl_bdis_tmr timer */

R
A
/* the minimum value is 200 ms */
OTG_TIMER = 200;

/* Enable the timer */

OTG_STAT_CTRL |= TMR_EN;

Stop OTG timer

/* Disable the timer – causes TMR_CNT to be reset to 0 */

OTG_STAT_CTRL &= ~TMR_EN;

/* Clear TMR interrupt */

OTG_INT_CLR = TMR;

Suspend host on port 1

/* Write to PortSuspendStatus bit to suspend host port 1 – */

/* this example demonstrates the low-level action software needs to take. */
/* The host stack code where this is done will be somewhat more involved. */
HC_RH_PORT_STAT1 = PSS;

8. Clocking and power management

The OTG controller clocking is shown in Figure 15–58. Note that the host controller is not
implemented on the LPC2927 and LPC2929.

A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.

To conserve power, the clocks to the Device, host, OTG, and I2C controllers can be
disabled when not in use by disabling the clocks in the CGU1 (see Table 3–14).

When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.

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cclk ahb_slave_clk REGISTER

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PCUSB

R
INTERFACE

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FT

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D
R
A
ahb_master_clk

FT
CLOCK

D
SWITCH

R
EN

A
AHB_CLK_ON
ahb_need_clk

AHB_CLK_EN
CLOCK dev_dma_need_clk
USB CLOCK SWITCH DEVICE
DIVIDER usbclk EN CONTROLLER dev_need_clk
DEV_CLK_ON
(48 MHz)
DEV_CLK_EN

CLOCK host_dma_need_clk
SWITCH HOST
EN CONTROLLER host_need_clk
HOST_CLK_ON

HOST_CLK_EN

CLOCK
SWITCH OTG USB_NEED_CLK
CONTROLLER
EN OTG_CLK_ON

OTG_CLK_EN

CLOCK
I2C
SWITCH
CONTROLLER
EN I2C_CLK_ON

I2C_CLK_EN

Fig 58. Clocking and power control

8.1 Device clock request signals

The Device controller has two clock request signals, dev_need_clk and
dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and
ahb_master_clk respectively.

The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register). This signal allows DEV_CLK_EN to be cleared during normal operation
when software does not need to access the Device controller registers – the Device will
continue to function normally and automatically shut off its clock when it is suspended or
disconnected.
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The dev_dma_need_clk signal is asserted on any Device controller DMA access to

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memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA

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throughput is not affected by any latency associated with re-enabling ahb_master_clk.

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2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve

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power. This signal allows AHB_CLK_EN to be cleared during normal operation.

D
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8.2 Clocking and power management

D
R
A
The OTG controller clocking is shown in Figure 15–58.

A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.

To conserve power, the clocks to the Device, Host, OTG, and I2C controllers can be
disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl
register. When the entire USB block is not in use, all of its clocks can be disabled by
clearing the PCUSB bit in the PCONP register.

When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.

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cclk ahb_slave_clk REGISTER

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PCUSB

R
INTERFACE

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FT

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D
R
A
ahb_master_clk

FT
CLOCK

D
SWITCH

R
EN

A
AHB_CLK_ON
ahb_need_clk

AHB_CLK_EN
CLOCK dev_dma_need_clk
USB CLOCK SWITCH DEVICE
DIVIDER usbclk EN CONTROLLER dev_need_clk
DEV_CLK_ON
(48 MHz)
DEV_CLK_EN

CLOCK host_dma_need_clk
SWITCH HOST
EN CONTROLLER host_need_clk
HOST_CLK_ON

HOST_CLK_EN

CLOCK
SWITCH OTG USB_NEED_CLK
CONTROLLER
EN OTG_CLK_ON

OTG_CLK_EN

CLOCK
I2C
SWITCH
CONTROLLER
EN I2C_CLK_ON

I2C_CLK_EN

Fig 59. Clocking and power control

8.2.1 Device clock request signals

The Device controller has two clock request signals, dev_need_clk and
dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and
ahb_master_clk respectively.

The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register – Section 13–11.7). This signal allows DEV_CLK_EN to be cleared during
normal operation when software does not need to access the Device controller registers –
the Device will continue to function normally and automatically shut off its clock when it is
suspended or disconnected.

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The dev_dma_need_clk signal is asserted on any Device controller DMA access to

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memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA

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throughput is not affected by any latency associated with re-enabling ahb_master_clk.

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2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve

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power. This signal allows AHB_CLK_EN to be cleared during normal operation.

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8.2.1.1 Host clock request signals

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The Host controller has two clock request signals, host_need_clk and
host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and
ahb_master_clk respectively.

The host_need_clk signal is asserted while the Host controller functional state is not
UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a
disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared
during normal operation when software does not need to access the Host controller
registers – the Host will continue to function normally and automatically shut off its clock
when it goes into the UsbSuspend state.

The host_dma_need_clk signal is asserted on any Host controller DMA access to

memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA
throughput is not affected by any latency associated with re-enabling ahb_master_clk.
2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve
power. This signal allows AHB_CLK_EN to be cleared during normal operation.

8.2.2 Power-down mode support

<tbd>

Before Power-down mode can be entered when USBWAKE is set, USB_NEED_CLK

must be de-asserted. This is accomplished by clearing all of the CLK_EN bits in
OTGClkCtrl and putting the Host controller into the UsbSuspend functional state. If it is
necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be
de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to
determine when they have all been de-asserted.

9. USB OTG controller initialization

The LPC29xx OTG device controller initialization includes the following steps:

1. Enable the USB device block through the PMU, <tbd>.

2. Configure and enable the USB PLL in the CGU1, see Table 3–14.
3. Enable the desired controller clocks by setting their respective CLK_EN bits in the
USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register
until they are set.
4. Enable the desired USB pin functions by writing to the corresponding port control
registers, see Table 6–57.
5. Follow the appropriate steps in Section 13–12 “USB device controller initialization” to
initialize the device controller.

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Rev. 00.06 — 17 December 2008 User manual

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. Available ports depend on the pin

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configuration for each part.

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Table 199. GPIO ports available
Part number GPIO GPIO GPIO GPIO GPIO GPIO GPIO port 5/
port 0 port 1 port 2 port 3 port 4 port 5 USB
LPC2917/19/01 P0[31:0] P1[31:0] P2[27:0] P3[15:0] - - -
LPC2921/23/25 P0[31:0] P1[27:0] - - - - P5[19:18]
LPC2927/29 P0[31:0] P1[27:0] P2[27:0] P3[15:0] - - P5[19:18]
LPC2930 P0[31:0] P1[27:0] P2[27:0] P3[15:0] P4[23:0] P5[15:0] P5[19:16]
LPC2939 P0[31:0] P1[27:0] P2[27:0] P3[15:0] P4[23:0] P5[15:0] P5[19:16]

2. GPIO functional description

function select

GPIO n
GPIO 1
I/O pins
GPIO 0 ARM
(GPIO)

Fig 60. Schematic representation of the GPIO

Each General-Purpose I/O block GPIO provides control over up to 32 port pins. The data
direction (in/out) and output level of each port pin can be programmed individually.

If a port pin is to be used it must first be routed to an I/O pin so that it is available
externally. This part of the configuration is done via the SCU. See Section 6–3.1 for
information on mapping of GPIO port pins to I/O pins. GPIO port pinning can be found in
Ref. 32–1.

A number of points should be noted in regard to SCU mapping of GPIO pins:

• If an input port is not mapped through the SCU to an external I/O pin it is assigned a
logical 0.
• If an output port is not mapped through the SCU to an external I/O pin it is left
dangling; i.e. not connected.

The GPIO pins can also be used in an open-drain configuration. In this configuration,
multiple devices can communicate on one signal line in any direction (e.g. bi-directionally).

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The signal line is normally pulled up to a HIGH voltage level (logic 1) by an external

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resistor. Each of the devices connected to the signal line can either drive the signal line to

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a LOW voltage level (logic 0) or stay at high impedance (open-drain). If none of the

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devices drives the signal line to a LOW voltage level the signal line is pulled-up by the

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resistor (logic 1).

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Devices in high-impedance can also read the value of the signal line to detect a logic 0 or

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logic 1. This allows communication in multiple directions.

A
The open-drain configuration is achieved by:

• Initially:
– Configuring the pin direction as input (high impedance/open drain).
– Setting the pin output to a LOW voltage level (logic 0).
• Configuring the pin direction as output to drive a LOW voltage level (logic 0).
• Configuring the pin direction as input to provide an open drain. In this case the other
devices and external resistor determine the voltage level. The actual level (logic 0 or
logic 1) can be read from the GPIO pin.

3. GPIO register overview

The General-Purpose I/O registers have an offset to the base address GPIO RegBase
which can be found in the memory map, see Section 2–2.

The general purpose I/O registers are shown in Table 16–200.

Table 200. General purpose I/O register overview (base address: E004 A000h (GPIO0), E004
B000h (GPIO1), E004 C000h (GPIO2), E004 D000h (GPIO3), 0xE004 E000h (GPIO4),
E004 F000h (GPIO5))
Address Access Reset value Name Description Reference
offset
0h R - PINS Port input register see
Table 16–201
4h R/W 0000 0000h OR Port output register see
Table 16–202
8h R/W 0000 0000h DR Port direction register see
Table 16–203

3.1 GPIO port input register

The port input register is used to reflect the synchronized input level on each I/O pin
individually. In the case of writing to the port input register, the contents are written into the
port output register.

Table 16–201 shows the bit assignment of the PINS register. Bits for for unavailable ports
are reserved (see Table 16–199), do not modify, and read as logic 0.

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Table 201. PINS register bit description (PINS0 to 5, addresses 0xE004 A000 (GPIO0), 0xE004

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B000 (GPIO1), 0xE004 C000 (GPIO2), 0xE004 D000 (GPIO3), 0xE004 E000 (GPIO4),

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0xE004 F000 (GPIO5))

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Bit Symbol Access Value Description

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31 PINS[31] R/W 1 Pn[31] input pin is HIGH

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0 Pn[31] input pin is LOW

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: : : : :

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0 PINS[0] R/W 1 Pn[0] input pin is HIGH
0 Pn[0] input pin is LOW

3.2 GPIO port output register

The port output register is used to define the output level on each I/O pin individually if this
pin has been configured as an output by the port direction register. If the port input register
is written to the port output register is written to as well.

Table 16–202 shows the bit assignment of the OR register. Bits for for unavailable ports
are reserved (see Table 16–199), do not modify, and read as logic 0.

Table 202. OR register bit description (OR0 to 5, addresses 0xE004 A004 (GPIO0), 0xE004
B004 (GPIO1), 0xE004 C004 (GPIO2), 0xE004 D004 (GPIO3), 0xE004 E004 (GPIO4),
0xE004 F004 (GPIO5))
* = reset value
Bit Symbol Access Value Description
31 OR[31] R/W 1 If configured as an output, pin Pn[31] is driven
HIGH
0* If configured as an output, pin Pn[31] is driven
LOW
: : : : :
0 OR[0] R/W 1 If configured as an output, pin Pn[0] is driven
HIGH
0* If configured as an output, pin Pn[0] is driven
LOW

3.3 GPIO port direction register

The port direction register is used to individually control each I/O pin output-driver enable.
If the port is configured as input, see Table 6–58 to configure the appropriate pad type.

Table 16–203 shows the bit assignment of the DR register. Bits for for unavailable ports
are reserved (see Table 16–199), do not modify, and read as logic 0.

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Table 203. DR register bit description (DR0 to 5, addresses 0xE004 A008 (GPIO0), 0xE004

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B008 (GPIO1), 0xE004 C008 (GPIO2), 0xE004 D008 (GPIO3), 0xE004 E008 (GPIO4),

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0xE004 F008 (GPIO5))

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* = reset value

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Bit Symbol Access Value Description

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31 DR[31] R/W 1 Pin Pn[31] is configured as an output

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0* Pin Pn[31] is configured as an input

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: : : : :
0 DR[0] R/W 1 Pin Pn[0] is configured as an output
0* Pin Pn[0] is configured as an input

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. Note that capture pins CAP0 and

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CAP1 on timer 1 are not pinned out for LPC2927/29 and LPC2921/23/25.

A
2. Timer functional description
The timers can be used to measure the time between events. An interrupt can be
generated:

• When a predetermined period has elapsed (match functionality: see section

Section 17–4)
• On an external trigger (capture functionality: see section Section 17–4.1)

Capture
Event[x]

CAPTURE
PRESCALE VALUE[x]
VALUE

Timer
System Interrupt
Clock PRESCALE TIMER
COUNTER COUNTER

MATCH
VALUE[x]

Fig 61. Timer architecture

The timer runs at a frequency derived from the input system clock by dividing it by the
prescale value. The prescale value is programmed by writing to the PR register.

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3. Timer counter and interrupt timing

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Each timer consists of a prescale counter (PR register) and a timer counter (TC register).

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The prescale counter is incremented at every cycle of the system clock. As soon as the

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prescale counter matches the prescale value contained in the PV register it is reset to 0

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and the timer counter is incremented. Both events occur at the next system clock cycle, so

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effectively the timer counter is incremented at every prescale-value+1 cycle of the system

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clock.

When the timer counter equals a match value (MRx registers) the timer performs the
configured match action (MCR register). For a reset on match the timer counter is reset at
the next prescaled clock (see Figure 17–62): for a stop-on-match the prescale and timer
counters stop immediately (see Figure 17–63).

If interrupts are enabled and an interrupt condition occurs (match value reached or
capture event received) the timer generates an interrupt. This interrupt is generated at the
next system clock cycle (see Figure 17–62 and Figure 17–63).

CLK(SYS)

Prescale 2 0 1 2 0 1 2 0 1 2 0 1
Counter (PC)

Timer 4 5 6 0 1
Counter (TC)
Timer Counter (TC)
reached
Timer Interrupt Match Value (MRx=6)
(active low)

PR=2, MRx=6
Fig 62. Reset-on-match timing

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CLK(SYS)

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Prescale 2 0 1 2 0

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Counter (PC)

Timer 4 5 6
Counter (TC)
Timer Counter (TC)
reached
Timer Interrupt Match Value (MRx=6)
(active low)

PR=2, MRx=6
Fig 63. Stop-on-match timing

4. Timer match functionality

The timer block contains four match circuits, each of which can be programmed with an
individual match value and a specific action-on-match. Once the counter value matches
one of the programmed match values in the MR# register one or more of the following
actions can occur (selected by programming the MCR register):

• Reset the counter and prescaler

• Stop the counter
• Generate an interrupt
• Generate an external notification (in this case, on a match the external match pins go
to the setting selected via the EMR register).

4.1 Timer capture functionality

The timer block contains four capture circuits. The capture functionality allows measuring
the time of an external event. Depending on configuration, a rising or a falling edge of the
input can cause a capture event. Following an event the capture register is loaded with
the Timer Counter value and (if enabled) an interrupt is generated.

The trigger for the capture and whether an interrupt should be generated on match is
configured using the CCR register. The captured value is then available in the Capture
register (CR#).

4.2 Timer interrupt handling

Once the interrupt is generated its status can be accessed and cleared using the IR
register. See Section 17–4 and Section 17–4.1 for details of how to set up interrupt
generation.

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5. Timer register overview

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The timer registers are shown in table Table 17–204. They have an offset to the base

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address TMR RegBase which can be found in the memory map, see Section 2–2. The

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timers in the MSCSS have an offset to the base address MTMR RegBase.

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Table 204. Timer register overview (base address: E004 1000h (timer 0), E004 2000h (timer 1), E004 3000h (timer 2),

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E004 4000h (timer 3), E00C 0000h (MSCSS timer 0, E00C1000h (MSCSS timer 1))

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Address Access Reset value Name Description Reference
offset
000h R/W 0h TCR Timer control register see
Table 17–205
004h R/W 0000 0000h TC Timer counter value see
Table 20–253
008h R/W 0000 0000h PR Prescale register see
Table 20–254
00Ch R/W 000h MCR Match-control register see
Table 17–208
010h R/W 000h EMR External-match register see
Table 17–209
014h R/W 0000 0000h MR0 Match register 0 see
Table 17–210
018h R/W 0000 0000h MR1 Match register 1 see
Table 17–210
01Ch R/W 0000 0000h MR2 Match register 2 see
Table 17–210
020h R/W 0000 0000h MR3 Match register 3 see
Table 17–210
024h R/W 000h CCR Capture control register see
Table 17–211
028h R 0000 0000h CR0 Capture register 0 see
Table 17–212
02Ch R 0000 0000h CR1 Capture register 1 see
Table 17–212
030h R 0000 0000h CR2 Capture register 2 see
Table 17–212
034h R 0000 0000h CR3 Capture register 3 see
Table 17–212
FD4h R 0000 00C80h reserved Reserved
FD8h W - INT_CLR_ENABLE Interrupt clear-enable register see
Table 10–93
FDCh W - INT_SET_ENABLE Interrupt set-enable register see
Table 10–94
FE0h R 0000 0000h INT_STATUS Interrupt status register see
Table 10–95
FE4h R 0000 0000h INT_ENABLE Interrupt enable register see
Table 10–96

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Table 204. Timer register overview (base address: E004 1000h (timer 0), E004 2000h (timer 1), E004 3000h (timer 2),

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E004 4000h (timer 3), E00C 0000h (MSCSS timer 0, E00C1000h (MSCSS timer 1)) …continued

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Address Access Reset value Name Description Reference

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offset

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FE8h W - INT_CLR_STATUS Interrupt clear-status register see

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Table 10–97

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FECh W - INT_SET_STATUS Interrupt set-status register see

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Table 10–98
FFCh R 3012 2400h reserved Reserved

5.1 Timer control register (TCR)

The TCR is used to control the operation of the timer counter. The counting process starts
on CLK_TMRx once the COUNTER_ENABLE bit is set. The process can be reset by
setting the COUNTER_RESET bit. The Timer_Counter and Prescale_Counter remain in
the reset state as long as the COUNTER_RESET bit is active. The counting process is
suspended when the PAUSE_ENABLE bit is set and the pause pin is high.

Table 205. TCR register bits

* = reset value
Bit Variable name Access Value Description
31 to 3 reserved R - Reserved; do not modify, read as logic 0
2 PAUSE_ENABLE R/W Enables the pause feature of the timer. If
this bit is set the timer and prescale
counters will be stopped when a logic
HIGH is asserted on timer pin PAUSE [1]
0*
1 COUNTER_RESET R/W Reset timer and prescale counter. If this bit
is set the counters remain reset until it is
cleared again
0*
0 COUNTER_ENABLE R/W Enable timer and prescale counter. If this
bit is set the counters are running
0*

[1] Only for MSCSS Timer 0 and MSCSS Timer 1. For all other timers this bit is reserved: do not modify, read
as logic 0.

5.2 Timer counter

The timer counter represents the timer-count value, which is incremented every prescale
cycle. Depending on the prescale register value and the period of CLK_TMRx, this means
that the contents of the register can change very rapidly.

Table 206. TC register bits

* = reset value
Bit Variable name Access Value Description
31 to 0 TC[31:0] R/W Timer counter. It is advisable not to access this
register, which may change very rapidly
0000 00
00h*

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5.3 Timer prescale register

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The timer prescale register determines the number of clock cycles used as a prescale

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value for the timer counter clock. When the Prescale_Register value is not equal to zero

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the internal prescale counter first counts the number of CLK_TMRx cycles as defined in

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this register plus one, then increments the TC_value.

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Updates to the prescale register PR are only possible when the timer and prescale

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counters are disabled, see bit COUNTER_ENABLE in the TCR register. It is advisable to
reset the timer counters once a new prescale value has been programmed. Writes to this
register are ignored when the timer counters are enabled (i.e. bit COUNTER_ENABLE in
the TCR register is set).

Table 207. PR register bit description

* = reset value
Bit Variable name Access Value Description
31 to 0 PR[31:0] R/W Prescale register. This specifies the maximum
value for the prescale counter. The timer
counter (TC) increments after ‘PR+1’
CLK_TMRx cycles are counted.
0000 00
00h*

5.4 Timer match-control register

Each MCR can be configured through the match control register to stop both the timer
counter and prescale counter. This maintains their value at the time of the match to restart
the timer counter at logic 0, and allows the counters to continue counting and/or generate
an interrupt when their contents match those of the timer counter. A stop-on-match has
higher priority than a reset-on-match.

An interrupt is generated if one of the match registers matches the contents of the timer
counter and the interrupt has been enabled through the interrupt-enable control register.

The match control register is used to control what operations are performed when one of
the match registers matches the timer counter.

Table 208. MCR register bits

* = reset value
Bit Variable name Access Value Description
31 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 STOP_3 R/W 1 Stop on match MR3 and TC. When logic 1 the
timer and prescale counter stop counting if
MR3 matches TC
0*
6 RESET_3 R/W 1 Reset on match MR3 and TC. When logic 1 the
timer counter is reset if MR3 matches TC
0*
5 STOP_2 R/W 1 Stop on match MR2 and TC. When logic 1 the
timer and prescale counter stop counting if
MR2 matches TC
0*

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Table 208. MCR register bits …continued

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* = reset value

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Bit Variable name Access Value Description

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4 RESET_2 R/W 1 Reset on match MR2 and TC. When logic 1 the

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timer counter is reset if MR2 matches TC

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0*

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3 STOP_1 R/W 1 Stop on match MR1 and TC. When logic 1 the

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timer and prescale counter stop counting if
MR1 matches TC
0*
2 RESET_1 R/W 1 Reset on match MR1 and TC. When logic 1 the
timer counter is reset if MR1 matches TC
0*
1 STOP_0 R/W 1 Stop on match MR0 and TC. When logic 1 the
timer and prescale counter stop counting if
MR0 matches TC
0*
0 RESET_0 R/W 1 Reset on match MR0 and TC. When logic 1 the
timer counter is reset if MR0 matches TC
0*

5.5 Timer external-match register

The EMR provides both control and status of the external match pins. The external match
flags and the match outputs can either toggle, go to logic 0, go to logic 1 or maintain state
when the contents of the match register are equal to the contents of the timer counter.
Note that the match output is set to a specific level on writing the CTRL bits.

Table 209. EMR register bits

* = reset value
Bit Variable name Access Value Description
31 to 10 reserved R - Reserved; do not modify. Read as logic 0
11 and 10 CTRL_3[1:0] R/W External match control 3
00* Do nothing
01 Set logic 0
10 Set logic 1
11 Toggle
9 and 8 CTRL_2[1:0] R/W External match control 2
00* Do nothing
01 Set logic 0
10 Set logic 1
11 Toggle
7 and 6 CTRL_1[1:0] R/W External match control 1
00* Do nothing
01 Set logic 0
10 Set logic 1
11 Toggle

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Table 209. EMR register bits …continued

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* = reset value

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Bit Variable name Access Value Description

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5 and 4 CTRL_0[1:0] R/W External match control 0

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00* Do nothing

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01 Set logic 0

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10 Set logic 1

A
11 Toggle
3 EMR_3 R 0 Current value of the Match 3 pin
2 EMR_2 R 0 Current value of the Match 2 pin
1 EMR_1 R 0 Current value of the Match 1 pin
0 EMR_0 R 0 Current value of the Match 0 pin

5.6 Timer match register

The MR determines the timer-counter match value. Four match registers are available per
timer.

Table 210. MR register bits

* = reset value
Bit Variable name Access Value Description
31 to 0 MR[31:0] R/W Match register. This specifies the match
value for the timer counter
0000 00
00h*

5.7 Timer capture-control register

The CCR controls when one of the four possible capture registers is loaded with the value
in the timer counter, and whether an interrupt is generated when the capture occurs.

A rising edge is detected if the sequence logic 0 followed by logic 1 occurs: a falling edge
is detected if logic 1 followed by logic 0 occurs. The capture control register maintains
two bits for each of the counter registers to enable sequence detection for each of the
capture registers. If the enabled sequence is detected the timer counter value is loaded
into the capture register. If it has been enabled through the interrupt-enable control
register an interrupt is then generated. Setting both the rising and falling bits at the same
time is a valid configuration.

A reset clears the CCR register.

Table 211. CCR register bits

* = reset value
Bit Variable name Access Value Description
31 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 FALL_3 R/W 1 Capture on capture input 3 falling. When
logic 1, a sequence of logic 1 followed by
logic 0 from capture input 3 causes CR3 to
be loaded with the contents of TC
0*

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Table 211. CCR register bits …continued

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* = reset value

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Bit Variable name Access Value Description

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6 RISE_3 R/W 1 Capture on capture input 3 rising. When

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logic 1, a sequence of logic 0 followed by

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logic 1 from capture input 3 causes CR3 to

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be loaded with the contents of TC

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0*
5 FALL_2 R/W 1 Capture on capture input 2 falling. When
logic 1, a sequence of logic 1 followed by
logic 0 from capture input 2 causes CR2 to
be loaded with the contents of TC
0*
4 RISE_2 R/W 1 Capture on capture input 2 rising. When
logic 1, a sequence of logic 0 followed by
logic 1 from capture input 2 causes CR2 to
be loaded with the contents of TC
0*
3 FALL_1 R/W 1 Capture on capture input 1 falling. When
logic 1, a sequence of logic 1 followed by
logic 0 from capture input 1 causes CR1 to
be loaded with the contents of TC
0*
2 RISE_1 R/W 1 Capture on capture input 1 rising. When
logic 1, a sequence of logic 0 followed by
logic 1 from capture input 1 causes CR1 to
be loaded with the contents of TC
0*
1 FALL_0 R/W 1 Capture on capture input 0 falling. When
logic 1, a sequence of logic 1 followed by
logic 0 from capture input 0 causes CR0 to
be loaded with the contents of TC
0*
0 RISE_0 R/W 1 Capture on capture input 0 rising. When
logic 1, a sequence of logic 0 followed by
logic 1 from capture input 0 causes CR0 to
be loaded with the contents of TC
0*

5.8 Timer capture register

The CR is loaded with the timer-counter value when there is an event on the relevant
capture input. Four capture registers are available per timer.

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Table 212. CR register bits

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* = reset value

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Bit Variable name Access Value Description

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31 to 0 CR[31:0] R Capture register. This reflects the

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timer-counter captured value after a capture

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event

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0000 00

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00h*

5.9 Timer interrupt bit description

Table 17–213 gives the interrupts for the timer. The first column gives the bit number i in
the interrupt registers. For a general explanation of the interrupt concept and a description
of the registers see Section 10–5.

Table 213. Timer interrupt sources

Register Interrupt source Description
bit
31 to 8 unused Unused
7 C3 Capture 3 event
6 C2 Capture 2 event
5 C1 Capture 1 event
4 C0 Capture 0 event
3 M3 Match 3 event
2 M2 Match 2 event
1 M1 Match 1 event
0 M0 Match 0 event

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts.

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2. Introduction
The LPC29xx contains three Serial Peripheral Interface (SPI) modules to enable
synchronous serial communication with slave or master peripherals that have either
Motorola SPI or Texas Instruments synchronous serial interfaces.

The key features are:

• Master or slave operation

• Supports up to four slaves in sequential multi-slave operation
• Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock
• Separate transmit and receive FIFO memory buffers; each 16 bits wide by
32 locations deep
• Programmable choice of interface operation: Motorola SPI or Texas Instruments
synchronous serial interfaces
• Programmable data-frame size from four to16 bits
• Independent masking of transmit FIFO, receive FIFO and receive-overrun interrupts
• Serial clock rate master mode: fserial_clk ≤ fCLK_SPI/2
• Serial clock rate slave mode: fserial_clk = fCLK_SPI/4
• Internal loop-back test mode

2.1 SPI functional description

The SPImodule performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories (16 bits wide x
32 words deep). Serial data is transmitted on SPI_TxD and received on SPI_RxD.

2.1.1 Modes of operation

The SPI module can operate in:

• Master mode:
– Normal transmission mode
– Sequential-slave mode
• Slave mode
Normal transmission mode

In normal transmission mode software intervention is needed every time a new slave
needs to be addressed. Also some interrupt handling is required.

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In normal transmission mode software programs the settings of the SPI module, writes

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data to the transmit FIFO and then enables the SPI module. The SPI module transmits

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until all data has been sent, or until it gets disabled with data still unsent. When data

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needs to be transmitted to another slave software has to re-program the settings of the

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SPI module, write new data and enable the SPI module again.

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Remark: When reprogramming any of its settings the SPI module needs to be disabled

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first, then enabled again after changing the settings. Transmit data can also be added

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when the SPI module is still enabled: disabling is not necessary in this case.

Sequential-slave mode

This mode reduces software intervention and interrupt load.

In this mode it is possible to sequentially transmit data to different slaves without having to
reprogram the SPI module between transfers. The purpose of this is to minimize
interrupts, software intervention and bus traffic. This mode is only applicable when the SPI
module is in master mode.

In the example in Figure 18–64 the SPI module supports addressing of four slaves, all of
which are sent data in sequential-slave mode. Three elements are transferred to slave 1,
two to slave 2, three to slave 3 and finally one to slave 4, after which the SPI module
disables itself. When it gets enabled again the same data is transmitted to the four slaves.

Before entering this mode the transmit data needs to be present in the transmit FIFO. No
data may be added after entering sequential-slave mode. When the data to be transferred
needs to be changed the transmit FIFO needs to be flushed and sequential-slave mode
has to be left and entered again to take over the new data present in the transmit FIFO.
This is necessary because the FIFO contents are saved as a side-effect of entering
sequential-slave mode from normal transmission mode. The data in the transmit FIFO will
be saved to allow transmitting it repeatedly without the need to refill the FIFO with the
same data.

All programming of the settings necessary to adapt to all slaves has to be done before
enabling (starting the transfer) the SPI module in sequential-slave mode. Once a transfer
has started these settings cannot be changed until the SPI module has finished the
transfer and is automatically disabled again. The use of only one slave in sequential-slave
mode is possible.

Once a sequential-slave mode transfer has started it will complete even if the SPI module
is disabled before the transfers are over. When a transfer is finished the SPI module
disables itself and request a sequential-slave mode ready interrupt.

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Transmit FIFO

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1 Slave 1

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2 Slave 2
1
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3 Slave 3
1

Slave 4

Fig 64. Sequential-slave mode: example

It is possible to temporarily suspend or skip one or more of the slaves in a transfer. To do

this the data in the transmit FIFO does not need to be flushed: during the transfer it is
skipped and nothing happens on the serial interface for the exact time that would have
been used by transferring to the skipped slave. In the receive FIFO dummy zero-filled
words are written, their number being equal to the number of words that would have been
received by the suspended slave. When suspending slaves it is important to keep the
corresponding SLVn_SETTINGS. The NUMBER_WORDS field is necessary to skip the
data for this slave and the other settings are needed to create the delay of the suspended
transfer on the serial interface. Suspending a slave does not change anything in the
duration of a sequential-slave transfer.

A slave can also be completely disabled. In this case the transmit FIFO may not hold any
data for this slave, which means the transmit FIFO may need to be flushed and
reprogrammed. The SLVn_SETTINGS for a disabled slave are ignored.

2.1.2 Slave mode

The SPI module can be used in slave mode by setting the MS_MODE bit in the
SPI_CONFIG register. The settings of the slave can be programmed in the
SLV0_SETTINGS registers that would correspond to slave 0 (offsets 02h4 and 028h).
Only slave 0 can be enabled by writing 01h to the SLV_ENABLE register and setting the
update_enable bit in the SPI_CONFIG register. A slave can only be programmed to be in
normal transmission mode.

3. SPI register overview

The SPI registers are shown in Table 18–214. These have an offset to the base address
SPI RegBase which can be found in the memory map, see Section 2–2.

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Table 214. SPI register overview (base address: 0xE004 7000 (SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2))

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F
Address Access Reset value Name Description Reference

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offset

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000h R/W 0001 0000h SPI_CONFIG Configuration register see

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Table 18–215

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004h R/W 0000 0000h SLV_ENABLE Slave-enable register see

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Table 18–216

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008h W - TX_FIFO_FLUSH Tx FIFO flush register see
Table 18–217
00Ch R/W 0000 0000h FIFO_DATA FIFO data register see
Table 18–218
010h W 010h RX_FIFO_POP Rx FIFO pop register see
Table 18–219
014h R/W 0000 0000h RX_FIFO_READM Rx FIFO read-mode selection register see
ODE Table 18–220
018h R/W 0000 0000h DMA_SETTINGS DMA settings and enable register -
01Ch R 0000 0005h STATUS Status register see
Table 18–222
024h R/W 0000 0020h SLV0_SETTINGS1 Slave-settings register 1 for slave 0 see
Table 18–223
028h R/W 0000 0000h SLV0_SETTINGS2 Slave-settings register 2 for slave 0 see
Table 18–224
02Ch R/W 0000 0020h SLV1_SETTINGS1 Slave-settings register 1 for slave 1 see
Table 18–223
030h R/W 0000 0000h SLV1_SETTINGS2 Slave-settings register 2 for slave 1 see
Table 18–224
034h R/W 0000 0020h SLV2_SETTINGS1 Slave-settings register 1 for slave 2 see
Table 18–223
038h R/W 0000 0000h SLV2_SETTINGS2 Slave-settings register 2 for slave 2 see
Table 18–224
03Ch R/W 0000 0020h SLV3_SETTINGS1 Slave-settings register 1 for slave 3 see
Table 18–223
040h R/W 0000 0000h SLV3_SETTINGS2 Slave-settings register 2 for slave 3 see
Table 18–224
FD4h R/W 0000 0000h INT_THRESHOLD Tx/Rx FIFO threshold interrupt levels see
Table 18–225
FD8h W - INT_CLR_ENABLE Interrupt clear-enable register see
Table 10–93
FDCh W - INT_SET_ENABLE Interrupt set-enable register see
Table 10–94
FE0h R 0000 0000h INT_STATUS Interrupt status register see
Table 10–95
FE4h R 0000 0000h INT_ENABLE interrupt enable register see
Table 10–96
FE8h W - INT_CLR_STATUS Interrupt clear-status register see
Table 10–97
FECh W - INT_SET_STATUS Interrupt set-status register see
Table 10–98
FFCh - 3409 3600h reserved Reserved

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3.1 SPI configuration register

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The SPI configuration register configures SPI operation mode.

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Table 215. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000

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(SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2))

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* = reset value

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Bit Symbol Access Value Description

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31 to 16 INTER_SLAVE_DLY R/W The minimum delay between two transfers
to different slaves on the serial interface
(measured in clock cycles of
BASE_SPI_CLK)
The minimum value is 1.
0001h*
15 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 UPDATE_ENABLE R/W Update enable bit
This must be set by software when the
SLV_ENABLE register has been
programmed. It will be automatically cleared
when the new value is in use.
In sequential-slave mode the newly
programmed value will be used when the
pending sequential-slave transfer finishes.
In normal transmission mode the newly
programmed value will be used right away
(after a clock-domain synchronization delay)
1 The newly programmed value in the
SLV_ENABLE register is not used for
transmission yet. As soon as the value is
used this bit is cleared automatically.
0* The current value in the SLV_ENABLE
register is used for transmission. A new
value may be programmed. As soon as
update enable is cleared again the new
value will be used for transmission
6 SOFTWARE_RESET R/W Software reset bit.
1 Writing 1 to this bit resets the SPI module
completely. This bit is self-clearing
0*
5 TIMER_TRIGGER R/W Timer trigger-block bit
When set the trigger pulses received from a
timer (outside the SPI) enable the SPI
module; otherwise they are ignored.
NOTE: the SPI module can only be enabled
by the timer when in sequential-slave mode,
otherwise the trigger pulses are ignored.
Timer2 Match Outputs:
Tmr2, Match0 --> SP10, trigger in
Tmr2, Match1 --> SP11, trigger in
Tmr2, Match2 --> SP12, trigger in
1 Trigger pulses enable SPI module
0* Trigger pulses are ignored
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Table 215. SPI_CONFIG register bit description (SPI_CONFIG0/1/2, addresses: 0xE004 7000

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(SPI0), 0xE004 8000 (SPI1), 0xE004 9000 (SPI2)) …continued

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* = reset value

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Bit Symbol Access Value Description

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4 SLAVE_DISABLE R/W Slave-output disable (only relevant in slave

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mode)

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When multiple slaves are connected to a

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single chip-select signal for broadcasting of

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a message by a master, only one slave may
drive data on its transmit-data line since all
slave transmit-data lines are tied together to
the single master.
1 Slave cannot drive its transmit-data output
0* Slave can drive its transmit-data output
3 TRANSMIT_MODE R/W Transmit mode
1 Sequential-slave mode
0* Normal mode
2 LOOPBACK_MODE R/W Loopback-mode bit
Note: when the RX FIFO width is smaller
than the TX FIFO width the most significant
bits of the transmitted data will be lost in
loopback mode.
1 Transmit data is internally looped-back and
received
0* Normal serial interface operation
1 MS_MODE R/W Master/slave mode
1 Slave mode
0* Master mode
0 SPI_ENABLE R/W SPI enable bit
Slave mode:
If the SPI module is not enabled it will not
accept data from a master or send data to a
master.
Master mode:
If there is data present in the transmit FIFO
the SPI module will start transmitting. This
bit will also be set when the SPI module
receives a non-blocked enable trigger from
the external timer in sequential-slave mode.
In sequential-slave mode or when using the
external trigger this bit is self-clearing.
1 SPI enable
0* SPI disable

3.2 SPI slave-enable register

The slave-enable register controls which slaves are enabled.

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Table 216. SLV_ENABLE register bit description (SLV_ENABLE0/1/2, addresses: 0xE004

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7004 (SPI0), 0xE004 8004 (SPI1), 0xE004 9004 (SPI2))

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* = reset value

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Bit Symbol Access Value Description

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31 to 8 reserved R - Reserved; do not modify. Read as logic 0

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Slave enable slave 3[1]

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6 and 7 SLV_ENABLE_3 R/W

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00* The slave is disabled

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01 The slave is enabled
10 Not supported
11 The slave is suspended
4 and 5 SLV_ENABLE_2 R/W Slave enable slave 2[1]
00* The slave is disabled
01 The slave is enabled
10 Not supported
11 The slave is suspended
3 and 2 SLV_ENABLE_1 R/W Slave enable slave 1[1]
00* The slave is disabled
01 The slave is enabled
10 Not supported
11 The slave is suspended
1 and 0 SLV_ENABLE_0 R/W Slave enable slave 0[1]
00* The slave is disabled
01 The slave is enabled
10 Not supported
11 The slave is suspended

[1] In normal transmission mode only one slave may be enabled and the others should be disabled: in
sequential-slave mode more than one slave may be enabled. Slaves can also be suspended, which means
they will be skipped during the transfer. This is used to avoid sending data to a slave while there is data in
the transmit FIFO for that slave, thus skipping data in the transmit FIFO.

3.3 SPI transmit-FIFO flush register

The transmit-FIFO flush register forces transmission of the transmit FIFO contents.

Table 217. TX_FIFO_FLUSH register bit description (TX_FIFO_FLUSH0/1/2: addresses

0xE004 7008 (SPI0), 0xE004 8008 (SPI1), 0xE004 9008 (SPI2))
Bit Symbol Access Value Description
31 to 1 reserved R - Reserved; do not modify. Read as logic 0
0 TX_FIFO_FLUSH W 1 Flush transmit FIFO
In sequential-slave mode the transmit FIFO
keeps its data by default. This means that the
FIFO needs to be flushed before changing its
contents.

3.4 SPI FIFO data register

The FIFO data register is used to write to the transmit FIFO or read from the receive FIFO.

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Table 218. FIFO_DATA register bit description (FIFO_DATA0/1/2: addresses 0xE004 700C

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(SPI0), 0xE004 800C (SPI1), 0xE004 900C (SPI2))

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* = reset value

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Bit Symbol Access Value Description

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31 to reserved R - Reserved; do not modify. Read as logic 0

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16

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15 to 0 FIFO_DATA R/W 0000h* This register is used to access the FIFOs:

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Writing data puts new data in the transmit
FIFO.
Reading data reads a word from the receive
FIFO[1].

[1] The RX_FIFO_READMODE register can change the effect of reading this register.

3.5 SPI receive FIFO POP register

The receive-FIFO POP register is used in RX FIFO PROTECT mode (see
Section 18–3.6) to pop the first element from the receive FIFO.

Table 219. RX_FIFO_POP register bit description (FIFO_POP0/1/2: addresses 0xE004 7010
(SPI0), 0xE004 8010 (SPI1), 0xE004 9010 (SPI2))
Bit Symbol Access Value Description
31 to 1 reserved R - Reserved; do not modify. Read as logic 0
0 RX_FIFO_POP W 1 Pops the first element from the receive FIFO.
This is necessary in RX FIFO PROTECT
mode because reading the FIFO_DATA
register will not cause the receive FIFO
pointer to be updated. This is to protect the
receive FIFO against losing data because of
speculative reads.

3.6 SPI receive-FIFO read-mode register

The receive-FIFO read-mode register configures the SPI RX FIFO read mode.

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Table 220. RX_FIFO_READMODE register bit description (RX_FIFO_READMODE0/1/2:

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addresses 0xE004 7014 (SPI0), 0xE004 8014 (SPI1), 0xE004 9014 (SPI2))

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* = reset value

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Bit Symbol Access Value Description

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31 to 1 reserved R - Reserved; do not modify. Read as logic 0

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0 RX_FIFO_PROTECT R/W Receive-FIFO protect-mode bit

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1 Enables the receive-FIFO protect mode to

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protect the receive-FIFO contents from
speculative read actions
A read of the FIFO_DATA register will return
the data from the FIFO, but will not update the
FIFO’s read pointer. Speculative reads of the
FIFO_DATA register will thus not cause data
loss from the receive FIFO. After every read of
data the RX FIFO POP register needs to be
written to remove the read element from the
FIFO and to point to the next element.
0* Disables receive-FIFO protect mode
An explicit pop of the receive FIFO is no
longer needed. Reading the FIFO_DATA
register will also update the receive FIFO’s
read pointer.

3.7 SPI DMA settings register

The DMA settings register enables the DMA transfer for the receive and transmit lines and
the defines the burst mode.

Table 221. DMA_SETTINGS register bit description (DMA_SETTINGS0/1/2: addresses

0xE004 7018 (SPI0), 0xE004 8018 (SPI1), 0xE004 9018 (SPI2))
* = reset value
Bit Symbol Access Value Description
31 to 8 reserved R - Reserved; do not modify. Read as logic 0
7:5 TX_DMA_BURST R/W 000* - Defines when the SPI will request a Tx burst
111 DMA transfer. The DMA burst will be
requested when the transmit FIFO has this
number of free spaces (= room to hold one
element):
000 : 1 free space
001 : 4 free spaces
010 : 8 free spaces
011 : 16 free spaces
100 : 32 free spaces
101 : 64 free spaces
110 : 128 free spaces
111 : 256 free spaces

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Table 221. DMA_SETTINGS register bit description (DMA_SETTINGS0/1/2: addresses

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0xE004 7018 (SPI0), 0xE004 8018 (SPI1), 0xE004 9018 (SPI2)) …continued

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F
* = reset value

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Bit Symbol Access Value Description

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4:2 RX_DMA_BURST R/W 000* - Defines when the SPI will request a Rx burst

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111 DMA transfer. The DMA burst will be

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requested when the receive FIFO contains

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this number of received data elements:

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000 : 1 element
001 : 4 elements
010 : 8 elements
011 : 16 elements
100 : 32 elements
101 : 64 elements
110 : 128 elements
111 : 256 elements
1 TX_DMA_ENABLE R/W Tx DMA enable bit
1 DMA enabled
0* DMa disabled
0 RX_DMA-ENABLE R/W Rx DMA enable bit
1 DMA enabled
0* DMA disabled

3.8 SPI status register (Status)

The status register summarizes the status of the SPI module.

Table 222. SPI status-register bit description (STATUS0/1/2, addresses: 0xE004 701C (SPI0),
0xE004 801C (SPI1), 0xE004 901C (SPI2))
* = reset value
Bit Symbol Access Value Description
31 to 6 reserved R - Reserved; do not modify. Read as logic 0
5 SMS_MODE_BUSY R Sequential-slave mode busy flag
1 SPI is currently transmitting in sequential-slave
mode. Once all data to all slaves has been
sent this bit will be cleared
0* SPI is not in sequential-slave mode or not busy
transmitting in this mode
4 SPI_BUSY R SPI busy flag
1 SPI is currently transmitting/receiving or the
transmit FIFO is not empty
0* SPI is idle
3 RX_FIFO_FULL R Receive FIFO full bit
1 Receive FIFO full
0* Receive FIFO not full
2 RX_FIFO_EMPTY R Receive FIFO empty bit
1* Receive FIFO empty
0 Receive FIFO not empty
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Table 222. SPI status-register bit description (STATUS0/1/2, addresses: 0xE004 701C (SPI0),

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0xE004 801C (SPI1), 0xE004 901C (SPI2)) …continued

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* = reset value

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Bit Symbol Access Value Description

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1 TX_FIFO_FULL R Transmit FIFO full bit

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1 Transmit FIFO full

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0* Transmit FIFO not full

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0 TX_FIFO_EMPTY R Transmit FIFO empty bit
1* Transmit FIFO empty
0 Transmit FIFO not empty

3.9 SPI slave-settings 1 register

The 1st slave-settings register configures the serial clock rate, the number of words and
the inter-frame delay for each slave of the SPI module.

Table 223. SLVn_SETTINGS1 register bit description (SLV0/1/2_SETTINGS1, addresses:

0xE004 7024/2C/34/3C (SPI0), 0xE004 8024/2C/34/3C (SPI1), 0xE004 9024/2C/34/3C
(SPI2))
* = reset value
Bit Symbol Access Value Description
31 to 24 INTER_TRANSFER_DLY R/W The delay between transfers to this
slave, measured in serial clock cycles.
This delay is a minimum of 0 serial clock
cycles[1]
00h*
23 to 16 NUMBER_WORDS R/W Number of words to send in sequential-
slave mode.
After this number of words has been
transmitted to the slave the master will
start transmitting to the next slave. If
sequential-slave mode is disabled this
field is not used (minus 1 encoded)[1].
00h*
15 to 8 CLK_DIVISOR2 R/W Serial clock-rate divisor 2[2]:
A value from 2 to 254 (lsb bit is
hard-coded 0)
02h*
7 to 0 CLK_DIVISOR1 R/W Serial clock-rate divisor 1[2]:
A value from 0 to 255
00h*

[1] This register is only relevant in master mode, and each individual slave has its own parameters.
[2] The serial-clock frequency is derived from BASE_SPI_CLK (CLK_SPI) using the values programmed in the
CLK_DIVISOR1 and CLK_DIVISOR2 fields:

f ( CLK_SPI )
fserialclk = ---------------------------------------------------------------------------------
clkdivisor2 × ( 1 + clkdivisor1 )

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3.10 SPI slave-settings 2 register

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The SPI second slave-settings register configures several other parameters for each

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slave of the SPI module.

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Remark: Some bits in this register are only relevant in master mode, and each individual

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slave has its own register with parameters.

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Table 18–224 shows the bit assignment of the SLVn_SETTINGS2 register.

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Table 224. SLVn_SETTINGS2 register bit description (SLV0/1/2_SETTINGS2, addresses:
0xE004 7028/30/38/40 (SPI0), 0xE004 8028/30/38/40 (SPI1), 0xE004 9028/30/38/40
(SPI2))
* = reset value
Bit Symbol Access Value Description
31 to 17 reserved R - Reserved; do not modify. Read as logic 0
16 to 9 PRE_POST_CS_DLY R/W Programmable delay that occurs twice in
a transfer. This delay is present (i)
between assertion of the chip-select and
transfer (sampling) of the first data bit
AND (ii) between transfer of the last data
bit and de-assertion of chip-select.
The minimum delay is one SPI serial clock
cycle. This register is minus-one encoded
(0 gives a one-cycle delay).
This field is only relevant in master mode.
0*
8 CS_VALUE R/W Chip-select value between back-to-back
transfers selection bit.
The period in which the chip-select has
this value is programmed in the
inter_transfer_dly field of the
SLVn_SETTINGS1 register
This field is only relevant in master mode.
1 Chip-select has a steady-state HIGH
value between transfers
0* Chip-select has a steady-state LOW value
between transfers
7 TRANSFER_FORMAT R/W Format of transfer
1 Texas Instruments synchronous serial
format
0* Motorola SPI format
6 SPO R/W Serial clock polarity (only used if Motorola
SPI mode is selected)
1 The serial clock has a steady-state HIGH
value between transfers
0* The serial clock has a steady-state LOW
value between transfers

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Table 224. SLVn_SETTINGS2 register bit description (SLV0/1/2_SETTINGS2, addresses:

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0xE004 7028/30/38/40 (SPI0), 0xE004 8028/30/38/40 (SPI1), 0xE004 9028/30/38/40

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(SPI2)) …continued

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* = reset value

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Bit Symbol Access Value Description

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5 SPH R/W Serial clock phase (only used if Motorola

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SPI mode is selected). Determines which

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edges of the serial clock data is captured

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on during transfers.
1 First data bit is captured on the second
clock-edge transition of a new transfer
0* First data bit is captured on the first clock-
edge transition of a new transfer
4 to 0 WORDSIZE R/W Word size of transfers to this slave[1]
(minus 1 encoded)
Motorola SPI mode:
0 0111h 8 bits
0 1111h 16 bits
Texas Instruments synchronous serial
mode:
0 0011h 4 bits
0 0111h 8 bits
0 1111h 16 bits
0
0000h*

[1] Tx: If WORDSIZE < Tx FIFO width (16 bits) only the LSBs are transmitted. Rx: In case WORDSIZE < Rx
FIFO (16 bits) the MSBs of the data stored in the Rx FIFO are zero.

3.11 SPI FIFO interrupt threshold register

The interrupt threshold register configures the FIFO levels at which an interrupt request is
generated to service the FIFOs.

Table 18–225 shows the bit assignment of the INT_THRESHOLD register.

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Table 225. INT_THRESHOLD register bit description (INT_THRESHOLD, addresses: 0xE004

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7FD4 (SPI0), 0xE004 8FD4 (SPI1), 0xE004 9FD4 (SPI2))

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* = reset value

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Bit Symbol Access Value Description

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31 to 16 reserved R - Reserved; do not modify. Read as logic 0

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15 to 8 TX_THRESHOLD R/W A transmit threshold-level interrupt is

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requested when the transmit FIFO contains

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less than this number of elements. When the
value is higher than the FIFO size the
behavior of the threshold interrupt is
undefined.
00h*
7 to 0 RX_THRESHOLD R/W A receive threshold-level interrupt is
requested when the receive FIFO contains
more than this number of elements. When
the value is higher than the FIFO size the
behavior of the threshold interrupt is
undefined.
00h*

3.12 SPI interrupt bit description

Table 18–226 gives the interrupts for the Serial Peripheral Interface. The first column
gives the bit number in the interrupt registers. For an overview of the interrupt registers
see Table 18–214. For a general explanation of the interrupt concept and a description of
the registers see Section 10–5.

Table 226. SPI interrupt sources

Register Interrupt source Description
bit
31 to 5 unused Unused
4 SMS Sequential-slave mode ready
3 TX Transmit threshold level
2 RX Receive threshold level
1 TO Receive time-out
0 OV Receive overrun

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Receiver/Transmitter (UART)

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1. How to read this chapter

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The contents of this chapter apply to all LPC29xx parts. The modem control features are
pinned out on the LPC2939/30 only. Therefore, registers MCR, MSR and RS485DLY are
available on LPC2939/30 only

2. Features
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Fractional divider for baud rate control, autobaud capabilities and mechanism that
enables software flow control implementation.
• RS-485/9-bit mode support.
• DMA support.
• Standard modem interface signals included (CTS, DCD, DTS, DTR, RI, RTS).

3. Pin description
Table 227. UART0/1 Pin description
Pin Type Description
UART0 RXD, UART1 RXD Input Serial Input. Serial receive data.
UART0 TXD, UART1 TXD Output Serial Output. Serial transmit data.
Modem interface pins
UART0/1 CTS Input Clear To Send. Active low signal indicates if the external
modem is ready to accept transmitted data via TXD1 from the
UART1. In normal operation of the modem interface
(MCR[4] = 0), the complement value of this signal is stored in
U1MSR[4]. State change information is stored in MSR[0] and
is a source for a priority level 4 interrupt, if enabled
(IER[3] = 1).
Only CTS1 is also used in auto-cts mode to control the UART1
transmitter.
Clear to send. CTS1 is an asynchronous, active low modem
status signal. Its condition can be checked by reading bit 4
(CTS) of the modem status register. Bit 0 (DCTS) of the
Modem Status Register (MSR) indicates that CTS1 has
changed states since the last read from the MSR. If the
modem status interrupt is enabled when CTS1 changes levels
and the auto-cts mode is not enabled, an interrupt is
generated. CTS1 is also used in the auto-cts mode to control
the transmitter.

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Table 227. UART0/1 Pin description

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Pin Type Description

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UART0/1 DCD Input Data Carrier Detect. Active low signal indicates if the external

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modem has established a communication link with the UART1

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and data may be exchanged. In normal operation of the

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modem interface (MCR[4]=0), the complement value of this

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signal is stored in MSR[7]. State change information is stored

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in MSR3 and is a source for a priority level 4 interrupt, if

A
enabled (IER[3] = 1).
UART0/1 DSR Input Data Set Ready. Active low signal indicates if the external
modem is ready to establish a communications link with the
UART1. In normal operation of the modem interface
(MCR[4] = 0), the complement value of this signal is stored in
MSR[5]. State change information is stored in MSR[1] and is a
source for a priority level 4 interrupt, if enabled (IER[3] = 1).
UART0/1 DTR Output Data Terminal Ready. Active low signal indicates that the
UART1 is ready to establish connection with external modem.
The complement value of this signal is stored in MCR[0].
The DTR pin can also be used as an RS-485/EIA-485 output
enable signal.
UART0/1 RI Input Ring Indicator. Active low signal indicates that a telephone
ringing signal has been detected by the modem. In normal
operation of the modem interface (MCR[4] = 0), the
complement value of this signal is stored in U1MSR[6]. State
change information is stored in MSR[2] and is a source for a
priority level 4 interrupt, if enabled (IER[3] = 1).
UART0/1 RTS Output Request To Send. Active low signal indicates that the UART1
would like to transmit data to the external modem. The
complement value of this signal is stored in MCR[1].
Only in the auto-rts mode uses RTS to control the transmitter
FIFO threshold logic.
Request to send. RTS1 is an active low signal informing the
modem or data set that the UART is ready to receive data.
RTS is set to the active (low) level by setting the RTS modem
control register bit and is set to the inactive (high) level either
as a result of a system reset or during loop-back mode
operations or by clearing bit 1 (RTS) of the MCR. In the
auto-rts mode, RTS is controlled by the transmitter FIFO
threshold logic.
The RTS pin can also be used as an RS-485/EIA-485 output
enable signal.
UART0/1 UOUT1/2 Output <tbd>

4. Register description
Each UART contains registers as shown in Table 19–228. The Divisor Latch Access Bit
(DLAB) is contained in UnLCR7 and enables access to the Divisor Latches.

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Table 228. UART Register Map ( base address 0xE004 5000 (UART0) and 0xE004 6000 (UART1))
Generic Description Bit functions and addresses Acces Reset UARTn Register
Name MSB LSB s value[1 Name & Address
]

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RBR Receiver Buffer 8 bit Read Data RO NA U0RBR - 0xE004 5000
(DLAB=0) Register U1RBR - 0xE004 6000
THR Transmit Holding 8 bit Write Data WO NA U0THR - 0xE004 5000
(DLAB=0) Register U1THR - 0xE004 6000
DLL Divisor Latch 8 bit Data R/W 0x01 U0DLL - 0xE004 5000
(DLAB=1) LSB U1DLL - 0xE004 6000
DLM Divisor Latch 8 bit Data R/W 0x00 U0DLM - 0xE004 5004
(DLAB=1) MSB U1DLM - 0xE004 6004
IER Interrupt Enable Reserved Enable Enable End R/W 0x00 U0IER - 0xE004 5004

Chapter 19: LPC29xx Universal Asynchronous FReceiver/Transmitter

(DLAB=0) Register Auto- Baud of Auto- U1IER - 0xE004 6004
Rev. 00.06 — 17 December 2008

Time- Out Baud

Interrupt Interrupt
0 Enable Enable Enable RX
RX Line THRE Data
Status Interrupt Available
Interrupt Interrupt
IIR Interrupt ID Reserved ABTOInt ABEOint RO 0x01 U0IIR - 0xE004 5008
Register FIFOs Enabled 0 IIR3 IIR2 IIR1 IIR0 U1IIR - 0xE004 6008

FCR FIFO Control RX Trigger Reserved TX FIFO RX FIFO FIFO WO 0x00 U0FCR - 0xE004 5008
Register Reset Reset Enable U1FCR - 0xE004 6008
LCR Line Control DLAB Set Stick Even Parity Number Word Length Select R/W 0x00 U0LCR - 0xE004 500C
Register Break Parity Parity Enable of Stop U1LCR - 0xE004 600C
Select Bits

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MCR Modem Control Auto Auto - LoopEn OUT2 OUT1 RTS DTR R/W 0x00 U0MCR - 0xE004 5010

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Register CTSen RTSen U1MCR - 0xE004 6010

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LSR Line Status RX TEMT THRE BI FE PE OE DR RO 0x60 U0LSR - 0xE004 5014

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Register FIFO U1LSR - 0xE004 6014

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© NXP B.V. 2008. All rights reserved.

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MSR Modem Status DCD RI DSR CTS Delta Trailing Delta DSR Delta CTS RO 0x00 U0MSR - 0xE004 5018

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Register DCD Edge RI U1MSR - 0xE004 6018

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SCR Scratch Pad 8 bit Data R/W 0x00 U0SCR - 0xE004 501C

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Register U1SCR - 0xE004 601C

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Table 228. UART Register Map ( base address 0xE004 5000 (UART0) and 0xE004 6000 (UART1))
User manual
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Generic Description Bit functions and addresses Acces Reset UARTn Register
Name MSB LSB s value[1 Name & Address
]

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

ACR Auto-baud Reserved [31:10] ABTO IntClr ABEO IntClr R/W 0x00 U0ACR - 0xE004 5020
Control Register Reserved [7:3] Auto Mode Start U1ACR - 0xE004 6020
Reset
FDR Fractional MulVal DivAddVal R/W 0x10 U0FDR - 0xE004 5028
Divider Register U1FDR - 0xE004 6028
TER Transmit Enable TXEN Reserved R/W 0x80 U0TER - 0xE004 5030
Register U1TER - 0xE004 6030
RS485 RS-485 Control Reserved AADEN RXDIS NMMEN R/W 0x00 U0RS485CTRL -
CTRL 0xE004 504C

Chapter 19: LPC29xx Universal Asynchronous FReceiver/Transmitter

U1RS485CTRL -
Rev. 00.06 — 17 December 2008

0xE004 604C
ADR RS-485 address address match value R/W 0x00 U0ADRMATCH -
MATCH match 0xE004 5050
U1ADRMATCH -
0xE004 6050
RS485 RS-485/ RTS/DTR direction control delay value R/W 0x00 U0RS485DLY -
DLY EIA-485 0xE004 5054
direction control U1RS485DLY -
delay 0xE004 6054

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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4.1 UARTn Receiver Buffer Register

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The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains

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the oldest character received and can be read via the bus interface. The LSB (bit 0)

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represents the “oldest” received data bit. If the character received is less than 8 bits, the

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unused MSBs are padded with zeroes.

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The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.

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The UnRBR is always Read Only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.

Table 229. UARTn Receiver Buffer Register (U0RBR - address 0xE004 5000,
U1RBR - 0xE004 6000 when DLAB = 0, Read Only) bit description
Bit Symbol Description Reset Value
7:0 RBR The UARTn Receiver Buffer Register contains the oldest Undefined
received byte in the UARTn Rx FIFO.

4.2 UARTn Transmit Holding Register

The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.

The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always Write Only.

Table 230. UARTn Transmit Holding Register (U0THR - address 0xE004 5000,
U1THR - 0xE004 6000 when DLAB = 0, Write Only) bit description
Bit Symbol Description Reset Value
7:0 THR Writing to the UARTn Transmit Holding Register causes the data NA
to be stored in the UARTn transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.

4.3 UARTn Divisor Latch LSB Register

The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used to divide the APB clock (BASE_UART_CLK) in order to produce the baud rate clock,
which must be 16× the desired baud rate. The UnDLL and UnDLM registers together form
a 16 bit divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains
the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by
zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order
to access the UARTn Divisor Latches.

Table 231. UARTn Divisor Latch LSB Register (U0DLL - address 0xE004 5000,
U1DLL - 0xE004 6000 when DLAB = 1) bit description
Bit Symbol Description Reset Value
7:0 DLLSB The UARTn Divisor Latch LSB Register, along with the UnDLM 0x01
register, determines the baud rate of the UARTn.

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Table 232. UARTn Divisor Latch MSB Register (U0DLM - address 0xE004 5004,

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U1DLM - 0xE004 6004 when DLAB = 1) bit description

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Bit Symbol Description Reset Value

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7:0 DLMSB The UARTn Divisor Latch MSB Register, along with the U0DLL 0x00

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register, determines the baud rate of the UARTn.

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4.4 UARTn Interrupt Enable Register

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The UnIER is used to enable the three UARTn interrupt sources.

Table 233. UARTn Interrupt Enable Register (U0IER - address 0xE004 5004,
U1IER - 0xE004 6004 when DLAB = 0) bit description
Bit Symbol Value Description Reset
Value
0 RBR enables the Receive Data Available interrupt for UARTn. It 0
Interrupt also controls the Character Receive Time-out interrupt.
Enable 0 Disable the RDA interrupts.
1 Enable the RDA interrupts.
1 THRE enables the THRE interrupt for UARTn. The status of this 0
Interrupt can be read from UnLSR[5].
Enable 0 Disable the THRE interrupts.
1 Enable the THRE interrupts.
2 RX Line enables the UARTn RX line status interrupts. The status of 0
Status this interrupt can be read from UnLSR[4:1].
Interrupt 0 Disable the RX line status interrupts.
Enable
1 Enable the RX line status interrupts.
7:3 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
8 ABEOIntEn enables the end of auto-baud interrupt. 0
0 Disable End of Auto-baud Interrupt.
1 Enable End of Auto-baud Interrupt.
9 ABTOIntEn enables the auto-baud time-out interrupt. 0
0 Disable Auto-baud Time-out Interrupt.
1 Enable Auto-baud Time-out Interrupt.
31:10 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

4.5 UARTn Interrupt Identification Register

The UnIIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during
an UnIIR access, the interrupt is recorded for the next UnIIR access.

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Table 234. UARTn Interrupt Identification Register (U0IIR - address 0xE004 5008,

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U1IIR - 0xE004 6008, Read Only) bit description

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Bit Symbol Value Description Reset

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Value

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0 IntStatus Interrupt status. Note that U1IIR[0] is active low. The 1

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pending interrupt can be determined by evaluating

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UnIIR[3:1].

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0 At least one interrupt is pending.
1 No interrupt is pending.
3:1 IntId Interrupt identification. UnIER[3:1] identifies an interrupt 0
corresponding to the UARTn Rx FIFO. All other
combinations of UnIER[3:1] not listed above are reserved
(000,100,101,111).
011 1 - Receive Line Status (RLS).
010 2a - Receive Data Available (RDA).
110 2b - Character Time-out Indicator (CTI).
001 3 - THRE Interrupt
5:4 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
7:6 FIFO Enable These bits are equivalent to UnFCR[0]. 0
8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished 0
successfully and interrupt is enabled.
9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed 0
out and interrupt is enabled.
31:10 - Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.

If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in Table 19–235. Given the status of UnIIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.

The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UARTn Rx input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an UnLSR read.

The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.

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The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn

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Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in

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3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will

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clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has

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been received that is not a multiple of the trigger level size. For example, if a peripheral

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wished to send a 105 character message and the trigger level was 10 characters, the

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CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5

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CTI interrupts (depending on the service routine) resulting in the transfer of the remaining

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5 characters.

Table 235. UARTn Interrupt Handling

U0IIR[3:0] Priority Interrupt Type Interrupt Source Interrupt Reset
value[1]
0001 - None None -
0110 Highest RX Line Status OE[2] or PE[2] or FE[2] or BI[2] UnLSR Read[2]
/ Error
0100 Second RX Data Rx data available or trigger level reached UnRBR Read[3]
Available in FIFO (UnFCR0=1) or UARTn FIFO
drops below
trigger level
1100 Second Character Minimum of one character in the Rx UnRBR Read[3]
Time-out FIFO and no character input or removed
indication during a time period depending on how
many characters are in FIFO and what
the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level
- number of characters) × 8 + 1] RCLKs
0010 Third THRE THRE[2] UnIIR Read (if
source of
interrupt) or
THR write[4]

[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 19–4.9 “UARTn Line Status Register”
[3] For details see Section 19–4.1 “UARTn Receiver Buffer Register”
[4] For details see Section 19–4.5 “UARTn Interrupt Identification Register” and Section 19–4.2 “UARTn
Transmit Holding Register”

The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated
when the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).

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4.6 UARTn FIFO Control Register

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The UnFCR controls the operation of the UARTn Rx and TX FIFOs.

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Table 236. UARTn FIFO Control Register (U0FCR - address 0xE004 5008,

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U1FCR - 0xE004 6008, Write Only) bit description

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Bit Symbol Value Description Reset Value

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0 FIFO Enable 0 UARTn FIFOs are disabled. Must not be used in the 0

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application.
1 Active high enable for both UARTn Rx and TX
FIFOs and UnFCR[7:1] access. This bit must be set
for proper UARTn operation. Any transition on this
bit will automatically clear the UARTn FIFOs.
1 RX FIFO 0 No impact on either of UARTn FIFOs. 0
Reset 1 Writing a logic 1 to UnFCR[1] will clear all bytes in
UARTn Rx FIFO and reset the pointer logic. This bit
is self-clearing.
2 TX FIFO 0 No impact on either of UARTn FIFOs. 0
Reset 1 Writing a logic 1 to UnFCR[2] will clear all bytes in
UARTn TX FIFO and reset the pointer logic. This bit
is self-clearing.
3 DMA mode 1 When in FIFO mode multiple-character transfers are 0
performed until the transmitter FIFO is filled or the
receiver FIFO is empty. The receiver direct-memory
access becomes active when the receive-FIFO
trigger level is reached or a character time-out
occurs
0 Only single-character transfers are done as default
in 450 mode
5:4 - 0 Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit is
not defined.
7:6 RX Trigger These two bits determine how many receiver 0
Level UARTn FIFO characters must be written before an
interrupt is activated.
00 Trigger level 0 (1 character or 0x01)
01 Trigger level 1 (4 characters or 0x04)
10 Trigger level 2 (8 characters or 0x08)
11 Trigger level 3 (14 characters or 0x0E)

4.7 UARTn Line Control Register

The UnLCR determines the format of the data character that is to be transmitted or
received.

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Table 237. UARTn Line Control Register (U0LCR - address 0xE004 500C,

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U1LCR - 0xE004 600C) bit description

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Bit Symbol Value Description Reset

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Value

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1:0 Word Length 00 5 bit character length 0

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Select

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01 6 bit character length

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10 7 bit character length

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11 8 bit character length
2 Stop Bit Select 0 1 stop bit. 0
1 2 stop bits (1.5 if UnLCR[1:0]=00).
3 Parity Enable 0 Disable parity generation and checking. 0
1 Enable parity generation and checking.
5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and 0
the attached parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and
the attached parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6 Break Control 0 Disable break transmission. 0
1 Enable break transmission. Output pin UART0 TXD is
forced to logic 0 when UnLCR[6] is active high.
7 Divisor Latch 0 Disable access to Divisor Latches. 0
Access Bit 1 Enable access to Divisor Latches.
(DLAB)

4.8 UART0/1 Modem Control Register

The U0/1MCR enables the modem loopback mode and controls the modem output
signals.

Table 238: UART0/1 Modem Control Register (U0MCR - address 0xE004 5010,
U1MCR - 0xE004 6010) bit description
Bit Symbol Value Description Reset
value
0 DTR Source for modem output pin, DTR. This bit reads as 0 when 0
Control modem loopback mode is active.
1 RTS Source for modem output pin RTS. This bit reads as 0 when 0
Control modem loopback mode is active.
2 OUT1 inverse control for the UxOUT1 pin. 0
control
3 OUT2 inverse control for the UxOUT2 pin. 0
control

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Table 238: UART0/1 Modem Control Register (U0MCR - address 0xE004 5010,

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U1MCR - 0xE004 6010) bit description

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Bit Symbol Value Description Reset

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value

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4 Loopback The modem loopback mode provides a mechanism to perform 0

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Mode diagnostic loopback testing. Serial data from the transmitter is

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Select connected internally to serial input of the receiver. Input pin,

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RXD1, has no effect on loopback and output pin, TXD is held in

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marking state. The four modem inputs (CTS, DSR, RI and DCD)
are disconnected externally. Externally, the modem outputs (RTS,
DTR) are set inactive. Internally, the four modem outputs are
connected to the four modem inputs. As a result of these
connections, the upper four bits of the MSR will be driven by the
lower four bits of the MCR rather than the four modem inputs in
normal mode. This permits modem status interrupts to be
generated in loopback mode by writing the lower four bits of
U1MCR.
0 Disable modem loopback mode.
1 Enable modem loopback mode.
5 - NA Reserved, user software should not write ones to reserved bits. 0
The value read from a reserved bit is not defined.
6 RTSen 0 Disable auto-rts flow control. 0
1 Enable auto-rts flow control.
7 CTSen 0 Disable auto-cts flow control. 0
1 Enable auto-cts flow control.

4.8.1 Auto-flow control

If auto-RTS mode is enabled the UART0/1‘s receiver FIFO hardware controls the RTS
output of the UART. If the auto-CTS mode is enabled the UART0/1‘s TSR hardware will
only start transmitting if the CTS input signal is asserted.

19.4.8.2 Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the RBR module and is linked to the programmed receiver FIFO trigger level.
If auto-RTS is enabled, the data-flow is controlled as follows:

When the receiver FIFO level reaches the programmed trigger level, RTS is deasserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the deassertion of RTS until after it has begun sending the additional
byte. RTS is automatically reasserted (to a low value) once the receiver FIFO has reached
the previous trigger level. The reassertion of RTS1 signals to the sending UART to
continue transmitting data.

If Auto-RTS mode is disabled, the RTSen bit controls the RTS output of the UART. If
Auto-RTS mode is enabled, hardware controls the RTS output, and the actual value of
RTS will be copied in the RTS Control bit of the UART. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.

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Example: Suppose the UART operating in type 550 has trigger level in FCR set to 0x2

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then if Auto-RTS is enabled the UART will deassert the RTS output as soon as the receive

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FIFO contains 8 bytes. The RTS output will be reasserted as soon as the receive FIFO

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hits the previous trigger level: 4 bytes.

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UART1 TX

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start bits0..7 stop start bits0..7 stop start bits0..7 stop

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~
~
CTS1 pin
~
~
Fig 65. Auto-RTS Functional Timing

19.4.8.3 Auto-CTS
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the TSR module checks CTS input before sending the next data
byte. When CTS is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS signal
does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set, Delta
CTS bit in the MSR will be set though. Table 19–239 lists the conditions for generating a
Modem Status interrupt.

Table 239: Modem status interrupt generation

Enable CTSen CTS Delta CTS Delta DCD or Trailing Edge Modem
Modem (MCR[7]) Interrupt (MSR[0]) RI or Status
Status Enable Delta DSR (MSR[3] or Interrupt
Interrupt (IER[7]) MSR[2] or MSR[1])
(IER[3])
0 x x x x No
1 0 x 0 0 No
1 0 x 1 x Yes
1 0 x x 1 Yes
1 1 0 x 0 No
1 1 0 x 1 Yes
1 1 1 0 0 No
1 1 1 1 x Yes
1 1 1 x 1 Yes

The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result. Figure 19–66
illustrates the Auto-CTS functional timing.

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UART1 TX

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start bits0..7 stop start bits0..7 stop start bits0..7 stop

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~
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CTS1 pin

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Fig 66. Auto-CTS Functional Timing

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While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is deasserted (high). As soon as CTS1 gets
deasserted transmission resumes and a start bit is sent followed by the data bits of the
next character.

4.9 UARTn Line Status Register

The UnLSR is a read-only register that provides status information on the UARTn TX and
RX blocks.

Table 240. UARTn Line Status Register (U0LSR - address 0xE004 5014,
U1LSR - 0xE004 6014, Read Only) bit description
Bit Symbol Value Description Reset
Value
0 Receiver UnLSR0 is set when the UnRBR holds an unread character 0
Data Ready and is cleared when the UARTn RBR FIFO is empty.
(RDR) 0 UnRBR is empty.
1 UnRBR contains valid data.
1 Overrun Error The overrun error condition is set as soon as it occurs. An 0
(OE) UnLSR read clears UnLSR1. UnLSR1 is set when UARTn
RSR has a new character assembled and the UARTn RBR
FIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
0 Overrun error status is inactive.
1 Overrun error status is active.
2 Parity Error When the parity bit of a received character is in the wrong 0
(PE) state, a parity error occurs. An UnLSR read clears UnLSR[2].
Time of parity error detection is dependent on UnFCR[0].
Note: A parity error is associated with the character at the top
of the UARTn RBR FIFO.
0 Parity error status is inactive.
1 Parity error status is active.

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Table 240. UARTn Line Status Register (U0LSR - address 0xE004 5014,

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U1LSR - 0xE004 6014, Read Only) bit description

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Bit Symbol Value Description Reset

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Value

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3 Framing Error When the stop bit of a received character is a logic 0, a 0

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(FE) framing error occurs. An UnLSR read clears UnLSR[3]. The

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time of the framing error detection is dependent on UnFCR0.

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Upon detection of a framing error, the Rx will attempt to

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resynchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the UARTn RBR FIFO.
0 Framing error status is inactive.
1 Framing error status is active.
4 Break When RXDn is held in the spacing state (all 0’s) for one full 0
Interrupt character transmission (start, data, parity, stop), a break
(BI) interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXDn goes to marking state (all
1’s). An UnLSR read clears this status bit. The time of break
detection is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at
the top of the UARTn RBR FIFO.
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter THRE is set immediately upon detection of an empty UARTn 1
Holding THR and is cleared on a UnTHR write.
Register 0 UnTHR contains valid data.
Empty
(THRE)) 1 UnTHR is empty.

6 Transmitter TEMT is set when both UnTHR and UnTSR are empty; TEMT 1
Empty is cleared when either the UnTSR or the UnTHR contain valid
(TEMT) data.
0 UnTHR and/or the UnTSR contains valid data.
1 UnTHR and the UnTSR are empty.
7 Error in RX UnLSR[7] is set when a character with a Rx error such as 0
FIFO framing error, parity error or break interrupt, is loaded into the
(RXFE) UnRBR. This bit is cleared when the UnLSR register is read
and there are no subsequent errors in the UARTn FIFO.
0 UnRBR contains no UARTn RX errors or UnFCR[0]=0.
1 UARTn RBR contains at least one UARTn RX error.

4.10 UART0/1 Modem Status Register

The MSR is a read-only register that provides status information on the modem input
signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct affect
on UART1 operation, they facilitate software implementation of modem signal operations.

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Table 241: UARTn Modem Status Register (U0MSR - address 0xE004 5018,

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U1MSR - 0xE004 6018, Read Only) bit description

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Bit Symbol Value Description Reset

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Value

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0 Delta Set upon state change of input CTS. Cleared on an MSR read. 0

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CTS

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0 No change detected on modem input, CTS.

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1 State change detected on modem input, CTS.

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1 Delta Set upon state change of input DSR. Cleared on an MSR read. 0
DSR 0 No change detected on modem input, DSR.
1 State change detected on modem input, DSR.
2 Trailing Set upon low to high transition of input RI. Cleared on an MSR read. 0
Edge RI 0 No change detected on modem input, RI.
1 Low-to-high transition detected on RI.
3 Delta Set upon state change of input DCD. Cleared on an MSR read. 0
DCD 0 No change detected on modem input, DCD.
1 State change detected on modem input, DCD.
4 CTS Clear To Send State. Complement of input signal CTS. This bit is 0
connected to MCR[1] in modem loopback mode.
5 DSR Data Set Ready State. Complement of input signal DSR. This bit is 0
connected to MCR[0] in modem loopback mode.
6 RI Ring Indicator State. Complement of input RI. This bit is connected 0
to MCR[2] in modem loopback mode.
7 DCD Data Carrier Detect State. Complement of input DCD. This bit is 0
connected to MCR[3] in modem loopback mode.

4.11 UARTn Scratch Pad Register

The UnSCR has no effect on the UARTn operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the UnSCR has occurred.

Table 242. UARTn Scratch Pad Register (U0SCR - address 0xE004 501C,
U1SCR - 0xE004 601C) bit description
Bit Symbol Description Reset
Value
7:0 Pad A readable, writable byte. 0x00

4.12 UARTn Auto-baud Control Register

The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.

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Table 243. UARTn Auto-baud Control Register (U0ACR - 0xE004 5020, U1ACR - 0xE004 6020)

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bit description

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Bit Symbol Value Description Reset value

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0 Start This bit is automatically cleared after auto-baud 0

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completion.

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0 Auto-baud stop (auto-baud is not running).

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1 Auto-baud start (auto-baud is running).Auto-baud run

A
bit. This bit is automatically cleared after auto-baud
completion.
1 Mode Auto-baud mode select bit. 0
0 Mode 0.
1 Mode 1.
2 AutoRestart 0 No restart. 0
1 Restart in case of time-out (counter restarts at next 0
UART0 Rx falling edge)
7:3 - NA Reserved, user software should not write ones to 0
reserved bits. The value read from a reserved bit is not
defined.
8 ABEOIntClr End of auto-baud interrupt clear bit (write only 0
accessible). Writing a 1 will clear the corresponding
interrupt in the UnIIR. Writing a 0 has no impact.
9 ABTOIntClr Auto-baud time-out interrupt clear bit (write only 0
accessible). Writing a 1 will clear the corresponding
interrupt in the UnIIR. Writing a 0 has no impact.
31:10 - NA Reserved, user software should not write ones to 0
reserved bits. The value read from a reserved bit is not
defined.

4.12.1 Auto-baud
The UARTn auto-baud function can be used to measure the incoming baud-rate based on
the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers UnDLM and UnDLL
accordingly.

Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing
the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).

Two auto-baud measuring modes are available which can be selected by the UnACR
Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the
UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significant
bit). In mode 1 the baud-rate is measured between the falling edge and the subsequent
rising edge of the UARTn Rx pin (the length of the start bit).

The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate
measurement will restart at the next falling edge of the UARTn Rx pin.

The auto-baud function can generate two interrupts.

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• The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn

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is set and the auto-baud rate measurement counter overflows).

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• The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn

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is set and the auto-baud has completed successfully).

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The auto-baud interrupts have to be cleared by setting the corresponding UnACR

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ABTOIntClr and ABEOIntEn bits.

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Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UARTn Rx pin baud-rate, but the value of the UnFDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to UnDLM and UnDLL registers should be done before UnACR register write.
The minimum and the maximum baudrates supported by UARTn are function of
BASE_UART_CLK (UARTCLK), number of data bits, stop bits and parity bits.

(1)

2 × UART CLK UART CLK

ratemin = --------------------------------------- ≤ UART n baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratem
16 × 2 15 16 × ( 2 + databits + paritybits + stopbits )

4.12.2 Auto-baud modes

When the software is expecting an ”AT" command, it configures the UARTn with the
expected character format and sets the UnACR Start bit. The initial values in the divisor
latches UnDLM and UnDLM don‘t care. Because of the ”A" or ”a" ASCII coding
(”A" = 0x41, ”a" = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the UnACR Start bit is set, the
auto-baud protocol will execute the following phases:

1. On UnACR Start bit setting, the baud-rate measurement counter is reset and the
UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate.
2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting BASE_UART_CLK cycles optionally pre-scaled
by the fractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the (fractional baud-rate pre-scaled) UARTn input clock,
guaranteeing the start bit is stored in the UnRSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UARTn input clock
(BASE_UART_CLK).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin.
6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched to
normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt
UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the
remaining bits of the ”A/a" character.

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'A' (0x41) or 'a' (0x61)

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start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

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UARTn RX

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start bit LSB of 'A' or 'a'

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U0ACR start

rate counter

16xbaud_rate
16 cycles 16 cycles

a. Mode 0 (start bit and LSB are used for auto-baud)

'A' (0x41) or 'a' (0x61)

start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

UARTn RX
start bit LSB of 'A' or 'a'

U1ACR start

rate counter

16xbaud_rate
16 cycles

b. Mode 1 (only start bit is used for auto-baud)

Fig 67. Autobaud a) mode 0 and b) mode 1 waveform

4.13 UARTn Fractional Divider Register

The UART Fractional Divider Register (U0/1FDR) controls the clock pre-scaler for the
baud rate generation and can be read and written at the user’s discretion. This pre-scaler
takes the APB clock and generates an output clock according to the specified fractional
requirements.

Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.

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Table 244. UARTn Fractional Divider Register (U0FDR - address 0xE004 5028,

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U1FDR - 0xE004 6028) bit description

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Bit Function Value Description Reset

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A
value

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3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0

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0, fractional baud-rate generator will not impact the UARTn

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baudrate.

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7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be 1
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
31:8 - NA Reserved, user software should not write ones to reserved 0
bits. The value read from a reserved bit is not defined.

This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of the UARTs disabled making sure that the
UART is fully software and hardware compatible with UARTs not equipped with this
feature.

The UART baudrate can be calculated as (n = 0/1):

(2)

UARTCLK
UARTn baudrate = ----------------------------------------------------------------------------------------------------------------------------------
16 × ( 256 × UnDLM + UnDLL ) × ⎛ 1 + DivAddVal -----------------------------⎞⎠
⎝ MulVal

Where UARTCLK is the peripheral clock (BASE_UART_CLK), U0/1DLM and U0/1DLL

are the standard UART0/1 baud rate divider registers, and DIVADDVAL and MULVAL are
UART0/1 fractional baudrate generator specific parameters.

The value of MULVAL and DIVADDVAL should comply to the following conditions:

1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL < 15
3. DIVADDVAL<MULVAL

The value of the U0/1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.

If the U0/1FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.

4.13.1 Baudrate calculation

UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.

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Calculating UART

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baudrate (BR)

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PCLK,

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BR

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DL est = PCLK/(16 x BR)

DL est is an True
integer?

False DIVADDVAL = 0
MULVAL = 1
FR est = 1.5

Pick another FR est from

the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est))

FR est = PCLK/(16 x BR x DL est)

False
1.1 < FR est < 1.9?

True

DIVADDVAL = table(FR est )

MULVAL = table(FR est )

DLM = DL est [15:8]

DLL = DLest [7:0]

End
PCLK = BASE_UART_CLK

Fig 68. Algorithm for setting UART dividers

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Table 245. Fractional Divider setting look-up table

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F
FR DivAddVal/ FR DivAddVal/ FR DivAddVal/ FR DivAddVal/

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MulVal MulVal MulVal MulVal

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1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4

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1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13

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1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9

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1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14

A
1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5
1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11
1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6
1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13
1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7
1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15
1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8
1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9
1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10
1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11
1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12
1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13
1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14
1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15

4.13.1.1 Example 1: BASE_UART_CLK = 14.7456 MHz, BR = 9600

According to the the provided algorithm DLest = BASE_UART_CLK/(16 x BR) =
14.7456 MHz / (16 x 9600) = 96. Since this DLest is an integer number, DIVADDVAL = 0,
MULVAL = 1, DLM = 0, and DLL = 96.

4.13.1.2 Example 2: BASE_UART_CLK = 12 MHz, BR = 115200

According to the the provided algorithm DLest = BASE_UART_CLK/(16 x BR) = 12 MHz /
(16 x 115200) = 6.51. This DLest is not an integer number and the next step is to estimate
the FR parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated
and FRest is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified
range of 1.1 and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached
look-up table.

The closest value for FRest = 1.628 in the look-up Table 19–245 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.

Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 19–2 UART’s is 115384. This
rate has a relative error of 0.16% from the originally specified 115200.

4.14 UARTn Transmit Enable Register

The UnTER register enables implementation of software flow control. When TXEn=1,
UARTn transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UARTn transmission will stop.

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Table 19–246 describes how to use TXEn bit in order to achieve software flow control.

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Table 246. UARTn Transmit Enable Register (U0TER - address 0xE004 5030,

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U1TER - 0xE004 6030) bit description

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Bit Symbol Description Reset

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Value

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6:0 - Reserved, user software should not write ones to reserved bits. The NA

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value read from a reserved bit is not defined.

A
7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output 1
on the TXD pin as soon as any preceding data has been sent. If this bit
is cleared to 0 while a character is being sent, the transmission of that
character is completed, but no further characters are sent until this bit is
set again. In other words, a 0 in this bit blocks the transfer of characters
from the THR or TX FIFO into the transmit shift register. Software
implementing software-handshaking can clear this bit when it receives
an XOFF character (DC3). Software can set this bit again when it
receives an XON (DC1) character.

4.15 UART0 RS485 Control register

The U0RS485CTRL register controls the configuration of the UART as an addressable
slave. The addressable slave is one of multiple slaves controlled by a single master.

The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.

Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.

Table 247. UART0 RS485 Control register(U0/2RS485CTRL - 0xE004 504C/0xE004 604C/ bit
description
Bit Symbol Value Description Reset
value
0 NMMEN 0 RS-485 Normal Multidrop Mode (NMM) is 0
enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
1 RS-485 Normal Multidrop Mode (NMM) is
disabled.
1 RXDIS 0 The receiver is enabled. 0
1 The receiver is disabled.
2 AADEN 0 Auto Address Detect (AAD) is disabled. 0
1 Auto Address Detect (AAD) is enabled.
31:3 - - Reserved, user software should not write ones to NA
reserved bits. The value read from a reserved bit
is not defined.

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4.16 UART0 RS485 Address Match register

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Table 248. UART0 RS485 Address Match register (U0/1RS485ADRMATCH -

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0xE004 50450/0xE004 6050) bit description

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Bit Symbol Description Reset value

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7:0 ADRMATCH Contains the address match value. 0x00

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4.17 UART1 RS-485 Delay value register
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.

Table 249. UART1 RS-485 Delay value register (U0/1RS485DLY - 0xE004 50454/0xE004 6054)
bit description
Bit Symbol Description Reset value
7:0 DLY Contains the direction control (RTS or DTR) delay 0x00
value. This register works in conjunction with an 8-bit
counter. <tbd>

4.18 RS-485 modes of operation

RS-485 Normal Multidrop Mode (NMM)

Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.

If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received data bytes will be
ignored and will not be stored in the RXFIFO. When an address byte is detected (parity
bit = ‘1’) it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be
generated. The processor can then read the address byte and decide whether or not to
enable the receiver to accept the following data.

While the receiver is ENABLED (RS485CTRL bit 1 =’0’) all received bytes will be
accepted and stored in the RXFIFO regardless of whether they are data or address. When
an address character is received a parity error interrupt will be generated and the
processor can decide whether or not to disable the receiver.

RS-485 Auto Address Detection (AAD) mode

When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are
set, the UART is in auto address detect mode.

In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.

If the receiver is DISABLED (RS485CTRL bit 1 = ‘1’) any received byte will be discarded if
it is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.

When a matching address character is detected it will be pushed onto the RXFIFO along
with the partiy bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate n Rx Data Ready Interrupt.

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While the receiver is ENABLED (RS485CTRL bit 1 = ‘0’) all bytes received will be

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accepted and stored in the RXFIFO until an address byte which does not match the

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RS485ADRMATCH value is received. When this occurs, the receiver will be automatically

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disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address

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character will not be stored in the RXFIFO.

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RS-485/EIA-485 Auto Direction Control

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RS485/EIA-485 Mode includes the option of allowing the transmitter to automatically
control the state of either the RTS pin or the DTR pin as a direction control output signal.

Setting RS485CTRL bit 4 = ‘1’ enables this feature.

Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use
the DTR pin when RS485CTRL bit 3 = ‘1’.

When Auto Direction Control is enabled, the selected pin will be asserted (driven low)
when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven high) once
the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register.

The RS485CTRL bit 4 takes precedence over all other mechanisms controlling RTS (or
DTR) with the exception of loopback mode.

RS485/EIA-485 driver delay time

The driver delay time is the delay between the last stop bit leaving the TXFIFO and the
de-assertion of RTS (or DTR). This delay time can be programmed in the 8-bit RS485DLY
register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit
times may be programmed.

RS485/EIA-485 output inversion

The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by
programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control
pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction
control pin will be driven to logic 0 after the last bit of data has been transmitted.

5. Architecture
The architecture of the UARTs 0, 1 are shown below in the block diagram.

The APB interface provides a communications link between the CPU or host and the
UART.

The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input.
The UARTn RX Shift Register (UnRSR) accepts valid characters via RXDn. After a valid
character is assembled in the UnRSR, it is passed to the UARTn RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.

The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers
the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register
(UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via the
serial output pin, TXDn.
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The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by

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the UARTn TX block. The UnBRG clock input source is the APB clock

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(BASE_UART_CLK). The main clock is divided down per the divisor specified in the

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UnDLL and UnDLM registers. This divided down clock is a 16x oversample clock,

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NBAUDOUT.

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The interrupt interface contains registers UnIER and UnIIR. The interrupt interface

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receives several one clock wide enables from the UnTX and UnRX blocks.

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Status information from the UnTX and UnRX is stored in the UnLSR. Control information
for the UnTX and UnRX is stored in the UnLCR.

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UnTX

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TXDn
UnTHR UnTSR

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UnBRG

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UnDLL NBAUDOUT

UnDLM RCLK

UnRX
NRXRDY
INTERRUPT
RXDn
UnRBR UnRSR

UnINTR UnIER

UnIIR
UnFCR

UnLSR
UnSCR

UnLCR

PA[2:0]

PSEL

PSTB

PWRITE

APB
PD[7:0] DDIS
INTERFACE

AR

MR

UART_CLK

Fig 69. UART0/1 block diagram

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2. Introduction
The purpose of the Watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The Watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.

The Watchdog is programmed with a time-out value and then periodically restarted. When
the Watchdog times out it generates a reset through the RGU.

To generate Watchdog interrupts in Watchdog debug mode the interrupt has to be

enabled via the interrupt-enable register. A Watchdog-overflow interrupt can be cleared by
writing to the clear-interrupt register.

Another way to prevent resets during debug mode is via the pause feature of the
Watchdog timer. The Watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the Watchdog timer control register is set.

The Watchdog reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset-source register to identify the source when the device has gone through a reset.
See Section 4–3.

3. Watchdog programming example

The Watchdog should be set up for normal or debug mode as follows:

Table 250. Watchdog programming steps

Step Normal mode Debug mode
1 Read from Watchdog key register Read from Watchdog key register
(0x038). Returns value (0x251D8950). (0x038). Returns value (0x251D8950).
2 Write 0x251D8950 (key) to Watchdog Write 0x251D8951 (key exor
timeout register (0x03C). wd_rst_dis) to Watchdog debug register
It is now unlocked. (0x040).
Reset generation is now disabled.
3 Write time-out value (e.g.0x0000FFFF) Write 0x251D8950 (key) to Watchdog
to Watchdog timeout register . timeout register (0x03C).
This indicates time-out reset at 65,536 It is now unlocked.
clock cycles. It is now locked again

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Table 250. Watchdog programming steps

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Step Normal mode Debug mode

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4 Write 0x251D8951 (key exor Write time-out value (e.g.0x0000FFFF)

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counter_enable) to the Watchdog Timer to the Watchdog time-out register.

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Control register. The timer is now started This indicates time-out reset at 65,536

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clock cycles. It is now locked again.

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5 Write 0x251D8950 (key) to the Write 0x251D8951 (key exor

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Watchdog key register (0x038) at counter_enable) to the Watchdog timer
periodical intervals to restart control register. The timer is now started
Timer_Counter.
Write before time-out occurs !
6 - Write 0x251D8950 (key) to the
Watchdog key register (0x038) at
periodical intervals to restart
Timer_Counter.
Write before time-out occurs !

To generate Watchdog interrupts in Watchdog debug mode the interrupt has to be

enabled via the interrupt enable register. A Watchdog overflow interrupt can be cleared by
writing to the clear-interrupt register.

Another way to prevent resets during debug mode is via the pause feature of the
Watchdog timer. The Watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the Watchdog Timer Control register is set.

A Watchdog reset is equal to an external reset: the program counter will start from
0x0000 0000 and registers are cleared. The Reset Generation Unit contains a reset
source register to determine the reset source when the device has gone through a reset.
See Section 4–3.

4. Watchdog register overview

The Watchdog timer registers are shown in Table 20–251.

The timer registers have an offset to the base address WDT RegBase. This can be found
in the memory map, see Section 2–2.

Table 251. Watchdog timer register overview (base address 0xE004 0000)
Address Access Reset value Name Description Reference
offset
000h R/W 0h WTCR Timer control register see
Table 20–252
004h R/W 0000 0000h TC Timer counter value see
Table 20–253
008h R/W 0000 0000h PR Prescale register see
Table 20–254
038h R/W 251D 8950h WD_KEY Watchdog key register see
Table 20–255
03Ch R/W FFFF FFFFh WD_TIMEOUT Watchdog time-out register see
Table 20–256
040h R/W 0000 0000h WD_DEBUG Watchdog debug register see
Table 20–257

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Table 251. Watchdog timer register overview (base address 0xE004 0000)

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Address Access Reset value Name Description Reference

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offset

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FD4h R 0000 00C8h reserved Reserved

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FD8h W 0000 0101h INT_CLR_ENABLE Interrupt clear-enable register see

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Table 10–93

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FDCh W - INT_SET_ENABLE Interrupt set-enable register see

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Table 10–94
FE0h R 0000 0000h INT_STATUS Interrupt status register see
Table 10–95
FE4h R 0000 0000h INT_ENABLE interrupt enable register see
Table 10–96
FE8h W - INT_CLR_STATUS Interrupt clear-status register see
Table 10–97
FECh W - INT_SET_STATUS Interrupt set-status register see
Table 10–98
FFCh R 3012 2900h reserved Reserved

4.1 Watchdog timer-control register

The WTCR is used to control the operation of the timer counter. The Watchdog key - as
stored in the Watchdog Key register - is used to prevent unintentional control. This key
must be XOR-ed with the two control bits so that it is only possible to start the timer by
writing ‘251D 8951h’. All other values are ignored. Resetting the timer (e.g. just before
entering power-down mode) is only possible by writing ‘251D 8952h’. The counting
process starts on CLK_SAFE once the COUNTER_ENABLE bit is set. The process can
be reset by setting the COUNTER_RESET bit. The TC and TR remain in the reset state
for as long as the COUNTER_RESET bit is active.

Table 252. WTCR register bit description (WTCR, address: 0xE004 0000)
* = reset value
Bit Variable name Access Value Description
31 to 3 WD_KEY R/W Protection key, see above. Writes to the
WTCR register are ignored if a value other
than the Watchdog key is written to this
field, read as logic 0
0000
0000h*
2 PAUSE_ENABLE R/W 1 Enables the pause feature of the
Watchdog timer. If this bit is set the
counters (timer and prescale counter) will
be stopped when the ARM processor is in
debug mode (connected to
ARM9_DBGACK)
0*

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Table 252. WTCR register bit description (WTCR, address: 0xE004 0000) …continued

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* = reset value

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Bit Variable name Access Value Description

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1 COUNTER_RESET R/W 1 Reset timer and prescale counter. If this bit

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is set the counters remain reset until it is

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cleared again

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0*

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0 COUNTER_ENABLE R/W 1 Enable timer and prescale counter. If this
bit is set the counters are running
0*

4.2 Watchdog timer counter

The TC represents the timer-count value which is incremented every prescale cycle.
Depending on the prescale register value and the period of CLK_SAFE the contents of
this register can change very rapidly.

Writes to the timer counter register are disabled. Furthermore the timer counter is reset
when the Watchdog keyword is written to the WD_KEY register. The timer counter stops
counting on Watchdog_Time_Out match.

Table 253. TC register bit description (TC, address: 0xE004 0004)

* = reset value
Bit Variable name Access Value Description
31 to 0 TC[31:0] R Watchdog timer counter. It is advisable not to
access this register, which may change very
rapidly
0000
0000h*

4.3 Watchdog prescale register

The prescale register determines the number of clock cycles as a prescale value for the
Watchdog timer counter. When the value is not equal to zero the internal prescale counter
first counts the number of CLK_SAFE cycles as defined in this register plus one, then
increments the TC_value.

Updates to the prescale register are only possible when the timer and prescale counters
are disabled, see bit COUNTER_ENABLE in the TCR register. It is advisable to reset the
timer counters once a new prescale value has been programmed. Writes to this register
are ignored when the timer counters are enabled (bit COUNTER_ENABLE in the TCR
register is set).

Table 254. PR register bit descritpion (PR, address: 0xE004 0008)

* = reset value
Bit Variable name Access Value Description
31 to 0 PR[31:0] R/W Prescale register. This specifies the maximum
value for the prescale counter. The TC
increments after ‘PR+1’ CLK_SAFE cycles
have been counted
0000
0000h*

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4.4 Watchdog timer key register

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The Watchdog timer key register contains a protection code to be used when accessing

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the other Watchdog timer registers to prevent accidental alteration of these registers. The

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value is hard-wired and can only be read, not modified. Writing the key value to this

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register restarts the Timer_Counter, but writing other values has no effect. The Watchdog

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timer must be periodically triggered by correct writes to this register in order to prevent

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Table 255. WD_KEY register bit description (WD_KEY, address: 0xE004 0038)
* = reset value
Bit Variable name Access Value Description
31 to 0 WD_KEY_VAL R/W 251D Key value to be used when accessing
8950h* Watchdog-timer control register

4.5 Watchdog time-out register

The Watchdog time-out register holds the time-out value for Watchdog reset generation.
Timer_Counter counts up to this value and then asserts the Watchdog reset. To prevent
this from happening the user must write the key word to the Watchdog_Key register
before Timer_Counter reaches the programmed value. To be able to write to this register it
must be unlocked first. This is done by first writing to this register the key word as stored in
the Watchdog_Key register. Updating the Watchdog_Time_Out register by unlocking and
writing is also possible when the Watchdog timer has already been enabled (i.e. the
COUNTER_ENABLE bit in the WTCR register is set).

Table 256. WD_TIMEOUT register bit description

* = reset value
Bit Variable name Access Value Description
31 to 0 WD_TIMEOUT_VAL R/W 00FF When the TC matches this value the
FFFFh* Watchdog reset will be asserted

4.6 Watchdog debug register

To debug the Watchdog functionality, generation of a system reset when the Watchdog
timer counter reaches the Wd_Time_Out value must be prevented. When it is enabled an
interrupt can be generated instead. Reset generation on time-out can be blocked by
writing a 1 to the Watchdog reset-disable bit Wd_Rst_Dis.
This is only possible when the upper 31 bits of the data written to the Watchdog_Debug
register are identical to the Watchdog_Key. The Wd_Rst_Dis bit must be XOR-ed with the
Watchdog key. In all other cases writes to this register are ignored.

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Table 257. WD_DEBUG register bit description (WD_DEBUG, address: 0xE004 0040)

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* = reset value

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Bit Variable name Access Value Description

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31 to 1 WD_KEY R/W Protection key, see above. Writes to the

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WD_DEBUG register are ignored if a value

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(WD_KEY_VAL) 251D 8950h* is written to this

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field, read as logic 0

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0000
0000h*
0 WD_RST_DIS R/W 1 Disables generation of a reset on Watchdog
time-out. This feature is used for debug
purposes only
0*

4.7 Watchdog interrupt bit description

Table 20–258 gives the interrupts for the Watchdog subsystem. The first column gives the
bit number in the interrupt registers. For a general explanation of the interrupt concept and
a description of the registers see Section 10–5.

Table 258. Watchdog interrupt sources

Register Interrupt source Description
bit
31 to 9 unused Unused
8 WD Watchdog timer
7 to 0 unused Unused

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1. How to read this chapter

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2. CAN functional description
Figure 21–70 gives a brief overview of the main blocks in the CAN gateway controller.
This consists of two identical CAN controllers working as independent CAN nodes.
Incoming CAN messages can be filtered by the acceptance filter before they reach the
CAN controller. The acceptance filter fetches information on which message should be
filtered from the ID look-up table. The status of all CAN controllers is summarized in the
central CAN status registers.

The CAN controller block, acceptance filter block and ID look-up table RAM are described
in detail in the following sections.

ID Look-up Table
2k SRAM

Acceptance
Filter

CAN Controller 0

CAN Controller 1

Central CAN Status Registers

Fig 70. CAN gateway controller block diagram

3. CAN controller
The CAN controller is a complete serial interface with transmit and receive buffers but
without an acceptance filter. Identifier filtering is done for all CAN channels in a separate
block, see also Section 21–10.
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4. CAN bus timing

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4.1 Baud-rate prescaler

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The period of the CAN system clock, tscl , is programmable and determines individual bit

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timing. The CAN system clock is calculated using the following equation:

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BRP + 1
t scl = ----------------------
fclk ( sys )

BRP is the baud-rate prescaler value defined in the bus timing register CCBT.

4.2 Synchronization jump width

To compensate for phase shifts between the clock oscillators of different bus controllers,
any bus controller must resynchronize on any relevant signal edge of the current
transmission. The synchronization jump-width defines the maximum number of clock
cycles by which a certain bit period can be shortened or lengthened during one
resynchronization:

tsjw = tscl ( SJW + 1 )

SJW is the synchronization jump-width value defined in the bus timing register CCBT.

4.3 Time segments 1 and 2

Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit-period
and the location of the sampling point:

tSYNCSEG = 1tscl

tTSEG1 = tscl ( TSEG1 + 1 )

tTSEG2 = tscl ( TSEG2 + 1 )

TSEG1 and TSEG2 are timing-segment 1 and 2 values defined in CCBT. For
determination of bit-timing parameters see also Ref. 32–5.

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clk(sys)

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t t clk(sys) Baud rate prescaler

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scl

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CAN:

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t SYNCSEG
t TSEG1
t TSEG2

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nominal bit time

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Sync. TSEG1 TSEG2 Sync. TSEG1
Seg. Seg .

e.g. BRP = 00000001b

TSEG1 = 0101b
TSEG2 = 010b

Fig 71. General structure of a bit-period

5. CAN transmit buffers

The CAN controller contains three transmit buffers. Each of these has a length of four
32-bit words and can store one complete CAN message.

The transmit buffer-status bits TBS3, TBS2, TBS1 in the CAN controller status register
CCSTAT signal which of the three transmit buffers is available and ready to be filled with
data for the next transmit messages.

5.1 Transmit buffer layout

The transmit buffers are located in the address range from CANC Base 030h to 05Ch.
The buffer layout is subdivided into message-information, identifier and data registers.

The message info register includes the Tx frame info describing frame format, data length
and whether it is a remote or a data frame. In addition, a Tx priority field allows definition
of a priority for each transmit buffer (see Section 21–5.2 for more details).

The identifier register contains the message ID. Depending on the chosen frame format,
an 11-bit identifier for standard frame format (SFF) or a 29-bit identifier for extended frame
format (EFF) then follows.

Remark: Unused bits in the ID field have to be defined as 0.

Data registers A and B contain the message data bytes.

The number of data fields used in a message is coded with the data-length code DLC in
the message info register. At the start of a remote frame transmission the DLC is not
considered because the RTR bit is 1 (= remote).

This forces the number of transmitted/received data bytes to be 0. The DLC must be
specified correctly to avoid bus errors, which can occur if two CAN controllers
simultaneously start a remote frame transmission with the same identifier. For reasons of
compatibility no DLC greater than eight should be used. If a value greater than eight is
selected, eight bytes are transmitted in the data frame with the DLC specified in the
message info register.

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5.2 Automatic transmit-priority protection

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To allow uninterrupted streams of transmit messages, the CAN controller provides

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automatic transmit-priority detection for all transmit buffers. Depending on the selected

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transmit priority mode (TPM) in the mode register, internal prioritization is based on the

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CAN identifier or a user-defined local priority.

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If more than one message is enabled for transmission (TR=1 or SRR=1) the internal

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transmit-message queue is organized so that the transmit buffer with the lowest CAN
identifier (ID) or the lowest local priority (TXPRIO) is sent first. The result of this internal
scheduling process is taken into account before a new CAN message is sent onto the
bus. This is also true for a retransmission caused by a transmission error or lost
arbitration.

In cases where the same transmit priority or the same ID is chosen for more than one
transmit buffer, the buffer with the lowest number is sent first.

6. CAN receive buffer

The CAN Controller has double receive-buffer architecture which allows the CPU to read
a received message while the next message is being received and stored in the remaining
buffer.

The CAN controller generates a data-overrun condition when both receive buffers are full
of messages and have not been released before a new message arrives and passes
through the acceptance filter. The data-overrun situation is signaled via the DOS bit in the
global status register CCGS and by the data-overrun interrupt DOI (if enabled).

As soon as a received message is read from the receive buffer, the buffer should be
released by setting the release-receive buffer bit RRB in the CAN controller mode register
CCCMD.

6.1 Receive buffer layout

The receive message buffer layout is similar to the transmit message buffer described
above. The identifier, frame format, remote-transmission request bit and data-length code
have the same meanings as those already described.The only differences are the
identifier index IDI and the bypass-mode bit BP in the message info register CCRXBMI.

The identifier index IDI is a 10-bit field in the message info register. It contains the table
position (index number) of the ID look-up table for an accepted and received CAN
message (see Section 21–3 for more details). Software can use this index number to
simplify message transfers from the receive buffer into the standard CPU RAM. The
bypass-mode bit BP is a status bit which signals whether or not a current CAN message
was received in acceptance-filter bypass mode. The acceptance filter can be put into
bypass mode by setting the ACCBP bit in the acceptance-filter mode register CAMODE.

The received data-length code in the message info register represents the received data
length.

Remark: The CAN protocol specification Ref. 32–5 allows transmission of eight data
bytes in conjunction with a data-length code larger than eight. In this case the DLC will not
match the number of data bytes. This should be borne in mind when software uses the
received DLC information from the message info register CCRXBMI.
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7. CAN controller self-test

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The CAN controller supports two options for self-tests:

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• Global self-test: setting the self-reception request bit in normal operating mode

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• Local self-test: setting the self-reception request bit in self-test mode

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Both self-tests use the self-reception feature of the CAN controller. Along with the

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self-reception request the transmitted message is also received and stored in the receive
buffer, so the acceptance filter must be configured accordingly. As soon as the CAN
message is transmitted a transmit and a receive interrupt are generated (if enabled).

7.1 Global self-test

A global self-test can (for example) verify the used configuration in a given CAN system.
As shown in Figure 21–72, at least one other CAN node which acknowledges each CAN
message has to be connected to the CAN bus.

TX
TX Buffer CAN Bus
TXBuffer
Buffer

Transceiver

ack
RX Buffer

Fig 72. Global self-test (example high-speed CAN bus)

Initiating a global self-test is similar to a normal CAN transmission. Transmission of a CAN

message is initiated by setting the self-reception request bit SRR in conjunction with the
selected message-buffer bits STB3, STB2 and STB1 in the CAN controller command
register CCCMD.

7.2 Local self-test

Local self-test can be used for single-node tests. In this case an acknowledge from other
nodes is not needed. As shown in Figure 21–73, a CAN transceiver with an appropriate
CAN bus termination has to be connected.

The CAN controller must be put into self-test mode by setting the STM bit in the CAN
controller mode register CCMODE. Setting the STM bit is only possible when the CAN
controller is in reset mode.

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TX Buffer

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RX Buffer

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Fig 73. Local self-test (example for high-speed CAN bus)

A message transmission is initiated by setting the self-reception request bit SRR in

conjunction with the selected message buffer(s) STB3, STB2 and STB1.

8. CAN global acceptance filter

The global acceptance filter provides a look-up for received identifiers - called acceptance
filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table
memory in which software maintains one to five sections of identifiers. The CAN ID
look-up table memory is 2 kB (512 words, each of 32 bits). It can contain up to 1024
standard frame identifiers (SFFs) or 512 extended frame identifiers (EFFs) or a mixture of
both types. Note that the whole CAN ID look-up table memory is only word-accessible.
The CAN ID look-up table memory is structured into up to five sections, each of which lists
the identifiers of a certain CAN message type (see Table 21–259).

Table 259. CAN ID look-up table memory sections

Name of Section Reception method CAN message Explicit IDs or
frame format group of IDs
Standard Frame Format stored directly in Standard Frame Explicit
FullCAN identifier section memory Format (SFF)
Standard Frame Format buffered Standard Frame Explicit
explicit identifier section Format (SFF)
Standard Frame Format buffered Standard Frame Group
group identifier section Format (SFF)
Extended Frame Format buffered Extended Frame Explicit
explicit identifier section Format (EFF)
Extended Frame Format buffered Extended Frame Group
group identifier section Format (EFF)

Five start -address registers exist to indicate the boundaries of the different sections within
the ID look-up table memory. These registers store the offset for the base address
CANAFM (see Section 2–2). The standard frame-format FullCAN identifier section always
starts at the offset 00h, with the following sections starting as defined in the start-address
registers. The look-up table ends with the FullCAN message object section, which starts
at the offset CAEOTA. A non-existent section is indicated by equal values in consecutive
start-address registers.

See Figure 21–74 for the structure of the CAN ID look-up table memory sections.

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11-BIT index 0 11-BIT index 1

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11-BIT index 2 11-BIT index 3 standard frame

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h entries format FullCAN

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: : identifier section

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11-BIT index (h−2) 11-BIT index (h−1)

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CASFESA 11-BIT index (h) 11-BIT index (h+1)

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standard frame
i entries : : format explicit
identifier section
11-BIT index (h+i−2) 11-BIT index (h+i−1)

CASFGSA 11-BIT index (h+i) LOWER BOUND 11-BIT index (h+i) UPPER BOUND
standard frame
j groups : : format group
identifier section
11-BIT index (h+i+j−1) LOWER BOUND 11-BIT index (h+i+j−1) UPPER BOUND

CAEFESA 29-BIT index (h+i+j)

29-BIT index (h+i+j+1) extended frame

k entries format explicit
: identifier section

29-BIT index (h+i+j+k−1)

CAEFGSA 29-BIT index (h+i+j+k) LOWER BOUND

29-BIT index (h+i+j+k) UPPER BOUND

: extended frame
l groups format group
: identifier section

29-BIT index (h+i+j+k+l−1) LOWER BOUND

29-BIT index (h+i+j+k+l−1) UPPER BOUND

CAEOTA
FullCAN message
object section

001aaa175

Fig 74. ID-look-up table memory

8.1 Standard frame-format FullCAN identifier section

If the CAN controller is set into FullCAN mode (EFCAN = 1) the FullCAN identifier section
in the look-up table is enabled: otherwise the acceptance filter ignores this section. The
entries in the FullCAN identifier section must be arranged in ascending numerical order;
one per half-word and two per word (see Figure 21–74).

Since each CAN controller has its own address map, each table entry also contains the
number of the CAN controller to which it applies. This section starts at the offset 00h and
contains identifiers index 0 to (h-1). The bit allocation is given in Table 21–260.

Table 260. Standard frame-format FullCAN identifier section

Bit Symbol Description
31 to 29 SCC Even index: CAN controller number
28 MDB Even index: message disable bit. Logic 0 is message enabled and
logic 1 is message disabled
27 - Not used
26 to 16 ID[28:18] Even index: 11-bit CAN 2.0 B identifier
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Table 260. Standard frame-format FullCAN identifier section …continued

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Bit Symbol Description

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15 to 13 SCC Odd index: CAN controller number

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12 MDB Odd index: message disable bit. Logic 0 is message enabled and

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logic 1 is message disabled

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11 - Not used

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10 to 0 ID[28:18] Odd index: 11-bit CAN 2.0 B identifier

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If an incoming message is detected the acceptance filter first tries to find the ID in the
FullCAN section, then continues by searching the following sections. In the event of an
identifier match during the acceptance filter process, the received FullCAN message
object data is moved from the receive buffer of the appropriate CAN controller into the
FullCAN message-object section. Table 21–261 shows the detailed layout structure of one
FullCAN message stored in the FullCAN message-object section of the look-up table. The
base address of a specific message-object data can be calculated by the contents of the
CAEOTA and the index i of the ID in the section (see Figure 21–74). Message object data
address = CAEOTA + (12 × i).

Table 261. FullCAN message-object layout

Bit Symbol Description
Msg_ObjAddr + 0
31 FF CAN frame format
30 RTR Remote frame request
29 to 26 - Not used
25 to 24 SEM[1:0] Semaphore bits
23 to 23 - Not used
22 to 16 RXDLC[6:0] Data-length code
15 to 11 - Not used
10 to 0 ID[28:18] Identifier bits 28 to 18
Msg_ObjAddr + 4
31 to 24 RXDATA4[7:0] Receive data 4
23 to 16 RXDATA3[7:0] Receive data 3
15 to 8 RXDATA2[7:0] Receive data 2
7 to 0 RXDATA1[7:0] Receive data 1
Msg_ObjAddr + 8
31 to 24 RXDATA8[7:0] Receive data 8
23 to 16 RXDATA7[7:0] Receive data 7
15 to 8 RXDATA6[7:0] Receive data 6
7 to 0 RXDATA5[7:0] Receive data 5

Since the FullCAN message-object section of the look-up table can be accessed both by
the acceptance filter internal-state machine and by the CPU, there is a method for
ensuring that no CPU reads from a FullCAN message-object occurring while the internal
state-machine is writing to that object. The acceptance filter uses a three-state semaphore
encoded with the two semaphore bits SEM[1:0] for each message object. This
mechanism provides the CPU with information about the current state of acceptance filter
internal-state machine activity in the FullCAN message-object section.

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The semaphore operates in the following manner:

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• SEM[1:0] = 01: Acceptance filter is in the process of updating the buffer

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• SEM[1:0] = 11: Acceptance Filter has finished updating the buffer

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• SEM[1:0] = 00: Either the CPU is in the process of reading from the buffer, or no

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update since last reading from the buffer

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Before writing the first data to a message object SEM[1:0] is set to 01. After having written

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the last data byte into the message object the acceptance filter internal-state machine will
update the semaphore bits by setting SEM[1:0] = 11.

Before reading from a message object, the CPU should read SEM[1:0] to determine the
current state of the message object. If SEM[1:0] = 01, the internal state machine is
currently active in this message object. If SEM[1:0] = 11, the object is available for
reading.

Before the CPU begins reading from the message object it should clear SEM[1:0] = 00,
and when the CPU has finished reading it should check SEM[1:0] again. In the case of
SEM[1:0] unequal to 00, the message object has been changed during reading, so the
contents of the message object should be read out once again. If on the other hand
SEM[1:0] = 00 as expected, this means that the valid data has been successfully read by
the CPU.

Conditions to activate the FullCAN mode:

• The EFCAN bit in the CAMODE register has to be set

• The start-offset address of the standard frame-format explicit identifier section
CASFESA has to be greater than 0
• The available space for the FullCAN message-object section must be large enough to
store one object for any FullCAN identifier

8.2 Standard frame-format explicit identifier section

The entries of the standard frame-format explicit identifier section must be arranged in
ascending numerical order, one per half-word and two per word (see Figure 21–74). Since
each CAN controller has its own address map each entry also contains the number of the
CAN controller to which it applies.

This section starts with the CASFESA start-address register and contains the identifiers
index h to index (h + i − 1). The bit allocation of the first word is given in Table 21–262.

Table 262. Standard frame-format explicit identifier section

Bit Symbol Description
31 to 29 SCC Even index: CAN controller number
28 MDB Even index: message disable bit. Logic 0 is message enabled and
logic 1 is message disabled
27 - Not used
26 to 16 ID[28:18] Even index: 11-bit CAN 2.0 B identifier
15 to 13 SCC Odd index: CAN controller number

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Table 262. Standard frame-format explicit identifier section …continued

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Bit Symbol Description

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12 MDB Odd index: message disable bit. Logic 0 is message enabled and

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logic 1 is message disabled

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11 - Not used

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10 to 0 ID[28:18] Odd index: 11-bit CAN 2.0 B identifier

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By means of the message-disable bits particular CAN identifiers can be turned on and off
dynamically from acceptance filtering. When the acceptance filter function is enabled only
the message-disable bits in the acceptance-filter look-up table memory can be changed
by software. Disabled entries must maintain the ascending sequence of identifiers.

8.3 Standard frame-format group identifier section

The table of the standard frame- format group identifier section contains paired upper and
lower bounds, one pair per word. These pairs must be arranged in ascending numerical
order (see Figure 21–74).

This section starts with the CASFGSA start address register and contains the identifiers
index (h + i) lower bound to index (h + i + j − 1) upper bound. The bit allocation of the first
word is given in Table 21–263.

Table 263. SFF group identifier section

Bit Symbol Description
31 to 29 SCC Lower bound: CAN controller number
28 MDB Lower bound: message disable bit. Logic 0 is message enabled and
logic 1 is message disabled
27 - Not used
26 to 16 ID[28:18] Lower bound: 11-bit CAN 2.0 B identifier
15 to 13 SCC Upper bound: CAN controller number
12 MDB Upper bound: message-disable bit. Logic 0 is message enabled and
logic 1 is message disabled
11 - Not used
10 to 0 ID[28:18] Upper bound: 11-bit CAN 2.0 B identifier

By means of the message-disable bits particular CAN identifier groups can be turned on
and off dynamically from acceptance filtering. When the acceptance-filter function is
enabled only the message-disable bits in the acceptance-filter look-up table memory can
be changed by software. Note that in this section the lower bound and upper bound
message-disable bit must always have the same value. Disabled entries must maintain
the ascending sequence of identifiers.

8.4 Extended frame-format explicit identifier section

If extended identifiers (29-bit) are used they can be configured either in this section or in
the following section. The table of extended frame-format explicit identifiers must be
arranged in ascending numerical order (see Figure 21–74).

This section starts with CAEFESA start-address register and contains the identifiers index
(h + i + j) to index (h + i + j + k − 1). The bit allocation of the first word is given in
Table 21–264.

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Table 264. Extended frame-format explicit identifier section

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Bit Symbol Description

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EFF_GRP_ start address

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31 to 29 SCC CAN controller number

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28 to 0 ID[28:0] 29-bit CAN 2.0 B identifier

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8.5 Extended frame-format group identifier section
The extended frame-format group identifier section must contain an even number of
entries of the same form as in the extended frame-format explicit identifier section (see
Figure 21–74). Like the explicit identifier section, the group identifier section must be
arranged in ascending numerical order. The upper and lower bounds in the section are
implicitly paired as an inclusive group of extended addresses, so that any received
address which falls in the inclusive group is accepted and received. Software must
maintain the section to consist of such word pairs.

This section starts with CAEFGSA start address register and contains the identifiers index
(h + i + j + k) lower bound to index (h + i + j + k + l − 1) upper bound. The bit allocation is
given in Table 21–265.

Table 265. Extended frame-format group identifier section

Bit Symbol Description
CAEFGSA start address
31 to 29 SCC Lower bound: CAN controller number
28 to 0 ID[28:0] Lower bound: 29-bit CAN 2.0 B identifier
CAEFGSA start address + 4
31 to 29 SCC Upper bound: CAN controller number
28 to 0 ID[28:0] Upper bound: 29-bit CAN 2.0 B identifier

8.6 CAN acceptance filter registers

The complete register layout of the CAN acceptance filter is shown in Figure 21–75. Refer
to it for resolving register, register-slice and bit names.

8.7 CAN acceptance-filter mode register

The ACCBP and ACCOFF bits of the acceptance-filter mode register CAMODE are used
for putting the acceptance filter into the bypass- and off-modes respectively. The EFCAN
bit of the mode register can be used to activate FullCAN mode for received 11-bit CAN ID
messages.

Acceptance filter off-mode is typically used during initialization. In this mode an

unconditional access to all registers and the look-up table RAM is possible. CAN
messages are not accepted in acceptance filter off-mode and are therefore not stored in
the receive buffers of active CAN Controllers.

Acceptance filter bypass-mode can be used (for example) to change the acceptance
filter configuration in a running system by changing identifiers in the ID look-up table
memory. Software acceptance filtering has to be used during this reconfiguration.

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Use the ID ready interrupt IDI and the receive interrupt RI. In this mode all CAN messages

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are accepted and stored in the receive buffers of active CAN Controllers.

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With the activated FullCAN Mode, received FullCAN messages are automatically stored

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by the acceptance filter in the FullCAN message-object section (see also Section 21–13

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for more details).

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8.8 Section start-registers of the ID look-up table memory

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Four 12-bit section configuration registers CASFESA, CASFGSA, CAEFESA and
CAEFGSA define the boundaries of the different identifier sections in the ID look-up table
memory (see Figure 21–76). The fifth 12-bit section configuration register, the
end-of-table address register CAEOTA, defines the end of all identifier sections. The
end-of-table address also assigns the start address of the section where FullCAN
message objects (if enabled) are stored. See also the example in Section 21–13.

A write-access to all section configuration registers is only possible during acceptance

filter off- and bypass-modes. Read-access is allowed in all acceptance filter modes.

ID Look-up Table Value: Compare Value: Section:

Section: operand:

FullCAN (Standard Larger than Enabled

Frame Format) CASFESA 000h
Identifier Section Equal Disabled

Explicit Standard Larger than Enabled

Frame Format CASFGSA CASFESA
Identifier Section Equal Disabled

Group of Standard Larger than Enabled

Frame Format CAEFESA CASFGSA
Identifier Section Equal Disabled

Explicit Extended Larger than Enabled

Frame Format CAEFGSA CAEFESA
Identifier Section Equal Disabled

Group of Extended Larger than Enabled

Frame Format CAEOTA CAEFGSA
Identifier Section Equal Disabled

Fig 75. Section configuration register settings

8.9 CAN ID look-up table memory

The CAN identifier look-up table memory can contain explicit CAN identifiers and groups
of identifiers for standard and extended CAN frame formats. These are listed as a table by
source CAN channel (SCC) in ascending order, together with a CAN identifier in each
section.
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Each CAN identifier is linked to an ID Index number (see also Figure 21–76 and

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Figure 21–86). For a CAN identifier match, the matching ID index is stored in the identifier

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index IDI of the message info register CCRXBMI for the appropriate CAN controller (see

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Section 21–6.1 for more details).

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8.10 CAN acceptance-filter search algorithm

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The identifier-screening process of the acceptance filter starts in the following order:

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1. FullCAN (standard frame-format) identifier section
2. Explicit standard frame-format identifier section
3. Group of standard frame-format identifier section
4. Explicit extended frame-format identifier section
5. Group of extended frame-format identifier section

Remark: Only activated sections take part in the screening process.

In cases where equal message identifiers of the same frame format are defined in more
than one section, the first match ends the screening process for this identifier. For
example, if the same source CAN channel in conjunction with the identifier is defined in
the FullCAN, explicit standard frame-format and group of standard frame-format identifier
sections, screening will finish with the match in the FullCAN section.

Message Message
disable bit disable bit

Index 0, 1 SCC = 0 0 ID = 5Ah SCC = 0 0 ... FullCAN

Explicit
Index 2, 3 SCC = 1 0 ... SCC = 2 0 ... Standard
Frame
Index 4, 5 SCC = 3 0 ... SCC = 4 0 ... Format
Identifier
Index 6, 7 SCC = 5 0 ... SCC = 5 0 ... Section

Explicit
Index 8, 9 SCC = 0 0 ID = 5Ah SCC = 0 0 ...
Standard
Frame
Index 10, 11 SCC = 1 0 ... SCC = 2 0 ...
Format
Identifier
Index 12, 13 SCC = 3 0 ... SCC = 4 0 ...
Section

Group of
Index 14 SCC = 0 0 ID = 5Ah SCC = 0 0 ID
ID == 0x5A
5Fh Standard
Frame
Index 15 SCC = 1 0 ... SCC = 1 0 ... Format
Identifier
Section

Fig 76. ID look-up table example explaining the search algorithm

In Figure 21–76, identifiers with their SCC have been defined in the FullCAN, explicit and
group of standard frame-format identifier sections. The identifier 5Ah of Source CAN
Channel 0 is defined in all three sections. With this configuration, incoming CAN
messages on Source CAN Channel 0 with a 5Ah identifier find a match in the FullCAN
section.

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It is possible to disable the 5Ah identifier in the FullCAN section. Then, the screening

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process would be finished with the match in the explicit identifier section.

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The first group in the group identifier section has been defined so that incoming CAN

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messages with identifiers of 5Ah up to 5Fh are accepted on SCC 0. As stated above, the

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identifier 5Ah would find a match in the FullCAN or explicit identifier sections if enabled.

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The rest of the defined identifiers of this group (5Bh to 5Fh) find a match in this group

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identifier section.

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In this way the user can switch dynamically between different filter modes for the same
identifiers.

8.11 CAN central status registers

For easy and fast access, all the CAN controller status bits from each CAN controller
status register are bundled together. For example, the Tx status of all CAN controllers can
be read at once with one 32-bit word access. The status registers are read-only and allow
byte, half-word and word access.

9. CAN register overview

The CAN registers are shown in Table 21–266.

The CAN registers have an offset to the base address CANC/CANAFM/CANAFR or

CANCS RegBase which can be found in the memory map; see Section 2–2.

Table 266. CAN register overview

Address Access Reset value Name Description Reference
offset
CAN controller; CANC RegBase offset (base address 0xE008 0000 (CAN0) , 0xE008 1000
(CAN1))
00h R/W 01h CCMODE CAN controller mode see
register Table 21–267
04h W 00h CCCMD CAN controller command see
register Table 21–268
08h R/W 0000 003Ch CCGS CAN controller global see
status register Table 21–269
0Ch R 0000 0000h CCIC CAN controller interrupt see
and capture register Table 21–270
10h R/W 000h CCIE CAN controller interrupt- see
enable register Table 21–272
14h R/W 1C 0000h CCBT CAN controller bus-timing see
register Table 21–273
18h R/W 60h CCEWL CAN controller error- see
warning limit register Table 21–274
1Ch R 3C 3C3Ch CCSTAT CAN controller status see
register Table 21–275
20h R/W 0000 0000h CCRXBMI CAN controller receive- see
buffer message info Table 21–276
register

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Table 266. CAN register overview …continued

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Address Access Reset value Name Description Reference

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offset

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24h R/W 0000 0000h CCRXBID CAN controller receive- see

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buffer identifier register Table 21–277

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28h R/W 0000 0000h CCRXBDA CAN controller receive- see

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buffer data A register Table 21–278

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2Ch R/W 0000 0000h CCRXBDB CAN controller receive- see
buffer data B register Table 21–279
30h R/W 0000 0000h CCTXB1MI CAN controller transmit- see
buffer 1 message info Table 21–280
register
34h R/W 0000 0000h CCTXB1ID CAN controller transmit- see
buffer 1 identifier register Table 21–281
38h R/W 0000 0000h CCTXB1DA CAN controller transmit- see
buffer 1 data A register Table 21–282
3Ch R/W 0000 0000h CCTXB1DB CAN controller transmit- see
buffer 1 data B register Table 21–283
40h R/W 0000 0000h CCTXB2MI CAN controller transmit- see
buffer 2 message info Table 21–280
register
44h R/W 0000 0000h CCTXB2ID CAN controller transmit- see
buffer 2 identifier register Table 21–281
48h R/W 0000 0000h CCTXB2DA CAN controller transmit- see
buffer 2 data A register Table 21–282
4Ch R/W 0000 0000h CCTXB2DB CAN controller transmit- see
buffer 2 data B register Table 21–283
50h R/W 0000 0000h CCTXB3MI CAN controller transmit- see
buffer 3 message info Table 21–280
register
54h R/W 0000 0000h CCTXB3ID CAN controller transmit- see
buffer 3 identifier register Table 21–281
58h R/W 0000 0000h CCTXB3DA CAN controller transmit- see
buffer 3 data A register Table 21–282
5Ch R/W 0000 0000h CCTXB3DB CAN controller transmit- see
buffer 3 data B register Table 21–283
CAN ID look-up table memory; CANAFM RegBase offset (base adress: 0xE008 5000)
000h to R/W - CAFMEM CAN ID look-up table see
7FCh memory Table 21–288
to
Table 21–291
CAN acceptance filter; CANAFR RegBase offset (base address: 0xE008 7000)
00h R/W 1h CAMODE CAN acceptance-filter see
mode register Table 21–284
04h R/W 000h CASFESA CAN acceptance-filter see
standard frame explicit Table 21–285
start-address register
08h R/W 000h CASFGSA CAN acceptance-filter see
standard frame group start- Table 21–286
address register

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Table 266. CAN register overview …continued

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Address Access Reset value Name Description Reference

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offset

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0Ch R/W 000h CAEFESA CAN acceptance-filter see

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extended frame explicit Table 21–287

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start-address register

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10h R/W 000h CAEFGSA CAN acceptance-filter see

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extended frame group Table 21–288
start-address register
14h R/W 000h CAEOTA CAN acceptance-filter end- see
of-table address register Table 21–289
18h R 000h CALUTEA CAN acceptance-filter see
look-up table error address Table 21–290
register
1Ch R 0h CALUTE CAN acceptance-filter see
look-up table error register Table 21–291
20h R/W 0h FCANIE Global FullCAN Table 21–292
acceptance register
24h R/W 0h FCANIC0 FullCAN interrupt and Table 21–293
capture register 0
28h R/W 0h FCANIC1 FullCAN interrupt and Table 21–294
capture register 1
CAN central status; CANCS RegBase offset (base address: 0xE008 8000)
0h R 030303h CCCTS CAN controllers central see
transmit-status register Table 21–295
4h R 03h CCCRS CAN controllers central see
receive-status register Table 21–296
8h R 0000h CCCMS CAN controllers central see
miscellaneous status Table 21–297
register

Besides the hardware reset value the CAN controller registers have a soft reset mode
value.

• A hardware reset overrules a software reset

• If no soft reset value is specified the content is unchanged by a soft reset
• Bits with a single ’*’ are unchanged on setting the soft reset mode.
The reset value shows the result of a hardware reset, while the soft reset value indicates
the result of a software reset when the RM bit is set either by software or due to a bus-off
condition.

9.1 CAN controller mode register

The CAN controller mode register is used to change the behavior of the CAN controller.

Table 21–267 shows the bit assignment of the CCMODE register.

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Table 267. CCMODE register bit description (CCMODE, address 0xE008 0000 (CAN0) and

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0xE008 1000 (CAN1))

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* = reset value; **both reset value and soft reset mode value

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Bit Symbol Access Value Description

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31 to 6 reserved R - Reserved; do not modify. Read as logic 0

R
A
RPM[1]

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5 R/W Reverse polarity mode

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1 RXDC and TXDC pins are HIGH for a dominant

A
bit
0* RXDC and TXDC pins are LOW for a dominant
bit
4 reserved R - Reserved; do not modify. Read as logic 0
3 TPM[1][2] R/W Transmit priority mode
1 Priority depends on the contents of the transmit
priority register within the transmit buffer
0* Transmit priority depends on the CAN identifier
2 STM[1] R/W Self-test mode
1 The controller will consider a transmitted
message successful if there is no
acknowledgment. Use this state in conjunction
with the self-reception request bit in the CAN
controller command register
0* Transmitted message must be acknowledged
to be considered as successful
1 LOM[1][3] R/W Listen-only mode
1 The controller gives no acknowledgment on
CAN even if a message is successfully
received. Messages cannot be sent, and the
controller operates in error-passive mode
0* The CAN controller acknowledges a
successfully received message
0 RM[4][5] R/W Soft reset mode
1** CAN operation is disabled, and writable
registers can be written to
0 CAN controller operates and certain registers
cannot be written to

[1] A write-access to the RPM, TPM, STM and LOM registers is possible only if soft reset mode has previously
been entered.
[2] In cases where the same transmit priority or the same ID is chosen for more than one buffer, the transmit
buffer with the lowest buffer number is sent first.
[3] This mode of operation forces the CAN controller to be error-passive. Message transmission is not
possible.
[4] During a hardware reset or when the bus status bit is set to 1 (bus-off), the soft reset mode bit is set to 1
(present). After the soft reset mode bit has been set to 0 the CAN controller will wait for:
a) one occurrence of bus-free signal (11 recessive bits) if the preceding reset has been caused by a
hardware reset or a CPU-initiated reset.
b) 128 occurrences of bus-free signal, if the preceding reset has been caused by a CAN controller-initiated
bus-off, before re-entering the bus-on mode
[5] When entering soft reset mode it is not possible to access any other register within the same instruction.

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9.2 CAN controller command register

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The CAN controller command register initiates an action in the transfer layer of the CAN

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controller.

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The CCCMD register is write-only. Table 21–268 shows the bit assignment of the CCCMD

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register.

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Table 268. CAN controller command register bit description (CCCMD, address 0xE008 0004

A
(CAN0) and 0xE008 1004 (CAN1))
Bit Symbol Access Value Description
31 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 STB3 W Select transmit buffer 3
1 Transmit buffer 3 is selected for transmission.
6 STB2 W Select transmit buffer 2
1 Transmit buffer 2 is selected for transmission
5 STB1 W Select transmit buffer 1
1 Transmit buffer 1 is selected for transmission
4 SRR[1][2][3] W Self-reception request
1 A message is transmitted from the selected
transmit buffer and received simultaneously.
Transmission and self-reception request has to
be set simultaneously with STB3, STB2 or
STB1
3 CDO W Clear data overrun
1 The data-overrun bit in the CAN controller
status register is cleared. This command bit is
used to clear the data-overrun condition
signalled by the data-overrun status bit. As long
as the data-overrun status bit is set no further
data-overrun interrupt is generated
2 RRB[4] W Release receive buffer
1 The receive buffer, representing the message
memory space in the double receive buffer, is
released
1 AT[3][5] W Abort transmission
1 If not already in progress, a pending
transmission request for the selected transmit
buffer is cancelled. If the abort-transmission
and transmit-request bits are set in the same
write operation, frame transmission is
attempted once. No retransmission is
attempted if an error is flagged or if arbitration
has been lost
0 TR[2][3][5] W - Transmission request
1 A message from the selected transmit buffer is
queued for transmission

[1] On self-reception request a message is transmitted and simultaneously received if the acceptance filter is
set to the corresponding identifier. A receive and a transmit interrupt indicates correct self-reception (see
also the self-test mode (STM) bit in the mode register; see Table 21–267).

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[2] It is possible to select more than one message buffer for transmission. If more than one buffer is selected

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(TR = 1 or SRR = 1) the internal transmit-message queue is organized so that, depending on the transmit-

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priority mode TPM, the transmit buffer with the lowest CAN identifier (ID) or the lowest 'local priority'

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(TXPRIO) wins the prioritization and is sent first.

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[3] Setting the command bits TR and AT simultaneously results in transmitting a message once. No

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retransmission will be performed in the case of an error or lost arbitration (single-shot transmission). Setting

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the command bits SRR and AT simultaneously results in sending the transmit message once using the

FT
self-reception feature. No retransmission will be performed in the case of an error or lost arbitration. Setting

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the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for

A
TR and AT. Immediately the transmit status bit is set within the status register the internal transmission
request bit is automatically cleared. Setting TR and SRR simultaneously will ignore the set SRR bit.
[4] After reading the contents of the receive buffer the CPU can release this memory space by setting the
RRB bit to 1. This may result in another message becoming immediately available. If there is no other
message available the receive-interrupt bit is reset. If the RRB command is given it will take at least two
internal clock cycles before a new interrupt is generated.
[5] The AT bit is used when the CPU requires suspension of the previously requested transmission; e.g. to
transmit a more urgent message first. A transmission already in progress is not stopped. To see if the
original message has been either transmitted successfully or aborted, the transmission-complete status bit
should be checked. This should be done after the transmit buffer-status bit has been set to 1or a transmit
interrupt has been generated.
[6] If the TR or the SRR bits were set to 1 in a previous command, this cannot be cancelled by resetting the
bits. The requested transmission can only be cancelled by setting the AT bit.

9.3 CAN controller global status register

The CAN controller global status register reflects the global status of the CAN controller
including the transmit and receive error counter values.

Table 21–269 shows the bit assignment of the CCGS register.

Table 269. CCGS register bit description (CCGS, address 0xE008 0008 (CAN0) and 0xE008
1008 (CAN1))
* = reset value; **both reset value and soft reset mode value
Bit Symbol Access Value Description
31 to 24 TXERR[7:0] R/W Transmit error counter. This register reflects the
current value of the transmit error counter. It is
only writable in soft reset mode. If a bus-off
event occurs the transmit error counter is
initialized to 127 to count the minimum
protocol-defined time (128 occurrences of the
bus-free signal). Reading the transmit error
counter during this time gives information about
the status of the bus-off recovery. If bus-off is
active a write-access to the transmit error
counter in the range 0 to 254 clears the bus-off
flag, and the controller waits for one occurrence
of 11 consecutive recessive bits (bus-free) after
clearing the soft reset mode bit
00h*
23 to 16 RXERR[7:0] R/W Receive error counter.This register reflects the
current value of the receive error counter and is
only writable in soft reset mode. If a bus-off
event occurs the receive error counter is
initialized to 00h. As long as the bus-off
condition is valid writing to this register has no
effect
00h*
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Table 269. CCGS register bit description (CCGS, address 0xE008 0008 (CAN0) and 0xE008

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A
1008 (CAN1)) …continued

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FT

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* = reset value; **both reset value and soft reset mode value

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R

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Bit Symbol Access Value Description

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FT

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15 to 8 reserved R - Reserved; do not modify. Read as logic 0

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R
A
7 BS[1] R Bus status

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1 The CAN controller is currently prohibited from

R
A
bus activity because the transmit error counter
has reached its limiting value of FFh
0**
6 ES[2] R Error status
1 One or both of the transmit and receive error
counters has reached the limit set in the error
warning limit register
0**
5 TS[3] R Transmit status
1** The CAN controller is transmitting a message
4 RS[3] R Receive status
1** The CAN controller is receiving a message
3 TCS[4] R Transmission-complete status
1* All requested message transmissions have
completed successfully
0 At least one of the previously requested
transmissions has not yet completed
2 TBS R Transmit-buffer status
1** All transmit buffers are available for the CPU
0 At least one of the transmit buffers contains a
previously queued message that has not yet
been sent
1 DOS[5] R Data-overrun status
1 A message was lost because the preceding
message to this CAN controller was not read
and released quickly enough
0** No data overrun has occurred
0 RBS[6] R Receive-buffer status
1 At least one complete message is available in
the double receive buffer. If no subsequent
received message is available this bit is cleared
by the release receive-buffer command in the
CAN controller command register
0** No message is available in the double receive
buffer

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[1] When the transmit error counter exceeds the limit of 255 the BS bit is set to 1(bus-off), the CAN controller

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R

R
sets the soft reset mode bit to 1 (present) and an error warning interrupt is generated if enabled. Afterwards

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A

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FT
FT

F
the transmit error counter is set to 127 and the receive error counter is cleared. It stays in this mode until the

D
D
CPU clears the soft-reset mode bit. Once this is completed the CAN controller waits the minimum

R
R

A
A
protocol-defined time (128 occurrences of the bus-free signal) counting down the transmit error counter.

FT
FT
After that the BS bit is cleared (bus-on), the error status bit is set to 0 (OK), the error counters are reset and

D
D
R
an error warning interrupt is generated if enabled. Reading the Tx error counter during this time gives

A
FT
information about the status of the bus-off recovery.

D
R
[2] Errors detected during reception or transmission affect the error counters according to the CAN

A
specification. The ES bit is set when at least one of the error counters has reached or exceeded the error-
warning limit. An error-warning interrupt is generated if enabled. The default value of the error-warning limit
after hardware reset is 96 decimal, see also Table 21–274, CCEWL register bits.
[3] If both the RS and the TS bits are 0 (idle) the CAN bus is idle. If both bits are set the controller is waiting to
become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status
is reached. After bus-off this takes 128 detection cycles of 11 consecutive recessive bits.
[4] The TCS bit is set to 0 (incomplete) whenever the transmission request bit or the self -reception request bit
is set to 1 for at least one out of the three transmit buffers. The TCS bit remains 0 until all messages have
been successfully transmitted .
[5] If there is not enough space to store the message within the receive buffer, that message is dropped and
the data-overrun condition is signalled to the CPU the moment the message becomes valid. If this message
is not completed successfully (e.g. because of an error) no overrun condition is signalled.
[6] After reading all messages and releasing their memory space with the command 'release receive buffer'
this bit is cleared.

9.4 CAN controller interrupt and capture register

The CAN controller interrupt and capture register allows the identification of an interrupt
source. Reading the interrupt register clears all interrupt bits except the receive interrupt
bit, which requires the release receive-buffer command. If there is another message
available within the receive buffer after the release receive-buffer command the receive
interrupt is set again: otherwise the receive interrupt stays cleared.

Bus errors are captured in a detailed error report. When a transmitted message loses
arbitration the bit where the arbitration was lost is captured. Once either of these registers
is captured its value remains the same until it is read, after which it is released to capture
a new value.

The CCIC register is read-only. Table 21–270 shows its bit assignment.

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Table 270. CAN controller interrupt and capture register bit description (CCIC, address

R
R

R
A
A

A
0xE008 000C (CAN0) and 0xE008 100C (CAN1))

FT
FT

F
* = reset value; **both reset value and soft reset mode value

D
D

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R

A
A
Bit Symbol Access Value Description

FT
FT

D
D
31 to 29 reserved R - Reserved; do not modify. Read as logic 0

R
A
FT
28 to 24 ALCBIT[4:0] R Arbitration-lost bit. If arbitration is lost while

D
transmitting a message the bit number within

R
A
the frame is captured into this register
00h* Arbitration lost in the first (most significant)
bit of the identifier
: :
0Bh 11: arbitration lost in SRTR bit (RTR bit for
standard-frame messages)
0Ch 12: arbitration lost in IDE bit 13: arbitration
lost in 12th bit of identifier (extended-frame
only)
: :
1Eh 30: arbitration lost in last bit of identifier
(extended-frame only)
1Fh 31: arbitration lost in RTR bit (extended
frames only)
23 and 22 ERRT[1:0] R Error type. The bus error type is captured in
this register
00* Bit error
01 Form error
10 Stuff error
11 Other error
21 ERRDIR R Error direction
1 The bus error is captured during receiving
0* The bus error is captured during transmitting
20 to 16 ERRCC[4:0] R Error-code capture. The location of the error
within the frame is captured in this register;
see Table 21–271
00h*
15 to 11 reserved R - Reserved; do not modify. Read as logic 0
10 TI3 R Transmit interrupt 3
1 Transmit buffer status 3 is released
(transition from logic 0 to logic 1) and the
transmit interrupt-enable 3 is set
0**
9 TI2 R Transmit interrupt 2
1 Transmit buffer status 2 is released
(transition from logic 0 to logic 1) and the
transmit interrupt-enable 2 is set
0**

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Table 270. CAN controller interrupt and capture register bit description …continued(CCIC,

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R

R
A
address 0xE008 000C (CAN0) and 0xE008 100C (CAN1))

A
FT
FT

F
* = reset value; **both reset value and soft reset mode value

D
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R

A
Bit Symbol Access Value Description

FT
FT

D
8 IDI R ID ready interrupt

D
R
A
1 A CAN identifier has been received in

FT
acceptance filter bypass-mode and the ID

D
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A
ready interrupt-enable is set
0**
7 BEI R Bus error interrupt
1 A CAN controller has detected a bus error
and the bus error interrupt-enable is set
0*
6 ALI R Arbitration-lost interrupt
1 The CAN controller has lost arbitration while
attempting to transmit and the arbitration lost
interrupt-enable is set
0**
5 EPI R Error-passive interrupt
1 The CAN controller has reached the error-
passive status (at least one error counter
exceeds the CAN protocol defined level of
127) or if the CAN controller is in error-
passive status and enters error-active status
again, and the error-passive interrupt enable
is set
0**
4 reserved R - Reserved; read as logic 0
3 DOI R Data-overrun interrupt
1 The data-overrun occurred and the data-
overrun interrupt enable is set
0**
2 EWI R Error warning interrupt
1 A change of either the error status or bus
status occurred and the error warning
interrupt-enable is set
0*
1 TI1 R Transmit interrupt 1
1 The transmitter buffer status 1 is released
(transition from logic 0 to logic 1) and the
transmit interrupt-enable 1 is set
0**
0 RI[1] R Receive interrupt
1 The receive-buffer status is logic 1 and the
receive interrupt-enable is set
0**

[1] The RI bit is not cleared on a read-access to the interrupt register. Giving the command ‘Release receive
buffer will clear RI temporarily. If there is another message available within the receive buffer after the

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Table 271. Bus error capture code values

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F
ERRCC [4:0] Function

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0 0000 Reserved

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A

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0 0001 Reserved

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0 0010 Identifier bits 21 to 28

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0 0011 Start of frame

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0 0100 Standard frame RTR bit
0 0101 IDE bit
0 0110 Reserved
0 0111 Identifier bits 13 to 17
0 1000 CRC sequence
0 1001 Reserved bit 0
0 1010 Data field
0 1011 Data-length code
0 1100 Extended-frame RTR bit
0 1101 Reserved bit 1
0 1110 Identifier bits 0 to 4
0 1111 Identifier bits 5 to 12
1 0000 Reserved
1 0001 Active error flag
1 0010 Intermission
1 0011 Tolerate dominant bits
1 0100 Reserved
1 0101 Reserved
1 0110 Passive error flag
1 0111 Error delimiter
1 1000 CRC delimiter
1 1001 Acknowledge slot
1 1010 End of frame
1 1011 Acknowledge delimiter
1 1100 Overload flag
1 1101 Reserved
1 1110 Reserved
1 1111 Reserved

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9.5 CAN controller interrupt-enable register

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The CAN controller interrupt-enable register CCIE enables the different types of CAN

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controller interrupts.

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Table 21–272 shows the bit assignment of the CCIE register.

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Table 272. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008

D
R
0010 (CAN0) and 0xE008 1010 (CAN1))

A
* = reset value
Bit Symbol Access Value Description
31 to 11 reserved R Reserved; do not modify. Read as logic 0
10 TI3E R/W Transmit interrupt-enable 3
1 An interrupt is generated if the transmit buffer
status 3 is released (transition from logic 0 to
logic 1)
0*
9 TI2E R/W Transmit interrupt-enable 2
1 An interrupt is generated if the transmit buffer
status 2 is released (transition from logic 0 to
logic 1)
0*
8 IDIE R/W ID ready interrupt enable
1 An interrupt is generated if a CAN identifier has
been received in acceptance filter bypass
mode.
0*
7 BEIE R/W Bus-error interrupt enable
1 An interrupt is generated if a CAN controller has
detected a bus error
0*
6 ALIE R/W Arbitration-lost interrupt enable
1 An interrupt is generated if the CAN controller
has lost arbitration while attempting to transmit
0*
5 EPIE R/W Error-passive interrupt enable
1 An interrupt is generated if the CAN controller
has reached error-passive status (at least one
error counter exceeds the CAN
protocol-defined level of 127) or if the CAN
controller is in error-passive status and enters
error-active status again
0*
4 reserved R - Reserved; do not modify. Read as logic 0
3 DOIE R/W Data-overrun interrupt enable
1 An interrupt is generated if the data overrun
occurred
0*

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Table 272. CAN controller interrupt-enable register bit descriptioN (CCIE, address 0xE008

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R

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0010 (CAN0) and 0xE008 1010 (CAN1))

A
FT
FT

F
* = reset value

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R

A
Bit Symbol Access Value Description

FT
FT

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2 EWIE R/W Error warning interrupt-enable

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R
A
1 An interrupt is generated if either the error

FT
status or bus status have changed

D
R
A
0*
1 TIE1 R/W Transmit interrupt-enable 1
1 An interrupt is generated if the transmit buffer
status 1 is released (transition from logic 0 to
logic 1)
0*
0 RIE R/W Receive- interrupt enable
1 An interrupt is generated if the receive buffer is
not empty
0*

9.6 CAN controller bus timing register

The CAN controller bus timing register CCBT defines the timing characteristics of the
CAN bus. The register is only writable in soft-reset mode.

Table 21–273 shows the bit assignment of the CCBT register.

Table 273. CAN controller bust timing register bit description (CCBT, address 0xE008 0014
(CAN0) and 0xE008 1014 (CAN1))
* = reset value
Bit Symbol Access Value Description
31 to 24 reserved R - Reserved; do not modify. Read as logic 0
23 SAM R/W 1 The bus is sampled three times.
Recommended for low- or medium-speed
buses where filtering spikes on the bus line
are beneficial.
0* The bus is sampled once. Recommended for
high-speed busses
22 to 20 TSEG2[2:0] R/W Timing segment 2. This is the time segment
after the sample point, determined by the
formula of [1]
1h*
19 to 16 TSEG1[3:0] R/W timing segment 1; time segment before the
sample point which is determined by the
formula of [2]
Ch*
15 and 14 SJW[1:0] R/W Synchronization jump width. The
synchronization jump length is determined by
the formula of [3]
0h*

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Table 273. CAN controller bust timing register bit description (CCBT, address 0xE008 0014

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R

R
A
(CAN0) and 0xE008 1014 (CAN1)) …continued

A
FT
FT

F
* = reset value

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R

A
Bit Symbol Access Value Description

FT
FT

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13 to 10 reserved R - Reserved; do not modify. Read as logic 0

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A
9 to 0 BRP[9:0] R/W Baud-rate prescaler. This derives the CAN

FT
clock tscl from the BASE_IVNSS_CLK

D
R
A
(branch clocks to the CAN controller:
CLK_IVNSS_CANC*)[4]
000h*

[1] tseg2 = tscl × (TSEG2 + 1)

[2] tseg1 = tscl × (TSEG1 + 1)
[3] tsjw = tscl × (SJW + 1)

BRP + 1
[4] t scl = -----------------------
f CLK_CAN

9.7 CAN controller error-warning limit register

The CAN controller error-warning limit register CCEWL sets a limit to the transmit or
receive errors at which an interrupt can occur. This register is only writable in soft-reset
mode.

Table 21–274 shows the bit assignment of the CCEWL register.

Table 274. CAN controller error-warning limit register bit description (CCEWL, address
0xE008 0018 (CAN0) and 0xE008 1018 (CAN1))
* = reset value
Bit Symbol Access Value Description
31 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 to 0 EWL[7:0] R/W Error warning limit. During CAN operation this
value is compared with both the transmit and
receive error counters, and if either counter
matches the value the error status bit is set
60h*

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9.8 CAN controller status register

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The CAN controller status register CCSTAT reflects the transmit status of all three transmit

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buffers, and also the global status of the CAN controller itself.

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A

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FT

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The register is read-only. Table 21–275 shows the bit assignment of the CCSTAT register.

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A
FT
Table 275. CAN controller status register bit description (CCSTAT, address 0xE008 001C

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R
(CAN0) and 0xE008 101C (CAN1))

A
* = reset value; **both reset value and soft reset mode value
Bit Symbol Access Value Description
31 to 24 reserved R - Reserved; do not modify. Read as logic 0
23 BS R Bus status
1 The CAN controller is currently prohibited from
bus activity because the transmit error counter
has reached its limiting value of FFh
0**
22 ES R Error status
1 One or both of the transmit and receive error
counters has reached the limit set in the error
warning-limit register
0**
21 TS3 R Transmit status 3
1** The CAN controller is transmitting a message
from transmit buffer 3
20 RS R Receive status
1** The CAN controller is receiving a message
19 TCS3[1] R Transmission complete status 3
1* The last requested message transmissions
from transmit buffer 3 have been successfully
completed
0 The previously requested transmission is not
yet complete
18 TBS3[2] R Transmit buffer status 3
1** Transmit buffer 3 is available for the CPU
0 Transmit buffer 3 contains a previously queued
message that has not yet been sent
17 DOS R Data-overrun status
1 A message was lost because the preceding
message to this CAN controller was not read
and released quickly enough
0** No data overrun has occurred
16 RBS R Receive buffer status
1 At least one complete message is available in
the double receive buffer. If no subsequent
received message is available this bit is cleared
by the release receive-buffer command in the
CAN controller command register
0** No message is available in the double receive
buffer
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Table 275. CAN controller status register bit description (CCSTAT, address 0xE008 001C

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R

R
A
(CAN0) and 0xE008 101C (CAN1)) …continued

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FT
FT

F
* = reset value; **both reset value and soft reset mode value

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R

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Bit Symbol Access Value Description

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FT

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15 BS R Bus status

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A
1 The CAN controller is currently prohibited from

FT
bus activity because the transmit error counter

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A
has reached its limiting value of FFh
0**
14 ES R Error status
1 One or both of the transmit and receive error
counters has reached the limit set in the error
warning-limit register
0**
13 TS2 R Transmit status 2
1** The CAN controller is transmitting a message
from transmit buffer 2
12 RS R Receive status
1** The CAN controller is receiving a message
11 TCS2[1] R Transmission complete status 2
1* The requested message transmission from
transmit buffer 2 has been successfully
completed
0 The previously requested transmission from
transmit buffer 2 is not yet completed
10 TBS2[2] R Transmit buffer status 2
1** Transmit buffer 2 is available for the CPU
0 Transmit buffer 2 contains a previously queued
message that has not yet been sent
9 DOS R Data-overrun status
1 A message was lost because the preceding
message to this CAN controller was not read
and released quickly enough
0** No data overrun has occurred
8 RBS R Receive buffer status
1 At least one complete message is available in
the double receive buffer. If no subsequent
received message is available this bit is cleared
by the release receive buffer command in the
CAN controller command register
0** No message is available in the double receive
buffer
7 BS R Bus status
1 The CAN controller is currently prohibited from
bus activity because the transmit error counter
has reached its limiting value of FFh
0**

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Table 275. CAN controller status register bit description (CCSTAT, address 0xE008 001C

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A
(CAN0) and 0xE008 101C (CAN1)) …continued

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FT
FT

F
* = reset value; **both reset value and soft reset mode value

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R

A
Bit Symbol Access Value Description

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FT

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6 ES R Error status

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A
1 One or both of the transmit and receive error

FT
counters has reached the limit set in the error

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R
A
warning-limit register
0**
5 TS1 R Transmit status 1
1** The CAN controller is transmitting a message
from transmit buffer 1
4 RS R Receive status
1** The CAN controller is receiving a message
3 TCS1[1] R Transmission-complete status 1
1* The requested message transmission from
transmit buffer 1 has been successfully
completed
0 The previously requested transmission from
transmit buffer 1 has not yet completed
2 TBS1[2] R Transmit-buffer status
1** Transmit buffer 1 is available for the CPU
0 Transmit buffer 1 contains a previously queued
message that has not yet been sent
1 DOS R Data-overrun status
1 A message was lost because the preceding
message to this CAN controller was not read
and released quickly enough
0** No data overrun has occurred
0 RBS R Receive-buffer status
1 At least one complete message is available in
the double receive buffer. If no subsequent
received message is available this bit is cleared
by the release receive-buffer command in the
CAN controller command register
0** No message is available in the double receive
buffer

[1] The TCS1 bit is set to 0 (incomplete) whenever the transmission request bit or the self-reception request bit
is set to 1 for this TX buffer. The TCS1 bit will remain 0 until a message is successfully transmitted.
[2] If the CPU tries to write to this transmit buffer when the TBS1 bit is 0 (locked), the written byte will not be
accepted and will be lost without this being signalled.

9.9 CAN controller receive-buffer message info register

The CAN controller receive-buffer message info register CCRXBMI gives the
characteristics of the received message. This register is only writable in soft-reset mode.

Table 21–276 shows the bit assignment of the CCRXBMI register.

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Table 276. CAN controller receive-buffer message info register bit description (CCRXBMI,

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R

R
A
A

A
address 0xE008 0020 (CAN0) and 0xE008 1020 (CAN1))

FT
FT

F
* = reset value

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R

A
A
Bit Symbol Access Value Description

FT
FT

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31 FF R Frame format

R
A
FT
1 An extended frame-format message has been

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received

R
A
0* A standard frame-format message has been
received
30 RTR R Remote frame request
1 A remote frame has been received
0* A data frame has been received
29 to 20 reserved R - Reserved; do not modify. Read as logic 0
19 to 16 DLC[3:0] R Data-length code. This register contains the
number of data bytes received if bit RTR is
logic 0, or the requested number of data bytes if
bit RTR is logic 1. Values greater than eight are
handled as eight data bytes
0h*
15 to 11 reserved R - Reserved; do not modify. Read as logic 0
10 BP R Bypass mode
1 The message was received in acceptance filter
bypass mode, which makes the identifier index
field meaningless
0*
9 to 0 IDI[9:0] R Identifier index. If bit BP is not set this register
contains the zero-based number of the look-up
table entry at which the acceptance filter
matched the received identifier. Disabled
entries in the standard tables are included in
this numbering, but will not be considered for
filtering
000h*

9.10 CAN controller receive buffer identifier register

The CAN controller receive-buffer identifier register CCRXBID contains the identifier field
of the received message. This register is only writable in soft-reset mode.

Table 21–277 shows the bit assignment of the CCRXBID register.

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Table 277. CAN controller receive buffer identifier register bit description (CCRXBID,

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R

R
A
A

A
address 0xE008 0024 (CAN0) and 0xE008 1024 (CAN1))

FT
FT

F
* = reset value

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R

A
A
Bit Symbol Access Value Description

FT
FT

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31 to 29 reserved R - Reserved; do not modify. Read as logic 0

R
A
FT
28 to 0 ID[28:0] R Identifier register. This contains the

D
identifier of the received CAN message. If

R
A
a standard frame-format message has
been received the 11 least significant bits
represent the 11-bit identifier
0000 0000h*

9.11 CAN controller receive buffer data A register

The CAN controller receive buffer data A register CCRXBDA contains the first four data
bytes of the received message. This register is only writable in soft-reset mode.

Table 21–278 shows the bit assignment of the CCRXBDA register.

Table 278. CAN controller receive buffer data A register bit description (CCRXBDA, address
0xE008 0028 (CAN0) and 0xE008 1028 (CAN1))
* = reset value
Bit Symbol Access Value Description
31 to 24 DB4[7:0] R Data byte 4. If the data-length code value is
four or more this register contains the fourth
data byte of the received message
00h*
23 to 16 DB3[7:0] R Data byte 3. If the data-length code value is
three or more this register contains the third
data byte of the received message
00h*
15 to 8 DB2[7:0] R Data byte 2. If the data-length code value is two
or more this register contains the second data
byte of the received message
00h*
7 to 0 DB1[7:0] R Data byte 1. If the data-length code value is one
or more this register contains the first data byte
of the received message
00h*

9.12 CAN controller receive-buffer data B register

The CAN controller receive buffer data B register CCRXBDB contains the second four
data bytes of the received message. This register is only writable in soft-reset mode.

Table 21–279 shows the bit assignment of the CCRXBDB register.

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Table 279. CAN controller receive-buffer data B register bit description (CCRXBDB, address

R
R

R
A
A

A
0xE008 002C (CAN0) and 0xE008 102C (CAN1))

FT
FT

F
* = reset value

D
D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

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D
31 to 24 DB8[7:0] R Data byte 8. If the data-length code value is

R
A
eight or more this register contains the eighth

FT
data byte of the received message

D
R
A
00h*
23 to 16 DB7[7:0] R Data byte 7. If the data-length code value is
seven or more this register contains the
seventh data byte of the received message
00h*
15 to 8 DB6[7:0] R Data byte 6. If the data-length code value is six
or more this register contains the sixth data
byte of the received message
00h*
7 to 0 DB5[7:0] R Data byte 5. If the data-length code value is five
or more this register contains the fifth data byte
of the received message
00h*

9.13 CAN controller transmit-buffer message info registers

The CAN controller transmit-buffer message info registers CCTXB1MI, CCTXB2MI and
CCTXB3MI each reflect the characteristics of the transmit message. These registers are
only writable when the transmit buffer is released (i.e. corresponding transmit-buffer
status bit is logic 1).

Table 21–280 shows the bit assignment of the CCTXB1MI, CCTXB2MI and CCTXB3MI
registers.

Table 280. CAN controller transmit-buffer message info register bit description
(CCTXB1/2/3MI, addresses 0xE008 0030, 0xE008 0040, 0xE008 0050 (CAN0), and
0xE008 1030, 0xE008 1040, 0xE008 1050 (CAN1))
* = reset value
Bit Symbol Access Value Description
31 FF R/W Frame format
1 An extended frame-format message is
transmitted
0* A standard frame-format message is
transmitted
30 RTR R/W Remote frame request
1 A remote frame-format message is transmitted
0* A data frame-format message is transmitted
29 to 20 reserved R - Reserved; do not modify. Read as logic 0

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A

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Table 280. CAN controller transmit-buffer message info register bit description

D
D

D
R
R

R
A
(CCTXB1/2/3MI, addresses 0xE008 0030, 0xE008 0040, 0xE008 0050 (CAN0), and

A
FT
FT

F
0xE008 1030, 0xE008 1040, 0xE008 1050 (CAN1)) …continued

D
D

R
R
* = reset value

A
A

FT
FT
Bit Symbol Access Value Description

D
D
R
A
19 to 16 DLC[3:0] R/W 0h Data-length code. This register contains the

FT
number of data bytes to be transmitted if bit

D
R
RTR is logic 0, or the requested number of data

A
bytes if bit RTR is logic 1. Values greater than
eight are handled as eight data bytes
0h*
15 to 8 reserved R - Reserved; do not modify. Read as logic 0
7 to 0 TXPRIO[7:0] R/W Transmit priority. If the transmit-priority mode bit
in the CAN controller mode register is set, the
transmit buffer with the lowest transmit-priority
value wins the prioritization and is sent first. In
cases where the same transmit priority or the
same ID is chosen for more than one transmit
buffer, the transmit buffer with the lowest buffer
number is sent first
00h*

9.14 CAN controller transmit-buffer identifier registers

The CAN controller transmit buffer identifier registers CCTXB1ID, CCTXB2ID and
CCTXB3ID contain the identifier field of the transmit message. These registers are only
writable when the transmit buffer is released (i.e corresponding transmit-buffer status bit is
logic 1).

Table 21–281 shows the bit assignment of the CCTXB1ID, CCTXB2ID and CCTXB3ID
registers.

Table 281. CAN controller transmit-buffer identifier register bit description (CCTXB1/2/3ID,
addresses 0xE008 0034, 0xE008 0044, 0xE008 0054 (CAN0), and 0xE008 1034,
0xE008 1044, 0xE008 1054 (CAN1))
* = reset value
Bit Symbol Access Value Description
31 to 29 reserved R - Reserved; do not modify. Read as logic 0
28 to 0 ID[28:0] R/W Identifier register. This contains the
identifier of the transmit CAN message. If
a standard frame-format is transmitted the
11 least significant bits must represent the
11-bit identifier
0000 0000h*

9.15 CAN controller transmit-buffer data A registers

The CAN controller transmit-buffer data A registers CCTXB1DA, CCTXB2DA and
CCTXB3DA contain the first four data bytes of the transmit message. These registers are
only writable when the transmit buffer is released (i.e. corresponding transmit-buffer
status bit is logic 1).

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Table 21–282 shows the bit assignment of the CCTXB1DA, CCTXB2DA and CCTXB3DA

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R
R

R
A
A

A
registers.

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R
Table 282. CAN controller transmit-buffer data A registers register bit description

A
A

FT
FT
(CCTXB1/2/3DA, addresses 0xE008 0038, 0xE008 0048, 0xE008 0058 (CAN0), and

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D
0xE008 1038, 0xE008 1048, 0xE008 1058 (CAN1))

R
A
* = reset value

FT
D
Bit Symbol Access Value Description

R
A
31 to 24 DB4[7:0] R/W Data byte 4. If the data-length code value is
four or more this register contains the fourth
data byte of the received message
00h*
23 to 16 DB3[7:0] R/W Data byte 3. If the data length code value is
three or more this register contains the third
data byte of the received message
00h*
15 to 8 DB2[7:0] R/W Data byte 2. If the data-length code value is two
or more this register contains the second data
byte of the received message
00h*
7 to 0 DB1[7:0] R/W Data byte 1. If the data-length code value is one
or more this register contains the first data byte
of the received message
00h*

9.16 CAN controller transmit-buffer data B registers

The CAN controller transmit-buffer data B registers CCTXB1DB, CCTXB2DB and
CCTXB3DB contain the second four data bytes of the transmit message. These registers
are only writable when the transmit buffer is released (i.e the corresponding transmit-
buffer status bit is logic 1).

Table 21–283 shows the bit assignment of the CCTXB1DB, CCTXB2DB and CCTXB3DB
registers.

Table 283. CAN controller transmit-buffer data B register bit description (CCTX1/2/3DB,
addresses 0xE008 003C, 0xE008 004C, 0xE008 005C (CAN0), and 0xE008 103C,
0xE008 104C, 0xE008 105C (CAN1))
* = reset value
Bit Symbol Access Value Description
31 to 24 DB8[7:0] R/W Data byte 8. If the data -length code value is
eight or more this register contains the eighth
data byte of the received message
00h*
23 to 16 DB7[7:0] R/W Data byte 7. If the data-length code value is
seven or more this register contains the
seventh data byte of the received message
00h*

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Table 283. CAN controller transmit-buffer data B register bit description (CCTX1/2/3DB,

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R

R
A
addresses 0xE008 003C, 0xE008 004C, 0xE008 005C (CAN0), and 0xE008 103C,

A
FT
FT

F
0xE008 104C, 0xE008 105C (CAN1)) …continued

D
D

R
R
* = reset value

A
A

FT
FT
Bit Symbol Access Value Description

D
D
R
A
15 to 8 DB6[7:0] R/W Data byte 6. If the data-length code value is six

FT
or more this register contains the sixth data

D
R
byte of the received message

A
00h*
7 to 0 DB5[7:0] R/W Data byte 5. If the data-length code value is five
or more this register contains the fifth data byte
of the received message
00h*

10. CAN acceptance-filter register overview

10.1 CAN acceptance-filter mode register

The CAN acceptance-filter mode register CAMODE is used to change the behavior of the
acceptance filter.

Table 21–284 shows the bit assignment of the CAMODE register.

Table 284. CAN acceptance-filter mode register bit description (CAMODE, address
0xE008 7000)
* = reset value
Bit Symbol Access Value Description
31 to 3 reserved R - Reserved; do not modify. Read as logic 0
2 EFCAN R/W FullCAN extension mode
1 FullCAN functionality is enabled
0* FullCAN functionality is disabled
1 ACCBP R/W Acceptance filter bypass
1 All Rx messages are accepted on enabled CAN
controller. Software must set this bit before
modifying the contents of any of the acceptance-
filter registers, and before modifying the contents
of look-up table RAM in any other way than setting
or clearing the disable bits in standard-identifier
entries
0* When both this bit and bit ACCOFF are logic 0,
the acceptance filter operates to screen received
CAN identifiers
0 ACCOFF R/W Acceptance filter off
1* If bit ACCBP = 0 the acceptance filter is not
operational and all received CAN messages are
ignored
0 The acceptance filter is operational

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10.2 CAN acceptance-filter standard-frame explicit start-address register

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F
The CAN acceptance filter standard-frame explicit start-address register CASFESA

D
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R
defines the start address of the section of explicit standard identifiers in the

A
A

FT
FT
acceptance-filter look-up table. It also indicates the size of the section of standard

D
D
identifiers which the acceptance filter will search.

R
A
FT
Table 21–285 shows the bit assignment of the CASFESA register.

D
R
A
Table 285. CAN acceptance-filter standard-frame explicit start-address register bit
description (CASFESA, address 0xE008 7004)
* = reset value
Bit Symbol Access Value Description
31 to 12 reserved R - Reserved; do not modify. Read as logic 0
11 to 2 SFESA[9:0] R/W Standard-frame explicit start-address. This
register defines the start address of the section of
explicit standard identifiers in acceptance filter
look-up table. If the section is empty, write the
same value into this register and the SFGSA
register. If bit EFCAN = 1, this value also indicates
the size of the section of standard identifiers which
the acceptance filter will search and (if found)
automatically store received messages from in the
acceptance-filter section. Write access is only
possible during acceptance-filter bypass or
acceptance-filter off modes. Read access is
possible in acceptance-filter on and off modes.
The standard-frame explicit start address is
aligned on word boundaries, and therefore the
lowest two bits must be always be logic 0
00h*
1 to 0 reserved R - Reserved; do not modify. Read as logic 0

10.3 CAN acceptance-filter standard-frame group start-address register

The CAN acceptance-filter standard-frame group start-address register CASFGSA
defines the start address of the section of grouped standard identifiers in the acceptance-
filter look-up table.

Table 21–286 shows the bit assignment of the CASFGSA register.

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Table 286. CAN acceptance-filter standard-frame group start-address register bit description

R
R

R
A
A

A
(CASFGSA, address 0xE008 7008)

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F
* = reset value

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D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

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D
31 to 12 reserved R - Reserved; do not modify. Read as logic 0

R
A
FT
11 to 2 SFGSA[9:0] R/W Standard-frame group start address. This register

D
defines the start address of the section of grouped

R
A
standard identifiers in the acceptance-filter
look-up table. If this section is empty, write the
same value in this register and the EFESA
register. The largest value that should be written
to this register is 7FCh when only the standard
explicit section is used and the last word (address
7F8h) in the acceptance-filter look-up table is
used. Write access is only possible during
acceptance-filter bypass or acceptance-filter off
modes; read access is possible in acceptance-
filter on and off modes.
The standard-frame group start address is aligned
on word boundaries and therefore the lowest
two bits must be always logic 0
00h*
1 to 0 reserved R - Reserved; do not modify. Read as logic 0

10.4 CAN acceptance-filter extended-frame explicit start-address register

The CAN acceptance-filter extended-frame explicit start-address register CAEFESA
defines the explicit start address of the section of extended identifiers in the acceptance-
filter look-up table.

Table 21–287 shows the bit assignment of the CAEFESA register.

Table 287. CAEFESA register bit description (CAEFESA, address 0xE008 700C)
* = reset value
Bit Symbol Access Value Description
31 to 12 reserved R - Reserved; do not modify. Read as logic 0

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Table 287. CAEFESA register bit description (CAEFESA, address 0xE008 700C) …continued

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D

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R
R

R
A
* = reset value

A
FT
FT

F
Bit Symbol Access Value Description

D
D

R
R

A
A
11 to 2 EFESA[9:0] R/W Extended-frame explicit start address. This

FT
FT

D
register defines the start address of the section of

D
R
A
explicit extended identifiers in acceptance-filter

FT
look-up table. If the section is empty write the

D
R
same value in this register and the EFGSA

A
register. The largest value that should be written
to this register is 7FCh, when both extended
sections are empty and the last word (address
7F8h) in the acceptance-filter look-up table is
used. Write access is only possible in acceptance-
filter bypass or acceptance-filter off modes. Read
access is possible in acceptance-filter on and off
modes.
The extended-frame explicit start-address is
aligned on word boundaries, and therefore the
lowest two bits must be always logic 0
00h*
1 and 0 reserved R - Reserved; do not modify. Read as logic 0

10.5 CAN acceptance-filter extended-frame group start-address register

The CAN acceptance filter extended frame group start address register CAEFGSA
defines the start address of the section of grouped extended-frame identifiers in the
acceptance-filter look-up table.

Table 21–288 shows the bit assignment of the CAEFGSA register.

Table 288. CAN acceptance-filter extended-frame group start-address register bit

description (CAEFGSA, address 0xE008 7010)
* = reset value
Bit Symbol Access Value Description
31 to 12 reserved R - Reserved; do not modify. Read as logic 0
11 to 2 EFGSA[9:0] R/W Extended-frame group start-address. This register
defines the start address of the section of grouped
extended identifiers in the acceptance-filter
look-up table. If the section is empty write the
same value in this register and the EOTA register.
The largest value that should be written to this
register is 7FCh when the section is empty and
the last word (address 7F8h) in the acceptance-
filter look-up table is used. Write access is only
possible in acceptance-filter bypass or
acceptance-filter off modes. Read access is
possible in acceptance-filter on and off modes.
The extended-frame group start-address is
aligned on word boundaries, and therefore the
lowest two bits must be always logic 0.
00h*
1 to 0 reserved R - Reserved; do not modify. Read as logic 0

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10.6 CAN acceptance-filter end of look-up table address register

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F
The CAN acceptance filter end of look-up table address register CAEOTA contains the

D
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R
end-address of the acceptance-filter look-up table.

A
A

FT
FT

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D
Table 21–289 shows the bit assignment of the CAEOTA register.

R
A
FT
Table 289. CAN acceptance-filter end of look-up table address register bit description

D
R
(CAEOTA, address 0xE008 7014)

A
* = reset value
Bit Symbol Access Value Description
31 to 12 reserved R - Reserved; do not modify. Read as logic 0
11 to 2 EOTA[9:0] R/W End of look-up table address. The largest value of
the register CAEOTA should never exceed 7FC.
If bit EFCAN = 0 the register should contain the
next address above the last active acceptance-
filter identifier section;
If bit EFCAN = 1 the register contains the start
address of the FullCAN message object section.
In the case of an identifier match in the standard
frame-format FullCAN identifier section during
acceptance filtering, the received FullCAN
message object data is moved from the receive
buffer of the appropriate CAN Controller into the
FullCAN message object section. Each defined
FullCAN Message needs three address lines for
the message data in the FullCAN message object
data section. Write access is only possible in
acceptance-filter bypass or acceptance-filter off
modes. Read access is possible in acceptance-
filter on and off modes.
00h*
1 to 0 reserved R - Reserved; do not modify. Read as logic 0

10.7 CAN acceptance filter look-up table error address register

The CAN acceptance filter look-up table error address register CALUTEA represents the
address in the look-up table at which a problem has been detected when the look-up table
error bit is set.

The CALUTEA register is read-only. Table 21–290 shows the bit assignment of the
CALUTEA register.

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Table 290. CAN acceptance-filter look-up table error address register bit description

R
R

R
A
A

A
(CALUTEA, address 0xE008 7018)

FT
FT

F
* = reset value

D
D

R
R

A
A
Bit Symbol Access Value Description

FT
FT

D
D
31 to 11 reserved R - Reserved; do not modify. Read as logic 0

R
A
FT
10 to 2 LUTEA[8:0] R Look-up table error address. This register

D
contains the address in the look-up table at which

R
A
the acceptance filter encountered an error in the
content of the tables. It is valid when the look-up
table error bit is set. Reading this register clears
the look-up table error bit LUTE
00h*
1 and 0 reserved R - Reserved; do not modify. Read as logic 0

10.8 CAN acceptance-filter look-up table error register

The CAN acceptance filter look-up table error register CALUTE provides the configuration
status of the look-up table contents. In the event of an error an interrupt is generated via
the general CAN-interrupt input source of the Vectored Interrupt Controller.

The CALUTE register is read-only. Table 21–291 shows the bit assignment of the
CALUTE register.

Table 291. CAN acceptance-filter look-up table error register bit description (CALUTE,
address 0xE008 701C)
* = reset value
Bit Symbol Access Value Description
31 to 1 reserved R - Reserved; do not modify. Read as logic 0
0 LUTE R Look-up table error
1 The acceptance filter has encountered an error in
the contents of the look-up table. Reading the
LUTEA register clears this bit. This error condition
is part of the general CAN-interrupt input source
0*

10.9 Global FullCANInterrupt Enable register

A write access to the Global FullCAN Interrupt Enable register is only possible when the
Acceptance Filter is in the off mode.

Table 292. Global FullCAN Enable register (FCANIE - address 0xE008 7020) bit description
Bit Symbol Description Reset
Value
0 FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. 0
31:1 - Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

10.10 FullCAN Interrupt and Capture registers

For detailed description on these two registers, see Section 21–11.

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Table 293. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE008 7024) bit

R
R

R
A
A

A
description

FT
FT

F
D
D
Bit Symbol Description Reset

R
R

A
A
Value

FT
FT

D
D
0 IntPnd0 FullCan Interrupt Pending bit 0. 0

R
A
FT
... IntPndx (0<x<31) FullCan Interrupt Pending bit x. 0

D
R
31 IntPnd31 FullCan Interrupt Pending bit 31. 0

A
Table 294. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0xE008 7028) bit
description
Bit Symbol Description Reset
Value
0 IntPnd32 FullCan Interrupt Pending bit 32. 0
... IntPndx (32<x<63) FullCan Interrupt Pending bit x. 0
31 IntPnd63 FullCan Interrupt Pending bit 63. 0

10.11 CAN controller central transmit-status register

The CAN controller central transmit-status register CCCTS provides bundled access to
the transmission status of all the CAN controllers. The status flags are the same as those
in the status register of the corresponding CAN controller.

The CCCTS register is read-only. Table 21–295 shows the bit assignment of the CCCTS
register.

Table 295. CAN controller central transmit-status register bit description

* = reset value
Bit Symbol Access Value Description
31 to 18 reserved R - Reserved; do not modify. Read as logic 0
17 TCS1 R CAN controller 1 transmission-completed status
1* Transmission was successfully completed
16 TCS0 R CAN controller 0 transmission-completed status
1* Transmission was successfully completed
15 to 10 reserved R - Reserved; do not modify. Read as logic 0
9 TBS1 R CAN controller 1 transmit-buffer status
1* Transmit buffers are empty
8 TBS0 R CAN controller 0 transmit-buffer status
1* Transmit buffers are empty
7 to 2 reserved R - Reserved; do not modify. Read as logic 0
1 TS1 R CAN controller 1 transmit status
1* A message is being transmitted
0 TS0 R CAN controller 0 transmit status
1* A message is being transmitted

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10.12 CAN controller central receive-status register

D
D

D
R
R

R
A
A

A
FT
FT

F
The CAN controller central receive-status register CCCRS provides bundled access to the

D
D

R
reception status of all CAN controllers. The status flags are the same as those in the

A
A

FT
FT
status register of the corresponding CAN controller.

D
D
R
A
The CCCRS register is read only. Table 21–296 shows the bit assignment of the CCCRS

FT
register.

D
R
A
Table 296. CAN controller central receive-status register bit description
* = reset value
Bit Symbol Access Value Description
31 to 18 reserved R - Reserved; do not modify. Read as logic 0
17 DOS1[1] R CAN controller 1 data-overrun status
1 Received message was lost due to slow read-out
of the preceding message
0*
16 DOS0[1] R CAN controller 0 data-overrun status
1 Received message was lost due to slow read-out
of the preceding message
0*
15 to 10 reserved R - Reserved; do not modify. Read as logic 0
9 RBS1[1] R CAN controller 1 receive-buffer status
1 Receive buffers contain a received message
0*
8 RBS0[1] R CAN controller 0 receive-buffer status
1 Receive buffers contain a received message
0*
7 to 2 reserved R - Reserved; do not modify. Read as logic 0
1 RS1 R CAN controller 1 receive status
1* A message is being received
0 RS0 R CAN controller 0 receive status
1* A message is being received

[1] This bit is unchanged if a FullCAN message is received.

10.13 CAN controller central miscellaneous-status register

The CAN controller central miscellaneous-status register CCCMS provides bundled
access to the bus and error status of all the CAN controllers. The status flags are the
same as those in the status register of the corresponding CAN controller.

The CCCMS register is read only. Table 21–297 shows the bit assignment of the CCCMS
register.

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Table 297. CAN controller central miscellaneous-status register bit description

R
R

R
A
A

A
* = reset value

FT
FT

F
D
D
Bit Symbol Access Value Description

R
R

A
A

FT
FT
31 to 10 reserved R - Reserved; do not modify. Read as logic 0

D
D
R
9 BS1 R CAN controller 1 bus status

A
FT
1 The CAN controller is currently prohibited from

D
R
bus activity because the transmit error counter

A
has reached its limiting value of FFh
0*
8 BS0 R CAN controller 0 bus status
1 The CAN controller is currently prohibited from
bus activity because the transmit error counter
has reached its limiting value of FFh
0*
7 to 2 reserved R - Reserved; do not modify. Read as logic 0
1 ES1 R CAN controller 1 error status
1 The error warning limit has been exceeded
0*
0 ES0 R CAN controller 0 error status
1 The error warning limit has been exceeded
0*

11. FullCAN mode

The FullCAN mode is based on capabilities provided by the CAN Gateway module used in
the LPC2000 family of products. This block uses the Acceptance Filter to provide filtering
for both CAN channels.

The concept of the CAN Gateway block is mainly based on a BasicCAN functionality. This
concept fits perfectly in systems where a gateway is used to transfer messages or
message data between different CAN channels. A BasicCAN device is generating a
receive interrupt whenever a CAN message is accepted and received. Software has to
move the received message out of the receive buffer from the according CAN controller
into the user RAM.

To cover dashboard like applications where the controller typically receives data from
several CAN channels for further processing, the CAN Gateway block was extended by a
so-called FullCAN receive function. This additional feature uses an internal message
handler to move received FullCAN messages from the receive buffer of the according
CAN controller into the FullCAN message object data space of Look-up Table RAM.

When fullCAN mode is enabled, the Acceptance Filter itself takes care of receiving and
storing messages for selected Standard ID values on selected CAN buses, in the style of
“FullCAN” controllers.

In order to set this bit and use this mode, two other conditions must be met with respect to
the contents of Acceptance Filter RAM and the pointers into it:

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• The Standard Frame Individual Start Address Register (SFF_sa) must be greater than

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or equal to the number of IDs for which automatic receive storage is to be done, times

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two. SFF_sa must be rounded up to a multiple of 4 if necessary.

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• The EndOfTable register must be less than or equal to 0x800 minus 6 times the

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SFF_sa value, to allow 12 bytes of message storage for each ID for which automatic

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receive storage will be done.

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When these conditions are met and eFCAN is set:

A
• The area between the start of Acceptance Filter RAM and the SFF_sa address, is
used for a table of individual Standard IDs and CAN Controller/bus identification,
sorted in ascending order and in the same format as in the Individual Standard ID
table. Entries can be marked as “disabled” as in the other Standard tables. If there are
an odd number of “FullCAN” ID’s, at least one entry in this table must be so marked.
• The first (SFF_sa)/2 IDindex values are assigned to these automatically-stored ID’s.
That is, IDindex values stored in the Rx Frame Status Register, for IDs not handled in
this way, are increased by (SFF_sa)/2 compared to the values they would have when
eFCAN is 0.
• When a Standard ID is received, the Acceptance Filter searches this table before the
Standard Individual and Group tables.
• When a message is received for a controller and ID in this table, the Acceptance filter
reads the received message out of the CAN controller and stores it in Acceptance
Filter RAM, starting at (EndOfTable) + its IDindex*12.
• The format of such messages is shown in Table 21–298.

11.1 FullCAN message layout

Table 298. Format of automatically stored Rx messages
Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 F R 0000 SEM 0000 DLC 00000 ID.28 ... ID.18

F T [1:0]
R
+4 Rx Data 4 Rx Data 3 Rx Data 2 Rx Data 1
+8 Rx Data 8 Rx Data 7 Rx Data 6 Rx Data 5

The FF, RTR, and DLC fields are as described in Table 21–276.

Since the FullCAN message object section of the Look-up table RAM can be accessed
both by the Acceptance Filter and the CPU, there is a method for insuring that no CPU
reads from FullCAN message object occurs while the Acceptance Filter hardware is
writing to that object.

For this purpose the Acceptance Filter uses a 3-state semaphore, encoded with the two
semaphore bits SEM1 and SEM0 (see Table 21–298 “Format of automatically stored Rx
messages”) for each message object. This mechanism provides the CPU with information
about the current state of the Acceptance Filter activity in the FullCAN message object
section.

The semaphore operates in the following manner:

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Table 299. FullCAN semaphore operation

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SEM1 SEM0 activity

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0 1 Acceptance Filter is updating the content

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1 1 Acceptance Filter has finished updating the content

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0 0 CPU is in process of reading from the Acceptance Filter

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Prior to writing the first data byte into a message object, the Acceptance Filter will write

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the FrameInfo byte into the according buffer location with SEM[1:0] = 01.

After having written the last data byte into the message object, the Acceptance Filter will
update the semaphore bits by setting SEM[1:0] = 11.

Before reading a message object, the CPU should read SEM[1:0] to determine the current
state of the Acceptance Filter activity therein. If SEM[1:0] = 01, then the Acceptance Filter
is currently active in this message object. If SEM[1:0] = 11, then the message object is
available to be read.

Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00.

When the CPU is finished reading, it can check SEM[1:0] again. At the time of this final
check, if SEM[1:0] = 01 or 11, then the Acceptance Filter has updated the message object
during the time when the CPU reads were taking place, and the CPU should discard the
data. If, on the other hand, SEM[1:0] = 00 as expected, then valid data has been
successfully read by the CPU.

Figure 21–77 shows how software should use the SEM field to ensure that all three words
read from the message are all from the same received message.

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START

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read 1st word

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SEM == 01?

this message has not been

SEM == 11?
received since last check

clear SEM, write back 1st word

read 2nd and 3rd words

read 1st word

SEM == 00?

most recently read 1st, 2nd, and

3rd words are from the same
message

Fig 77. Semaphore procedure for reading an auto-stored message

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11.2 FullCAN interrupts

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The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a

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maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM

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is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to

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participate in the interrupt scheme. It is still possible to define more than 64 FullCAN

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objects. The only difference is, that the remaining FullCAN objects will not provide a

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FullCAN interrupt.

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The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)
FullCAN receive interrupts. As soon as a FullCAN message is received, the according
interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global
FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the
Vectored Interrupt Controller.

Application Software has to solve the following:

1. Index/Object number calculation based on the bit position in the FCANIC Interrupt
Register for more than one pending interrupt.
2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.

The software that covers the interrupt priority handling has to assign a receive interrupt
priority to every FullCAN object. If more than one interrupt is pending, then the software
has to decide, which received FullCAN object has to be served next.

To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so
that it is possible to enable or disable FullCAN interrupts for each object individually. The
new Message Lost flag (MsgLstx) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read by the
CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table
RAM.

11.2.1 FullCAN message interrupt enable bit

In Figure 21–78 8 FullCAN Identifiers with their Source CAN Channel are defined in the
FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used
to enable for each FullCAN message an Interrupt.

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Message Message

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disable bit disable bit

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3 2 1

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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

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Index 0, 1 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID FullCAN
Explicit
Index 2, 3 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Standard
Frame
Index 4, 5 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Format
Identifier
Index 6, 7 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Section

New: New:
FullCAN FullCAN
Message Message
Interrupt Interrupt
enable bit enable bit

Fig 78. FullCAN section example of the ID look-up table

11.2.2 Message lost bit and CAN channel number

Figure 21–79 is the detailed layout structure of one FullCAN message stored in the
FullCAN message object section of the Look-up Table.

New: New:
FullCAN CAN
Message Source
lost bit Channel

APB 31 24 23 16 15 10 9 8 7 0

Base +

R S S
F T
E E un- ID.2 ID.1
Msg_ObjAddr + 0 unused M M unused RX DLC SCC ............................
R used 8 8
F 1 0

Msg_ObjAddr + 4 RX Data 4 RX Data 3 RX Data 2 RX Data 1

Msg_ObjAddr + 8 RX Data 8 RX Data 7 RX Data 6 RX Data 5

Fig 79. FullCAN message object layout

The new message lost bit (MsgLst) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read. For
more information the CAN Source Channel (SCC) of the received FullCAN message is
added to Message Object.

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11.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)

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The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN

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message and if the interrupt of the according FullCAN Object is enabled (enable bit

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FCANIntxEn) is set).

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During the last write access from the data storage of a FullCAN message object the

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interrupt pending bit of a FullCAN object (IntPndx) gets asserted.

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11.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)
Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of
a message object are cleared by Software (ARM CPU).

11.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.

During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.

11.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to
0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.

During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.

11.3 Set and clear mechanism of the FullCAN interrupt

Special precaution is needed for the built-in set and clear mechanism of the FullCAN
Interrupts. The following text illustrates how the already existing Semaphore Bits (see
Section 21–11.1 “FullCAN message layout” for more details) and how the new introduced
features (IntPndx, MsgLstx) will behave.

11.3.1 Scenario 1: Normal case, no message lost

Figure 21–80 below shows a typical “normal” scenario in which an accepted FullCAN
message is stored in the FullCAN Message Object Section. After storage the message is
read out by Software (ARM CPU).

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semaphore
01 11 00

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bits

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IntPndx

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Write write write write read clear read read read

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look-up

A
ID, SEM D1 D2 SEM SEM SEM D1 D2 SEM
table
access

MsgLostx

message ARM
handler processor
access access

Fig 80. Normal case, no messages lost

11.3.2 Scenario 2: Message lost

In this scenario a first FullCAN Message is stored and read out by Software (1st Object
write and read). In a second course a second message is stored (2nd Object write) but not
read out before a third message gets stored (3rd Object write). Since the FullCAN Interrupt
of that Object (IntPndx) is already asserted, the Message Lost Signal gets asserted.

semaphore 01 11 00 01 11 11
bits

IntPndx

look-up write write write

table write write write read clear read read read ID, write write write write write write
ID, ID,
D1 D2 SEM SEM SEM D1 D2 SEM SEM D1 D2 SEM D1 D2 SEM
access SEM SEM

1st Object 2nd Object 3rd Object

write write write
1st Object
read

MsgLostx

message ARM
handler processor
access access

Fig 81. Message lost

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11.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits

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This scenario is a special case in which the lost message is indicated by the existing

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semaphore bits. The scenario is entered, if during a Software read of a message object

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another new message gets stored by the message handler. In this case, the FullCAN

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Interrupt bit gets set for a second time with the 2nd Object write.

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semaphore 01 11 00 01 11 00
bits

IntPndx

look-up write write

write write write read clear read read read clear read read read
table ID, ID, write write write
D1 D2 SEM SEM SEM D1 D2 SEM SEM D1 D2 SEM
access SEM SEM D1 D2 SEM

1st Object 2nd Object

write write
2nd Object
1st Object read
read
Interrupt Service
Routine

MsgLostx

message ARM
handler processor
access access

Fig 82. Message gets overwritten

11.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and
Message Lost
This scenario is a sub-case to Scenario 3 in which the lost message is indicated by the
existing semaphore bits and by Message Lost.

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semaphore 01 11 00 01 11 00

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bits

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IntPndx

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write write
write write write read clear write write write read read read clear read read read

A
look-up ID, ID,
table D1 D2 SEM SEM SEM D1 D2 SEM D1 D2 SEM SEM D1 D2 SEM
SEM SEM
access 1st Object 2nd Object
write write
1st Object read 2nd Object
read
Interrupt Service
Routine

MsgLostx

message ARM
handler processor
access access

Fig 83. Message overwritten indicated by semaphore bits and message lost

11.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost

This scenario is a sub-case to Scenario 3 in which the lost message is indicated by
Message Lost.

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semaphore 01 11 01 11 00 01 11

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bits

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IntPndx

look-up write write write

write write write read write write write clear read read read write write write
table ID, ID, ID,
D1 D2 SEM SEM D1 D2 SEM SEM D1 D2 SEM D1 D2 SEM
access SEM SEM SEM

1st Object 2nd Object 3rd Object

write write write
1st Object
read
Interrupt Service
Routine

MsgLostx

message ARM
handler processor
access access

Fig 84. Message overwritten indicated by message lost

11.3.6 Scenario 4: Clearing Message Lost bit

This scenario is a special case in which the lost message bit of an object gets set during
an overwrite of a none read message object (2nd Object write). The subsequent read out
of that object by Software (1st Object read) clears the pending Interrupt. The 3rd Object
write clears the Message Lost bit. Every “write ID, SEM” clears Message Lost bit if no
pending Interrupt of that object is set.

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01 11 01 11 00 11

A
semaphore

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bits

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IntPndx

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write write write
look-up write write write write write write read clear read read read write write write
ID, ID, ID,
D1 D2 SEM D1 D2 SEM SEM SEM D1 D2 SEM D1 D2 SEM
table SEM SEM SEM
access
1st Object 2nd Object 3rd Object
write write write
1st Object
read

MsgLostx

message ARM
handler processor
access access

Fig 85. Clearing message lost

12. CAN configuration example 1

Table 21–300 shows which sections and types of CAN identifiers are used and activated.
The ID look-up table configuration of this example is shown in Figure 21–86.

Table 300. Used ID look-up table sections of example 1

ID look-up table section Usage
FullCAN Not Activated
Explicit standard frame-format Activated
Group of standard frame-format Activated
Explicit extended frame-format Activated
Group of extended frame-format Activated

12.1 Explicit standard-frame format identifier section (11-bit CAN ID)

The start address of the explicit standard frame-format section is defined in the CASFESA
register with a value of 00h. The end of this section is defined in the CASFGSA register.

In the explicit standard frame-format section of the ID look-up table, two CAN identifiers
with their source CAN channels (SCCs) share one 32-bit word. Unused or disabled CAN
identifiers can be marked by setting the message-disable bit.

To provide memory space for eight explicit standard frame-format identifiers, the
CASFGSA register value is set to 10h. The identifier with Index 7 of this section is not
used and is therefore disabled.

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12.2 Group of standard frame-format identifier section (11-bit CAN ID)

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The start address of the group of the standard frame-format section is defined in the

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D

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CASFGSA register with a value of 10h. The end of this section is defined in the CAEFESA

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register.

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In the group of standard frame-format sections, two CAN Identifiers with the same SCC

FT
share one 32-bit word and represent a range of CAN Identifiers to be accepted. Bits 31

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R
A
down to 16 represent the lower boundary and bits 15 down to 0 represent the upper
boundary of the range of CAN Identifiers. All identifiers within this range (including the
boundary identifiers) are accepted. A whole group can be disabled and not used by the
acceptance filter by setting the message-disable bit in the upper and lower boundary
identifiers.

To provide memory space for four Groups of standard frame-format identifiers the
CAEFESA register value is set to 20h. The identifier group with Index 9 of this section is
not used and is therefore disabled.

12.3 Explicit standard frame-format identifier section (29-bit CAN ID)

The start address of the explicit extended frame-format section is defined in the
CAEFESA register with a value of 20h. The end of this section is defined in the CAEFGSA
register.

In the explicit extended frame-format section, only one CAN Identifier with its SCC is
programmed per address line.

To provide memory space for four explicit extended frame-format identifiers the
CAEFGSA register value is set to 30h.

12.4 Group of extended frame-format identifier section (29-bit CAN ID)

The start address of the extended frame-format group is defined by the CAEFGSA
register with a value of 30h. The end of this section is defined by the end-of-table address
register CAEOTA.

In the extended frame-format section group boundaries are programmed with a pair of
address lines. The first is the lower boundary, the second the upper boundary.

To provide memory space for two groups of extended frame-format Identifiers the
CAEOTA register value is set to 40h.

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Message Message

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disable bit disable bit

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Index

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CASFESA MSB LSB MSB LSB

A
SCC 0 ID28 0 ID18 SCC 0 ID28 1 ID18

FT
= 00h Explicit

D
MSB LSB MSB LSB
Standard SCC 2 SCC 3

R
0 ID28 ID18 0 ID28 ID18

A
Frame
MSB LSB MSB LSB
...Format SCC 0 ID28 4 ID18 SCC 0 ID28 5 ID18
Identifier MSB
MSB LSB LSB
Section SCC 0 ID28 6 ID18 SCC 1 ID28 Disabled, 7 ID18

CASFGSA MSB LSB MSB LSB

= 10h SCC 0 ID28 8 ID18 SCC 0 ID28 8 ID18 Group 8
Group of
MSB LSB MSB LSB Disabled
Standard SCC 1 ID28 Disabled, 9 ID18 SCC 1 ID28 Disabled, 9 ID18
Group 9
Frame
MSB LSB MSB LSB
...Format SCC 1 ID28 10 ID18 SCC 1 ID28 10 ID18 Group 10
Identifier MSB MSB LSB
LSB
Section SCC 0 ID28 11 ID18 SCC 0 ID28 11 ID18 Group 11
CAEFESA MSB LSB
SCC ID28 12 ID0
= 20h Explicit MSB LSB
Extended SCC ID28 13 ID0

Frame MSB LSB

Format SCC ID28 14 ID0

Identifier MSB LSB

Section SCC ID28 15 ID0

CAEFGSA MSB LSB

= 30h SCC ID28 16 ID0
Group of MSB LSB Group 16
Extended SCC ID28 16 ID0
Frame
MSB LSB
Format SCC ID28 17 ID0
Identifier MSB LSB
Group 17
Section SCC ID28 17 ID0

CAEOTA
= 40h

Fig 86. ID-look-up table, configuration example 1

13. CAN configuration example 2

Table 21–301 shows which sections and types of CAN identifiers are used and activated.
The ID look-up table configuration of this example is shown in Figure 21–87.

This example uses a typical configuration in which FullCAN as well as explicit standard
frame-format messages are defined. As described in Section 21–8.10, acceptance
filtering takes place in a certain order. With the FullCAN section enabled, the identifier-
screening process of the acceptance filter always starts in the FullCAN section before
continuing with the rest of the enabled sections.

Table 301. Used ID look-up table sections of example 2

ID-look-up table section Usage
FullCAN Activated and enabled
Explicit standard frame format Activated

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Chapter 21: LPC29xx CAN 0/1

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Table 301. Used ID look-up table sections of example 2

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ID-look-up table section Usage

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13.1 FullCAN explicit standard frame-format section (11-bit CAN ID)

A
The start address of the FullCAN explicit standard frame-format section is automatically
set to 00h. The end of this section is defined in the CASFESA register.

In the FullCAN ID section, only FullCAN object identifiers are stored for acceptance
filtering. In this section two CAN Identifiers with their SCCs share one 32-bit word. Unused
or disabled CAN Identifiers can be marked by setting the message-disable bit. The
FullCAN object data for each defined identifier can be found in the FullCAN message
object section. In the event of an identifier match during the acceptance filter process, the
received FullCAN message-object data is moved from the receive buffer of the
appropriate CAN controller into the FullCAN message-object section.

To provide memory space for eight FullCAN explicit standard frame-format identifiers the
CASFESA register value is set to 10h. Identifier index 1 of this section is not used and is
therefore disabled.

13.2 Explicit standard frame-format section (11-bit CAN ID)

The start address of the explicit standard frame-format section is defined in the CASFESA
register with a value of 10h. The end of this section is defined in the end-of-table address
register CAEOTA.

In the explicit standard frame-format section of the ID look-up table, two CAN Identifiers
with their SCCs share one 32-bit word. Unused or disabled CAN Identifiers can be marked
by setting the message-disable bit.

To provide memory space for eight explicit standard frame-format identifiers the EOTA
register value is set to 20h.

13.3 FullCAN message-object data section

The start address of the FullCAN message-object data section is defined in the EOTA
register. The number of enabled FullCAN identifiers is limited to the available memory
space in the data section.

Each defined FullCAN message needs three address lines in the data section for the
message data.

The FullCAN message-object section is organized so that each index number in the
FullCAN identifier section corresponds to a message-object number in the
message-object section.

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