I HAVEN Siticon | -SSREE Vist technoiores. Maven Silicon is « VLSI Trauning company that Wore i2¢e2 Sliow th cls wainag company in Indi that offers Syst Verlog bed nda eat ea offers wide range of comorate and profesiona mining oe of taining 250: cngowesre Yoo" ~ AD strinning process txtsolones ve growin design sizes ad increasing negation of IP Aemely complex and citcal par of any co ing and semiconductor industries. He bat worked as a Verification Consultant sphics. During this tenure, he worked rery closely with various ASIC and FPGA wel forthe successful:ape-outs ofmultimillin gate designs. Sure Synopsys Cadence and Mentor Gra r L eee ) SS ) sow more about our CEO, please vist NTtB://wwwlinkedin.com/in/sivape | FIVE REASONS TO MUSE “a ON MAVEN SILICON INCLUDES, | (SS rem Vertog band Advanced Vriteaion ss Sicon asthe ting at ees engineers 00 the mvanced ASIC ‘Denon teboleioges and Sem\erog. ta atdiien "yee els \eSineloge we abe iapat e Rat VIS thlogie Ne de et Dalen Mobolobgy, Vetop ASIC & FPGAS defen tsa, ereeg! Rizal 3 Peatas. | 2. Course Delivered by Indostry Experts ‘Sticatiot technologies only expeieaced VLSIengineers can deliverit-At Maven Silecoa, idasty expens share thir experience and guide yeu on how to eahance Snegpsisvistiodene ees Rim Sin, cep cinedcgerr sho wk nh op scaeencer Bis Siva Secor taper team be mp enehese Peete rrpeeittrenen se Catalase ene eS l ED cos ct ae VEStaN a compet of stron! VLSI dein nd ‘ ager Placement Assistance OSTEO, Sivaamaris be Foun eo CEO ofa VLSI design services compary 6: Accic Desga Technologies Werner the top performers of Maven Sifecn Se Ses ecrpery tot oie tem great opporuuitics to work on complex ve Fic proece nttlisty tot ney portage Te now te soo ar sreees Company, less vst vac cme rides great opportinitcs to eigners to work on verifiction platfone like SIND Ad Alors the advased ASIC verification techaologics and Stops | EDA Partner - Mentor Graphics SD soos nae Cece trp tomato. innovate i «ducts and soutons help ener tengo daign challenges a esas ty daunting workdofDovdansenipgeoge "SPS, please visit www nerd" som wrwmoven-silicon.com | more about Mentor ~ a) ~ oe a -Gr KIREE FL - Digital Electronics er www.maven-silicon.comPe ieiie le citar ee wu memaversiticon.com con Confidential \ All the presentations, books, documents {hard copies and | soft copies] and projects that you are using and developing | as part of the training course are the proprietary work of Maven Silicon and is fully protected under copyright and | trade secret laws. You may not view, use, disclose, copy, or | distribute the materials or any information except pursuant to a valid written license from Maven Silicon fa EE Eee eee eoARAVER, Signals ee * Signals are the variation in physical parameters, like temperature variation, Speech, videos, light intensity variation. + Any signal need to be processed . E.g., storing, transmitting or receiving the signal - Example : Microphone (Speech signal need to be amplified and given out to the speaker) * Electrical signals are the variation of electrical components IKE Voltage (VY) and current (I) with respect to time (t). a FPAVER: Analog Vs a perotee (wots) “Tame Ge matencends) sercturse (ovo) “Tere (ie itgecencs)MAVEN Advantages of Digital circuits eo Reproducibility of results ( ageing of components) Ease of design (2 iogic states: 0, 1) : Flexibility Programmability (HDLs) * Speed Economy Steadily advancing technologies (nm design) Digital signals can be copied, transmitted and processed without error (less pronounced effect of noise) * Small size and low power consumption + Less affected by noise . . . . . Disadvantages of Digital circuits In real life A. digital signal takes time to change from one value to another,atid “assumes intermediate values during transition. Steady values are slightly inaccurate. Voltages within certain ranges are guaranteed o be interpreted as certain permitted values Needs converters to communicate with real world Single bit error may corrupt an entire data therefore more expensive and less precisionMean) Number Systems — = + Binary The binary system is said to be of base, or radix, 2 because have only vo possible values: 0 and I. Decima\ The as ecimat base, or radix, 10 sce Me al number system is.saidf0 be of base, or 78 + Octal The octal number system is « j . © vase-8 system that has eight digits: 0, 1,2,3,4,5,6.7. te —_- + Hexadecimal The hexadecimal (base-I6) number system, the just 10 digits are borrowed from the decimal system. The letters A, B, C, D, ©. and F are used for the digits 10, 11,12, 73,14, and 15, respectively. + sew .maven-sflicon.comAMER, ste {ead Number system conversions Any radix to Decimal number system Where p> No. of digits to the left of the radix point... | n> No. of digits to the right of the radix point. | > value of the number 1 > radix of the number system 9 wemmavenssilicon-com AAAY Any Radix Number System to Decimal Binary to Decimal Conversion Example: 10101, p> No. of digits to the left of the radix point. =5 n> No. of digits to the right of the radix point. = 0 d > value of the number. > radix of the number system = 2Example : Decimal to binary Conversion i a u ‘ YER Decimal to any radix number system $$ ue Successive multiplication of fractional decimal number by radix numberAMAVEN, Siero we Convert binary to decimal —W—$— (110111.1011), = (2) 19 Solution = + (ort), = 1@2)° + 1(2)* + O(2P + IEP + 1(2)' + 12) =55 * (1011), (0.5)+0+1(0.125)+ 1 (0.0625) 0.6875, * ANS : 55.6875 = sromresveersticoe toe RAVER, STLIe On| Binary to Octal and Hex Convert the following 1, (11011.011), = Solution : O11. 33), (group of 3s) 0001 (1B.6),¢ (group of 4s) 2. (476.543)5= (2), Solution : Convert each digit into 3 bit binary form (476.543)g= (100 111 110. 101 100 011), 3. (ADESAC),¢= (2); Solution : Convert each digit to 4 bit binary form + (ADE.54C)g= (1010 1101 1110 . 0101 0100 1100), : Sewm.auaven-silicon comAMA! AB, ate) Signed Magnitude Representation EE * MSB of a bit string is used as the sign bit a lower bits contain the sed a it e lowe ct ig ind the lower bit in th + Examples T= 15 ~ unsigned tumbel] signed number | Complement Number system ae * I'scomplement is achieved by complementing each bits. + 2's complement is achieved by adding | to 1's complement \W -2=1010 signed number system o% -2=1101 I's complement representation \' 4 -2=1110 2's complement representation sewwemavenssilicon.comCompl 0 +0 “i 271 0000 t001\ 42 3 0 0001.5 0010 1101 9010! 4 i100 0011 “| Tri 000 1110 4 bit numbers precmmmer: | Complement Number system _—____ n's complement is achieved by adding 1 to (n-1)' complement i + . 8's complement is achieved. by adding | to 7's complement. Similarly 16's complement is achieved by adding | to 15° complement. 471 bone Bat \ Ea: | dw n.mavensiticon.cam j——PRAYER: Subtraction using 8's complement SSE + G4)s- 27s = (Ms Solution : 8's complement of 27 is (77-27) +1 = 51 234 / 7 51 \ =105 af Discard Carty 1 the result is 05 AAV & si Subtraction using 16's complement ao * (AF 6 — (2016 = Chie Solution : 16's complement of 2C is (FF-2C) +1 = D4 ) . Ad 5 +D4 = 78 (J carry). snwn-maven-silicon.com 20Codes —<— ¢ Code is a symbolic representation of discrete information, which may be present in the form of numbers ,letters or physical quantities. ¢ Required to conveniently input data into digital systems and interpret results. Stereo & Types Of Codes Se + Weighted binary codes. + Non-weighted codes. + Error detecting codes. + Alphanumeric codes.Principles. weights indicated. The sum equivalent decimal digit, Weighted Binary Codes a * Weighted binary codes obey their * Each positions of a number represents a specific weight. * In a weighted binary code, the bits are multiplied by the of these weighted bits gives the f TH \v Ef 4 positional weighting Weighted Code cere epee eS Many weighted codes are possible Straight binary coding is a method of representing a decimal number by its binary equivalent. Weights must be chosen in a way that their sum is not greater than 15 and not less thers 9 One of the weights must be 1 or-1BCD Code | BCD is weighted code Binary coded decimal (bed) uses the binary number system to specify the decimal numbers 0 to 9. | i | i + Ithas four bits. + The weights are assigi digits ned according to the positions ocoupied by these Example =) a Bed code for the decimal huniber 874 Solution: (874) j4= (1000 0111 0100),ca i i | A u VW e ° i | Non - Weighted Codes . Non —weighted codes are not positional weighted, this means that each position withi inary i in a bi 7 uu inary number is not 4 Examples * Excess ~3 codes * Gray codes owcmavensiligon.com —— | | | | |Excess-3 Code a + I represents a decimal number, in binary form, as a number greater than 3. + It is obtained by adding 3 to a decimal number. Example [643],o into excess-3 code See Decimal number 6 4 3. Add 3toeachbit +3 +3 43 Excess-3 code ae 6 wewsmavenssilicon.com 2 Gray Codes The gray code belongs to a | numbers —Binaryeode Gray code class of codes called minimum | rere i | | change codes, in which only |? 9000 oe one bit in the code changes | 2 cages | oan when moving from one step to 3 ool ooo the next. i : 0100 i pat j ag 1 (6 101 : i me o110 i It is a non-weighted code. ar 7 an; 100 | ®: 1000 100 | oN x 9 1001 1101 \ Q \ s ‘0 1010 in P | 1011 m0 | Se RY . ‘o\ 2 1100 too | DS 13 1101 lon | . ed 100 oD aerator :Srereund Binary to Gray code Conversion ——$—— The first bit(MSB) of the gray code is the same as the first bit of the binary number ‘+ The second bit of the gray code equals the exclusive OR of the first and second bits of the binary number from MSB + The third gray code bit equals the exclusive-OR of the second and third bits of the binary number and so on. eee Example 1010 Convert [10110], to gray code.» y Ans: 11101 yo ae » STUIe ON! Conversion from Gray to Binary —_ ‘+ The first binary bit(MSB) is the same as that of the first gray code bit. * The second gray bit is XOR ed with the first binary, the third gray bit is XOR-ed with the second binary and so on, Example Convert the gray code 1 1.010 1 to binary form Ans : [100110}2 100110 wwwimaven-tilican.cont a0; 7 pipe ony Other Codes 1 | ————— EE Reflective Codes * A code is said to be reflective when the code for $ is the complement of the code for 0, 8 for 1, 7 for 2,6 for 3, and 5 for 4. 2421, 5211 and excess-3 codes [ reflective codes. | 8421 code not reflective code. Sequential Codes * A code is said to be a sequential when each succeeding code is one binary number greater than its preceding code. 8421 and excess-3 codes sequential codes 2421 and 5421 codes not sequential codes. sewmmavenssiliconcom 3 can VE i | wentimaven-silicon.cont 2Error Detecting Codes * During the process of binary data transmission, errors may | occur. : | ! | * In order to correct such errors, two types of codes, | { (1) error-detecting codes _ (2) error-correcting codes nds Error Detecting * Odd parity code: | Total number of Is in the code group must be an odd(including parity bit). + Even parity code: | Total number of Is in the code group(including parity bit)must be an even. ewamacentiticon.com i | | | | |= ty Other Codes ———— + Hamming code + Alphanumeric codes + ASCII code * EBCDIC code * Hollerith code tow w 0 AICO NJAMAVER, Logic Circuits a Logic circuits perform operations on the digital signals and are usually implemented as electronic circuits were the signals values are restricted to few discrete values. * Binary logic circuits - 0 and 1 (2 values only) * Decimal logic circuits 0 t0 9 (10 values) Since each signal value is naturally represented by a “digit”, such logic circuits are referred to as “Digital circuits”. In contrast, there exist analog circuits where the signals may take on a continuous range of values between some minimum and maximum levels Example]: voltage range from Ov to Sv. wiywmavenssibeon.er-s = =~ Gates a—>o—-* A a— AtB A.B a B— - cee a— A+B — AB . B—_| Ao aA— A@B A@B B— B—_Truth Tables of all logic gates —$—$—$$—$— + The following Truth Table compares the logical functions of the 2-input logic gates. | of{e!ef{s1feof:sfeof4 | o{:1{/e°f+{fr+fefiafo | 7{efeiafafefafo | fa i 1 1 0 1 o o 1 | srernaveationcem vy ARAVER Active HIGH and Active LOW I/P Gates sewwamavensitconcom 0Boolean Algebra a a pce D- 00.2 (18) FWY KZ) AXA -D 19) XY) =X 103) (K+¥)-(X+¥) =X (ig K+ Y= 4X (I X+ (K+ 2)=KFVFZ (18) X-¥4X.Z=X. (92) (19) X#X.¥=X (T10)X .¥+X y=X (TI) X.Y+Y. ZX ZAK .V EZ | CTH) 4 YF +2). OC 2) EA) CCF) Sitdcow Boolean Theorem * DeMorgan's theorem Consensus theorem AB+A'C+BC = AB+A'CH(A+A)BC = ABtA'C+ABC+A'BC | wows ven-siliconcom 2dDual of a Boolean Function i + The dual of's Boolean function is obtained by INTERCHANGING OR & AND operations and REPLACING 1's by 0's and 0's by I's. y X+1=1 , By |xto=x 5 Duility. X+X=X X+X! s 5 5 wewsemavensilcon com 2 5 b 5 RAVER: 7 Dual of a Boolean Function 5 Example > X+X-Y=X > X-X+Y=X PATER, X+Y=X d , + The problem is in operator precedence. d * We used the identity X - X = X because of our convention that AND has precedence, » * So, the second line should have been written as X - (X + Y) = X to keep the original order.AMAVER, Complement of a Boolean Function ———EEEEEEE + The complement ofa function F, denoted by F’, is a function whose value is the opposite of “F”s value for every possible input combination We use DeMorgan's theorems to compute the complement of a function. Procedure 1. Parenthesize product terms. 2. Take the dual of the function. 3. Complement each literal meemavensilicon.com : 8i Logic Minimization oo - * A major step in digital design * This was critical in olden days Cost per logie gate Size of the product Power consumption Higher speeds wrorwumaven-ilicon.com ARAVER, Minimization using theorems RAVER, STUIeO NSKnowledge Check For the following circuit ,find the output and design a simpler circuit that has the same output ‘a ABeC ae WO new B- [>-F (ABC D.(AB+C)+D As | p47 ree use? AB | i { | | i Boolean Expressions \ + Sum-of-Products Boolean Expressions + Product-of-Sums Expressions + Expanded Forms of Boolean Expressions + Canonical Form of Boolean Expressions « SOP expression > wmtERM = POS expression T] MAXTERM TE FE PEO ie he nan am inMinimization Using Karnaugh Map + Developed by M. Karnaugh in 1953 + Widely used in computer based reduction of combinational expressions + Map displays the implicants (minterms) in the SOP K- Map EEE 4 Variable 2 Variable 3 Variable cp Map K- Map 10 A 0 ewe maven-silican.com 3Sree oN Plotting the Map AB cp aT Ti 10 00 0 S 1 Il 3 2 o1 : ° ‘ 5 1 6 u 1 1 1 33 15, a 10 o 0 1 q u 10 OeNsreree Reading the Map CD AB... ——<$ OL MW 10 AB + C’D'+B’D’K- Map ——_——_—____ ee. F=> m(0,1,4, 6, 7) BC 00 01 11 +10 A F=AB +A°B’ +B°C" F=AB +A°B’ +AC’ sovvumavenstcon.com 5s | K- Map F= 9) m(0,1,7,8,9,13,14,15) cD AB\ 00 01 11.10 F=B’C’+ ABC+BCD +ABD F=B’C’+ABC+BCD +AC’D swrw.maven-silicon.com 56K- Map —<—<— F= T1@,3.4,6,1 1,12) = ¥° m(0,2,5,7,8,9,10,13,1 4,15) cD cD 10 AB 00, 01 it Al 00,1} 0] 0 01} 0 11| 0 F=B'D’+BD +AC’D +ABC F=B’D’+BD + AB’C’+ ACD? sewsssma venssiican.com | K- Map doppia dal eee Sie acim (ADA BHC'4D’)(A+B'4D )‘MAVEN, SEOLC DE —_——— —_ EE + An input-output conditions that never occurs during, normal operation. * Mis indicated by 'X' in the truth table, * It can be cither 0 or 1, whichever produces simpler logic circuit i Don't-Care Conditions | ’ RAVER) Truth Table with Don't-Care K-Map preparation AB_00 01st 10 00) o 0 x of 0 0 ' : uy} 0 0 10} 0 x x Y=BC wivw.maven-silicon.com 60K- Map | ——_—_———_———— + F(A, B,C, D) = Emn(2, 3,4, 6, 11, 12) +d (10, 13, 14) cp | ABN, 0001 oo} 0 | 0 01 0 = y+ BC ula Ix F= BD'+ 10} 0} 0 swnnemavensiticon.comt Points to remember about Don't-Care * With given truth table, draw karnaugh map with Os, 1s and don't cares + Encircle the actual 1s in the largest groups-by treating don't, cares as 1s + Disregard the remaining don't cares by visualizing them as Os srmsmavensiliconcors @ARAVER, Minterm to Maxterm Conversion ee > Rewrite Minterm shorthand using Maxterm shorthand, Eg., (A,B,C) = ¥ m(3,4,5,6,7) Yim----— d= TMC -) > Replace minterm indices with the indices that are not in use. >3,4,5,6,7) = TIM (0,1,2) stuieen — EE > Rewrite Maxterm shorthand using Minterm shorthand. Eg. f(A, B,C) =TTM(1,3,5,7) I]™----- = Dim ) > Replace maxterm indices with the indices that are not in use. Maxterm to Minterm Conversio: T170,3,5,7) = m@,2,4,6) 1aven-silicon.com| EAAMER, Complement of an SOP expressio' —— — % The complement of a function expressed as a sum of minterms is constructed by selecting the minterms missing in the canonical SOP form Eg, f(A, B,C) =m (1, 3,5, 6) then, f' (A, B, C) = m(0, 2, 4, 7) & Alternatively, the complement of a function expressed by a Sum of Minterms form is simply the Product of Maxterms with the same indices. : SA, B.C) = TAT, 2, 5,6) i Complement of an POS cxpre hE EE » The complement of a function expressed as a product of maxterms is constructed by selecting the maxterms missing| in the canonical POS form. | Eg. f(A, B, C) =[ MU, 2, 5, 6) then , f' (A, B, C) = TI M(O, 3, 4, 7) ® Alternatively, the complement of a function expressed by al product of maxterms form is simply the sum of minterms with the same indices. S'(A, B,C) =¥ mA, 2, 5, 6) | |——_$_—_ CeSTUT CO Ne K - Map : Example OE Derive the circuit. 7 re oe yeK4 0 veousop—t LI l menimaven-siliconcom 67 FRAYERD Solution Inputs Outputs Time | ABC | f(4,B.C) | f(A.B.C) | 000 0 o a 001 1 r 2 010 1 0 6 oul 0 1 ‘ 4 100 0 0 15 101 0 1 | 6 110 1 1 j 7 Wl 1 0 » sew wuanaven-alilcon.com « > __ a$< ae BC AX _00_01 110 of 1 Fa=AB +BC’ +A’B’C Fb=A’C +B’C + ABC’ Ay 8. 8 5 7 Fa z c © vrecmaveneoncom —— 5 Variable K-Maps CDE 000 001 O11 O10 110 111 101 100 oo | 6 1 5 4 al ul id ual ast as] " 21 329} >a] 10) id ud aol asl ol od ail al AB Gray Code Style ee 705 Variable K Map: Example Design a circuit which has a S-bit binary input (A. B, C, D, E), with A being the MSB (Most Significant Bit). It must produce an output logic “High” or “value 1” for any prime number detected in the input data Solution: The set of numbers are (1,2,3,5,7.11,13,17,1923,29,31) isror line ——a a 111 101 100 AB \.000 001 011 010/110 11 1 00 Vofi fi 1 fi Plot I ineach 01 ~ 1 | 1 4 corresponding cell. _| n rf 10 Voit 1 Gray Code Style FRAVER) y= vel row. AMA t 5 Variable K Map : Example When using this ver other half of the map, mages in the Mirror line — CDE 109 AB \ 001 00 ol 1 10 ‘| Gray Code Style BICE +A'BE + A'CDE+ Vetch + BCD'E. +ACDE |= ARAVEN, Exercise —_—$—$—$ ae * Solve: We tea.boesd6)=2(103, 46,9, 1, 12,14 17.18, ‘ann 20,22, 25,27, 28,30) | Oo 001 O11 O10 110 111 101 100 AB a ey Ws | of ope hi i 1 ii fl i o pep ty i H | |—I : | mn i | |__|! ! | 10 a i ae | W=CE+ CE’ | 13 7 wnwmaveniliconcom + inl * Classification of Number Systems. + Representation of -ve numbers * Different Codes . Logical Operations and Logic Gates Boolean Algebraic Postulates + . Different forms of Boolean Expressions. | Dual and complement of a Boolean Expression | | i . Necessity of Minimization Minimization using Postulates, Minimization using K-Maps and don’t cares.Sreieon Combinational circuit = n inputs Combinational m outputs ~ * Circuit : Block Diagram of combinational circuit Circuits whose outputs depend only on the current inputs? wernimavenssiticon-com: i Combinational Circuits Sa =! + Adder, Subtractor + Code converters + Parity Checkers and Parity Generators * Multiplexer and De-multiplexer + Encoder and Decoder * Comparators * Multiplier, Divider & ALU . swvvveniaven-siicon.com Designing Combinational Circuits ES Problem description/specification Jnput/output of the circuit Define trath table Simplification for each output Draw the circuit ya eNeARAVER, SH UIE oN Example —————— «A switching circuit has twe control inputs (C1,C2),two data inpuls (X1.X2) and ore output (Z). The circuit performs one of the logic operations on the two data inputs, The function performed depends on the contro! inputs: C1 [C2 _| Function performed by circuit o fo oR ofa XOR r]o AND ofa EQU Design a circuit to realize Z using Kamaugh map. wrrmemavensiicon.com » _onvwamaven siticen.com soPossible groupings: Z= Cr'xr'X2 + Cixi X2" + CiC2X"X2 z= cr'xXi'k2 + cr'X1X2' + CrC2X1'X2 = CuXuX2 + CU NIK + CrC2X""X2 14 CrXIX2 * CV'Cr'K2 14 CrX1X2 + CV'CrX1 + CIX1K2 + C2XIX2 sewwimaven-silicon.comADDERS - Half Adder ——— 1. Specifications: Design Half Adder Adds 2 bits - A,B & produces Sum & Carry as Outputs A 2. Input/Output: Inputs - A,B B_ Outputs ~ Sum, Carry |. Sum HA |__. Carry Block Diagram A B Sum | Cary 0 0 0 0 < 3. Truth Table: 7 l ! 9 1 0 1 0 1 1 0 1 ADDERS - Half Adder EE 4. Simplification: fA uv Mi EF bh 5. Circuit Diagram: 84ADDERS - Full Adder |. Specifications: Design Full Adder 4 ‘Adds 3 bits - A,B & Cin, & gives Sum & Cout Outputs. Cin 2. Input/Output: Inputs ~ A, B, Cin / Outputs ~ Sum, Cout 3.Truth Table: [A] _B | Cin] Sum | Cout 0 0 0 0 oO 0 0 I I 0 otatolst o | 0 1 1 0 t < ifof oft] o 1 0 I 0 1 1 1 0 0 1 t 1 i 1 1 ‘werwmiavensilicon.comn pTeieon ARAVER, steiee ADDERS - Full Adder 4, Simplification: B’Cin’ B’Cin BCin BCin’ B’Cin’ B'Cin BCin BCin’ «fotze a [fo yo |it]jo a (ole ele ajo {{t Cout = AB + BC + AC Sum =A ® B@C Cout = ABABONA = ABACK ABC AB CH ABC) ™ AB (INC +C)4C (AB + AB’) = AB+C(A*B) wonemavenssilicon.com= 1) an ADDERS - Full Adder EE Sum =A @ BOC Cout = AB + C(A @ B) ’ 5. Cireuit Diagram PRAYER) 4 bit binary adder Ezz FA 3] raSubtractor em a] sp] ¢ [bit aoe im o | 0 o | 2 ; A Differen¢e [1 FS o |} 0 i , B |_. Borrow o |! | ° c oft 1 |o : - ; 4 of oft o_-| | 1 0 ! o u | 1 i 9 | 0 7 if ! ! ! | i __. sv = Trwimayensilicon.com Subtractor BC BC AN wo uw AN tt te elo (fo (EE ] | IE] [Tyo fo Jo |i jjo Dif =A® B@C Borrow =AB +AC+ BC Borrow = AB ARCA { = ABYAB DOHA BCHABCY A BC) 1 = AB(NEHQFC(ABTAB)” = AB+C(ASBy Borrow =A B +C(A@®B)so ar ANAVER| Subtractor es big =A@B@C Borrow mA B+ AC+ BC = AB+C(A@B) Pp Diff Borrow wonemavensilicon.con: 3 4 bit binary Adder-Subtractor 2AAV Stercond 4 bit binary Adder-Subtractor with overflow detector igs eauae wnvmionaven-silicon-£om 8 Working * The mode M controls the operation. When M=0 the circuit is an adder when M=1 the circuit is subtractor. It can be done by using exclusive- OR for each Bi and M. Note that 1 ® x= x' and 0 @ x=x + Note that in the previous slide if the numbers considered to besigned V detects overflow. V = 0 means no overflow and V = 1 means the resull is wrong because of overflow Overflow can happen when adding two numbers of the same sign (both negative or positive) and result can not be shown with the available bits. Itcan be detected by observing the carry into sign bit and carry out of sign bit position. If these two carries are not equal an overflow occurred. ‘That is why these two carries are applied to exclusive-OR gate to generate V. sevsoiaven-silicencom *—aaven] ARAVER, How do we extend this to larger adders? ——<—$< PE EE RE fF l Poe fF Sten Sus Soa Sy | | > Faster carry propagation 4 bits at a time mnvcmarensiliconcom 98 Carry Look Ahead Logic —$_$_—____smz. 1 Cary Generate G, , B, ; must generate carry when A = B Cary Propagate P= A, xor B, ; carry in will equal carry out here ‘Sum and Carry can be re expressed in terms of generate/propagate: $,=A;xor B; xor C; =P, xor C, | Cur = ABiC+ A,B,C h+A, BY C+ A,B, i =A,B,+C,(A;xorB) =G,+C,P; i If P,=A, or B;, then S;=A,xor B, xor C, CAB + AC* BC, =A,B,+C (A, orB) =G,+C,P, wywwumaven-ilicos.com 6a All Carries in Parallel Express the carry logic for each of the bits: c1=G0 + POCO | c2= G1 +PICI=GI +P1.G0+ PI POCO : 32.62 +P2C2=G2+P2GI + P2 PL GO+P2PI POCO | c4= G3 +P3C3 = G3 +P3G2+P3 p2 Gl +P3P2 P1 GO +P3P2P1PO Each of the carry equations can be implemented ina two-level logic network, Variables are the adder inputs and carry in to stage 0! CLA Adder Implementation ai ‘Adder with Propagate and — ‘ yy PGI gate delay Generate Outputs \ co \>- Si@2 gate delays Increasingly complex !ogi¢ | [ }——— se tase Nyt { } | i 4 bit CLA adder A B A B, AB ma) Ca cof etaccer | | 1 bit adder 1 bitadder Vitae 4 1 | 0+P3P2P1POcb s sz Sra eee ao Grr ee ah ee come co] i | Carry Look shead Logie i > a » { i = yn Cascaded Carry Lookahead atte we Baan Aue fa Da ome oe ft: . fff ff. cus[ 4 bitadder Abit adder Abitadder Abit adder f ! 4 : # oP cn Pca cr col (15:12) (11:8) (4) (3:0) °° Carry Look ahead Logie ERCODE CONVERTERS ——<—< 1. Specifications: Design Binary to Gray Code Converter (4 bit) Truth Table: 2. Input/Output: Inputs - BO,B1,B2,B3 Outputs — G0,G1,G2,63 Bo —| |__. Go Biraryto |. Gi BI Gray Code Be Convener G2 Bs o CODE CONVERTERS 4, Simplification: 5. Cireuit Diagram GO. (LSB) Gl a B3 G3 (MSB) Gl=B2@B1 G0 =B1® BO nvewimavenrsilicon.com 02fF uf \ ¥ £ b Exercise — EEE Design a circuit with minimum logic that receives a single digit, coded BCD (4 wires) and as an output gives yc multiplied by 5 ~ also BCD coded (8 wires). Solution ‘ou the result woewimaven-sitican.com 103 ENCODERS EEE An encoder is a device used to change a signal(such as a bitstream) or other codes into a binary code. The simplest encoder is a2" -to-n binary encoder One of 2"inputs = 1 > Output is an n-bit binary number = Binary — © inputs encoder |: outputs Lo rarer son1. Specifications: Design Take bits as inputs & 2, Input/Output: Inputs - D’ 3. Truth Table: 19,D1,D2,D3/ Outputs ~ ¥0.¥t ENCODERS Ds )D D, 1D A prionty | once it find Example Assign pr the outpat ae orlPRIORITY ENCODERS ee A priority encoder prioritizes more significant bits in the data stream, and once it finds a high signal will ignore all other bits Exainple: Single bit 8 to 3 priority encoder Assign priorities to the inputs When more than one input are asserted, the output generates the code of the input with the highest priority sinieon i Inputs Outputs Idle fie [is [x4 fs fro [nu [wo [v2 [vi yo o fo fo fo fo fo |[o {o [x [x [x fi o jo jo jo fo |o [o |i |o fo |o fo o fo jo jo jo jo |: |x fo jo [i fo o fo fo fo fo [1 |x |x [o |i [o fo o jo jo jo |i |x [x [x fo fi [i fo o jo fo |: [x [x [x [x [1 [o fo fo ojo ft {x [x fx fx [x |i fo fi fo of) [x fx [x [x fx [kx fi fifo fo 1 [x x [x [x [x [x |r fr fi fo Idle indicates that none of the inputs is high 108PRIORITY ENCODERS Ee Logie Equations Paenty Peony CS Binary encoder ar ® ht t 12 He a Bow Eye Ere ih He Me bts ‘ vt is He '6 7 a b ‘oe | 109 FRAY eR ENCODER Application $e Monitoring U! + Encoder identifies the request and encodes the value + Controller accepts digital inputs. ‘Alarm Controller” | ‘Seal Machine | Machine 2 Machine Action Controller} Machine a * Encoders are used for data compression com HoDECODERS binary code to other codes. eo A decoder is a device which does the reverse of an encoder, it changes @ ine Binary} | 6 steps . Decoder :| ¢ L no wouenaticonsom uw DECODERS 1. Specifications: Design 2:4 Decoder Take 2 Input code conven it to 4 output code 2.Inpu/Output: Inputs ~ $0, $1 / Outputs — ¥0,¥1,¥2,¥3, 3. Truth Table: 4. Circuit Diagram lope Ouipuse + s [so [ww lu pe py ¥ © fe o fe fe © ft fe [1 [fo fa r fe fe 7 Yo eeBCD-to- Seven Seam nt Decoder 1 Given the Block diagram of BC! the truth table, simplify every outpu DECODER App ication —_—_—_————— | D-to- Seven Segment Decoder, Draw | and draw the circuit di sewnmaven-siticon.com 7 Implementing Functions using Decodets a | ‘Any n-variable logic function can be implemented using a single n-to- er decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to the minterms of. th function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can implemented with an n-to-2* decoder with m OR gates. be Suitable when a circuit has many outputs, and each output function expressed with few minterms _owsumavensiticoncom aAMAVER: Implementing Functions using Decoders ee a full adder using a 3 to 8 decoder Sum=Em(1.2.4,7) and Carry = £m(3,5,6,7) « sic | ‘sum | Carry a op etst rte efape[ |e ePatsfels Tepes]. ofete ts swneumavenssilizon.com us EXERCISE ' Realize a full subtractor using a3 to 8 decoder with a) non inverting outputs ) b) inverting outputs . )» 2)n0n inverting outputs b) inverting outputs , y AD » B— 3wo8 pe c Bout b , sama ven-siliconcom 6MAGNITUDE COMPARATOR ee Design 1 bit magnitude comparator 1.Specification AMAVER Sturcony Compares | bit A & B to determine whether: A > B, orA= B, orA A>B,or > A=B, or PAB Inputs > First n-bit number A > Second n-bit number B Outputs 3 output signals (GT, EQ, LT), where:ARAVER, MAGNITUDE COMPARATOR OE 5. Cireuit Diagram 4, Simplification, 8 BB BB ete] «lote] ah afofi| Afi fo Alo lo 5 ; Hs D- >" COMPARATORS Equality Comparator ‘Truth Table a [® #0 * 0 0 1 EQ ° q 0 B t oe |e 1 1 i EQ = A@BSTC De! Universal logic elements « NAND « NOR + Multiplexer Universal logic elements, since they can be combined {o implement any kind of logic expression/gate wommavensiliconcom i StUqcor Design using only NOR Gate STEPS: 1. Apply De-morgan's theorem 2. Draw schematic 3. Replace OR with NOR ,AND with bubbled AND 4. Look for bubble incompatibilities and Replace bubbled AND with NORRAVER, stoean a Realize using only NOR Gate $s Example: Realize 'D + A'C +AB'C' using only NOR gates. aaa [STEP2. Schematic aa cs z rs ‘f >) —_ STEP3 D> - STEP4.a eau =D « 2 == a e=4 1S 5 = pe 7 ewmurenatiencem, a VIER, AMAVER| Yio n! : 7 shuieen Realize using only NOR Gate A aye Day A 1» éo 2 a > ¢ 5-1 x wewmaven-siliconcom na peCRAVER, Design using only NAND Gate — Steps : 1. Apply Demorgan's theorem 2. Draw schematic 3. Replace AND with NAND ,OR with bubbled OR. 4. Look for bubble incompatibilities and Replace bubbled OR with NAND seemrmaven-siticon.comn 1s Design using only NAND Gate ee Realize Z= ABC + AD +C'D' using only NAND gates. STEP.1.N/A STEP 2. Schematié™| > SS > wrenmavensiliconcom 126 go Om > o>mf WV € i 1 Design using only NAND Gate STEP 4. Findl Circuit — | Ft_>——_J x | sf > }— L/ | yo maven silicon.com: 17 Exercise al I] Realize Y= ABC'D + BD'C +AC'D' +B'CD [a] using only NOR gates. {b] using only NAND gates. [2] Realize ¥ = (A'+B+C'+D).(A+C'4D') (B4C+D) [a] using only NOR gates. [b] using only NAND gates. _wumamavenssiticon.com _ || MULTIPLEXERS a I switch «One directional digital «All the logic function can be implemented using @ multiplexer N variable logic function may be implemented using a 2%: muttiplerey 2:1 Multiplexer " Y =D,S'+D,S scusemavenctliconcom Peet e Re See cTAVER, MULTIPLEXERS $$ 1. Specifications: Design 2:1 MUX Choose from 2 Inputs - A.B using Select pin, then produces Input at output 2. InpuvOutput: Inputs - A, B, Sel Outputs ~ 3. TradCAAVER, MULTIPLEXERS 3. Thith Table: 4. Simplification ay ®[sa]y sa |v I or ofa 05 P, —D. MULTIPLEXERS 1 MU: 1. Specifications: Design Choose from 4 Inputs -using Select pin, thea produces Input at output Y 2. Inpu/Output: Inputs — D3, D2, D1, DO, $1, SO Output - Y Do o pt —_lo Y o 2 p2 ——l0 or D3 —_ju 7 T° pe 7 ap . FF siso o tt = S1' $0" DO + S1'SO D1 + $1 So" D2 + $1 $0 D3 “ =|RAVER, MULTIPLEXERS SE Specifications: Design 4:1 MUX USING 2:1 MUX |_—- vo yl ay o var st CRAVER, MULTIPLEXERS Specifications: | ‘wmwemaven-silicon.com neNOT Gate Using MUX Vee sf oO Gad | Y=a A é — Gate Implementation using 2:1 Mux 36 _..sty Function Implementation Using yj = Em(1,2.3,6,7,9,13,14) lmplement ¥ using 16: or Example 3: Y= F(A, Inputs © 7 7 Function Implementation Using MU Y= F(A.B,C.D) = Em{1,2,3,6,7,913.14) Implement using 8:1 Mux For each combination of A,B,C compare the dependence of output on D. Now, We will get the following teble: ByeLy > o a ° sl-lel-lel-le ° AMAYER se a ° ° ° ° r © © T @ € 7 te Ge we » weeweueve ©AAV: VER Function Implementation Using MUX Inputs or 1D) = Em{1,2,3,6,7,9,13,14) Implement using 4:1 Muy Now, For each combination of A,B. compare the dependence of output on Cand D For AD=09 Foran=o1 clo |v ec] y aio o|efe ofa fe 0 |'o fo tho fi] ryotr no eo voce yee de wumavensliconcom 9 Function Implementation Using MUX —— ao 10 forage . Thus, we will get the a] 1F oye Ty following circuit: epee ° |e fe ope ete Tete} wpe chef Thee ye Zo y=co@p wwnumaven-silicon.com M40FRAVER, Implementation Using MUX STU Shannon's Expansion Theorem * To break large functions * A Boolean Logic function F is expanded in terms of a Boolean variable X, Fe x.Px + xFx" where F is any function and Fx and Fx' are positive and negative Shannon cofactors of F, respectively. Example . F=(y.z) + (xyz) +4x'y'2) + To expand around the variable x, we simply don't have enough information in the first term to accomplish this task. + So, what do we do? wwimaven-silieon.com Mi An VER Function Implementation Using Shannon's Theorem Example F= (yz) + yz) + (yz) 1.Expand around the variable x But donit have enough information in the first term to accomplish this task. 2.AND the literal with ‘I or , in this case (x + x’) F= yz(x + x!) t xyz! +x'y¥z 3.Expand Fe xyz + x'y2 + xye + xyz sevyueaven-siconcom Weeae ARAVER: prea Ns Function Implementation Using Shannon's Theorem 4.Use Shannon's Expansion theorem d get Fx=yetye'= Substitute x=1 in Substitute x=0 in F and get Fe x Px + xPx : > r F= x! (2) + x(y) y , 1 x We can coniinue to expand a function 2s many times as it has variables until Feayrtyz = we reach the canonical form. 16 Function Implementation Using me f Shannon's Theorem (1) —“ —— Same question, but expanding around variable y. | Here all the terms are having the varible *y’ to accomplish this 6 task. 5 2.Use Shannon's Expansion theorem Substitute y=] in F and get Fy =z+xz' Fy =x'z Substitute y=0 in F and get 3.For, Fy’ again use Shannon's Expansion theorem in F and get Fz in F and get Substitute z= Substitute z= 144 sevuumaven-silieon-€omtid Function Implementation Using ‘sg Theorem (2) Shannon 4, For Fy again use Shannon's Expansion theorem Substitute z=! in F and get Substitute 2=0 in F and get Function Implementation Using Shannon's Theorem (3) Example 2: | F= (A.B) + (B.C) +D | First we expand F wrt B: F= B(A+D) +B’ (C+D) a | Describes 2 2:1 MUX behavior Now split Fl and F2, expand FI= Fb wrt A, and F2= Fb! wrt C: ii) | (iv) FI=A+D=(A1)+ (A.D) F2=C+D=(C.1) + (C.D)FRAVER Function Implementation Using eiecon Shannon's Theorem (4) Now, we may implement F by arranging for A, B,C to appear on select lines and ‘I’ and D to be the data inputs of the Mux. D [e Now, we know how to implement Boolean functions using Mux www.maven-silicon.com 1 ff uf . ¥ & i hb Function Implementation Using , Shannon's Theorem ————— * Implement ) FW). WosW3,Wgs Ws) = Wy'Wy'W Ws! + WW, + WLW + We + WyWAW sy using a 4:1 mux and as few other gates as possible. Assume that only uncomplemented form of the inputs are available.+ wyl.ws! = (w,#ws)! using NOR gate resco wl Function Implementation Using Shannon's Theorem ~ =D Ys 41 ; |) = “a MUX wy 1—4 ws OM nve.maren-silicon.com 9 FAAMERD DEMULTIPLEXERS Ne EE EINecssocaeall The demultiplexer is the inverse of the multiplexer, in that it takes 2 single data input and n address inputs. It has 2n outputs. ‘The address input determine which data output is going to have the same value as the data input. The other data outputs will have the value O. 80 SI Se wosemarensilicon.com 1501:2 DEMULTIPLEXER 4 ~L=Te | Yo ote |9 a op. e L Y ‘feo ) ae Sel or Sa] vo] vi o[ ale thela SICICON| i ein 1. Specifications: Dep ER 1:4 DEMUX USING i. NOT,AND & OR Gates ii, 1:2 DEMUX Ph w Truth Table ARAVER, Gi)= Applications of Mux & Demux “ee —_——_] * Multiplexer + Communication system + Telephone network ¢ Computér memory * Transmission from the computer system of a satellite + Demultiplexer + Demultiplexer is used to connect a single source to multiple destinations. * Communication systems = ALU (Arithmetic Logic Unit) = Serial to parallel converter - | TRI-STATE BUFFERS i + Three state gates exhibit three states instead of two states. The three states are: + high :1 + Low :0 + High impedance ea 4 oh o| In high impedance state the output is disconnected which is equal € °% circuit. In other words in that state, circuit has no logic sigmificant: | Input A. ——— Y_— Output Y=A if Sel =! Output Y = High-imped2n cc ise} Control input Sel mavea-siticon.comTRI-STATE BUFFERS 2:1 Mux using Tri state buffer 13s TP for Combinational Logic + Propagation delay (4a: The amount of time needed for a change in a logic input to result in a permanent change at an output. ¢ Contamination delay (t.¢): The amount of time needed for a change in a logic input to result in an_ initial change at an output. FRAMERS 136Example aT. AND gate Tpd = Sns — lp OR gate Tpd = 7ns -— Y ee What is the total delay at output? Sns + 7ns = 12ns srrsimavencitican.com 137 ao Using the following table of timing specifications for each component, what are the Tep and Tpp values for the circuit shown above? gate Top Teo 1 3ps_—15ps ND2 Sps30ps AN2 12ps__S0ps NR2 Sps 30ps OR2 _12ps__50ps Tpp = 110ps Top = 15 ps sovumavenailicon.com 138AV: prerean! Summary EE Combinational Logic Circuits — output depends on the combination of inputs. Eg: Adders, Subtractors, MUX, DEMUX, Encoder, Decoder, ete. MUX is an universal Logic Block. + Active HIGH output Decoder produces all the possible Minterms. Active LOW output Decoder produces all the possible Maxterms. Tristate Buffers produces a HIGH imy it is not enabled pedance state at the output if 139 RAVEN STUICON per =1 ial circuits Ws woswsmaven-sitican.comCombinat onal Logic circuits ed into circuits by usi the output = = Gates are combin gate as the input for another. = So, in these circuits combination of the inputs. AT the output depends only on the| ™ Output depends only on inputs. * Doesn't possess any memory elements. * There will be no feedback from the output to input. 2. ; easier to design & faster in operation. . Eg: MUX, DEMUX. ADDERS, ENCODERS & DECODERS Combinational Vs Sequential Breieow pt and Output depends on both in past state outputs. . Possess memory elements = Involves some kind of feedback: * Lots of complexity involves in BF design and slower in operation: ap: Flipftops, latches. eB counters etc. on.comARAVER, Logic circuits as memory elements Seem * Digital Circuits can also be as memory units. So, in these circuits the output depends on the past state of the inputs and outputs. These type of circuits are called as sequential circuits. srww.maven-siicon.com 16. Sequential Circuits ————— EE + Asynchronous Circuits. « Synchronous Circuits. * Input enable signals « Level sensitive + Edge sensitive + Two types: | | seve aaven silleon.com 164Latches —<————— R ° R-S Latch | . . ° wwmavensiliconcomt Behaviour of R-S LatchSen (RAVER: Bycic oN | f Truth table of R-S Latch RACE 68— RS Latch using NAND gates 2. -RESET No Chang| RX INVALIT So, it can be concluded that 2 2ate RACE | NAND latch can be considered 25 aw ACTIVE LOW latch j eresiican.com ___ _ | MAYER Truth table of Active low R-S Latch No Change° we$0. 1 1 nsmaven silicon.com APAVERS Truth table of gated RS latchCharacteristic equa ion of R: Qnt+1=S+ R’'Qn map Characteristic Equation 1B Overview —_——<—<——— SE Latch is a memory element which is capable of storing one bit (either 0 orl). + ALatch contains two output lines which are always complement to ach other. * AOR latch is an ACTIVE HIGH latch. + ANAND latch is an ACTIVE LOW latch. © Inorder to enable or disable any latch to accept the input data, control signal line can be used to convert latches into controlled latches. + Acontrolled NAND latch is active high latch. + Generally, invalid stale or RACE condition occurs in latches for certain pattern of inputs which are undesired and must be eliminated wmsimaventliconcom 6© To eliminate the invalid and race conditions (occurs when the inputs are either ‘00? and ‘11"), both the inputs must of RS latch must be compliment to each other. | os S =R’ =D sowsmaven-siticon.cont us oo ew Pala a Characteristic Equation Qnt1=S+R'Qr = Qn+l =D+DQn Qn+1=D smaven-ticon.com 17610 Necoae sagreange SEP ese 1 1 0 0 SET rode “oie / cocudieistitlgesd _—h i — ‘ Ena ese x 1 0 1x imine to 0 No Change. « Oem Th Te Pe ee thAven Characteristic equation of orate latch Se ESEESES o-oo O 1 Q 1 0 0 1 0 LK PK JK 1k 0 1 3 2 1 l 4 $ 7 3 l 1 Qn+}=JQn'+K°Qn RA Characteristic Equation | T latch | 2. | | | rs e icc IK 6 wteima ven-silicon.com 1507 ~ ABAYER, Behaviour of T latch SE 2272? Similar to behavior of controlled JK latch since... Characteristic Equation Qn+] =JQn*+K'Qn mp Qnt = TQn'+ TQn FRAY, £R Hazards with Latches a ¢ If the response time (time required for the output to respond for a corresponding change in input) of any latch is assumed be InS. 4 Then, it can be concluded that, for a T latch, the output toggles for 10 times if toggle state input (T=1) is in high state for 10nS. + ForRS latch, RACE condition occurs for 10 times if the corresponding inputs (R=S=1) are high for 10nS. + These rapid changes in the output are undesirable and must be avoided wormsmaven-silicon.com =;nme. Hazards with Latches i oe ea ee — 1008, 2008 Control ‘So, these hazards can be eliminated by enabling the latch only ance in @ complete exsle Steves wl Edge sensitivity ‘of Flipflops fs of os \ \ \ i] ' rf Control ttt 1 vLo \ \ a7 o> 2008 208 2008 ‘in a complete Cycle (which is spread over 2 period of 2088, The flip-flop respond only ence i e., only during the falling edge. This makes it possible to eliminate the race around condition in latches.Elimination of hazards hazards can be eliminated by enabling the latch te cycle. to make the memory elements edge sitive. ly once ina cycle. * So, these only once ina complet «+ So, it would be better sensitive instead of level sen: + Because, edges will occur on! mory elements are called flip-flops. + Bdge sensitive mel d flip-flops are edge sensitive. + Latches are level sensitive an + Latches will respond many no. of times in a single clk cycle. + But, flipflops will respond only once ina cycle erm maver-siticon.com Stere ow Gated latch Gated D Latch Given below is the timing diagram for a gated D-Latch Whenever G is enabled (ie 1) the input is passed to the output Whenever G is disabled the previous valu is latched ol aRAVER: Flip Flop Types SREF(Set Reset) DFE (Delay) __JK FF T FF (Toggle) | | | a T | | re po | | | se le |i [e | Te Je]| fF fe | |feje le | life fe 0 |e {a 7 fe fee ip 0 [i to mC 1 lo | [Ut 4 yt fe Lh | Te | | rh ted} JK FlipFlop T= tggk + AJ-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. «+ Feedback selectively enables one of the two seV/reset inputs so that they cannot both carry an active signal to the circuit, thus eliminating the Jid condition. wwwmavensilicon.com 18Positive Edge Triggered D FlipFlop ‘Master Latch Knowledge Check ——— positive level D latch and a + Complete the timing diagram for a gated positive edge triggered D Flip-Flop. D [ G/CL l | teh Quy p-Hop mie” QF mwumnavensilicon.com 10Knowledge Check i Complete the timing diagram for a falling edge trigger ed JK ff. a)Assume Q begins at 0 b)Assune Q begins at | Clock = Latch v/s Flipflop a Latch: * Level sensitive storage element. © Transfers data only during the active duration of pulse. They hold the last logic at the output during inactive period ‘They are used as temporary buffers. Constructed using transmission gates oe Flip Flop: + Edge sensitive storage eleraent. Transfers data only at the sampling instant andit cannot be changed until next sampling instant. They are used as registers + Consircied by cascading latches having opposite active gate pulse jevel 192ered Propagation delay for sequential circuit + Propagation Delay «+ C2Q: For an edge-triggerred flip-flop, the clock-to- Q time is the time it takes for the flipflop output to be ina stable state after 2 clock edge occurs. '$2Q, R2Q: I is the time taken by flipflop to come to SET or RESET state after the application of asynchronous inputs. Note - There is no propagation delay D2Q for DFF. D is synchronous input, no propagation delay value for synchronous inpus | Q i Q em I CLR CLR cLR | ; _ | AMESCharacteristics Equation —_—- EE RAVER, Device Characteristics Equation SR latch Q=S+RQ Gated SRlatch | Q*=SC+RQ+ CQ Gated Diatch | Q* =DC+CQ SR flip-flop Qr=S+RQ D flip-flop JK flip-flop T flip-flop 195 Choosing a Flip-Flop EE * R-S Clocked Latch : oF ¥ ‘ ¥ €F h used as storage element in narrow width clocked systems its use is not recommended! * however, fundamental building block of other flipflop types. * J-K Flip-flops: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement but has two inputs with increased wiring complexity edge-triggered varieties exist 196Choosing a Flip-Flop EE ‘+ D Flip-flops: «minimizes wires, much preferred in VLSI technologies = simplest design technique _ = best choice for storage registers + T Flip-flops: = don't really exist, constructed from J-K FFs = usually best choice for implementing counters 7 ==. were mavensilicon.com 7 Deriving JK FF Excitation table EE J K + From the truth table, for the Q 1 Q " o?foalotlo combinations of Q and Q* we see a : the combination for J and K is as 1 [4 shown below 0 1 | o]o | of} i1filjo Qiajs|xK c{ofofi o jojo 1 oti |i ofifitx] 1 1 fof. tfofx{i| La tf{iafo | wovemaven-iiconcon 1i : Excitation Table EE Qu Q 0 0 1 1 ono, Zw NS) 0 0 1 1 0 0 1 x | Design Procedure + Remember Excitation Table of FFs + Derive state synthesis table * Using K-map derive the design equations + Implement the circuit i Flip-Flop Conversions 2 StoveonConvert D FF into JK FF EE T State synthesis table ¢ K-map Use truth table of JK ff and Excitation Table of D JK J a Jk Jo [a |> AX 0001547 10 0 o jo j0 0 o fo fi fi ft oO 1 0 0 0 o fi fa fo fo 1 o jo t 1 1 0 1 1 1 1 1 o 1 1 r fr fr fo fo ensiticon.com JK FF from D FF + Circuit Diagram = ESExercise Convert JK Flip- Solution lo 203 Setup time and Hold time OE | + Synchronous inputs (e.g. D) have Setup, Hold time specification with | | respect to the CLOCK input. * Setup Time (Tsu) is the minimum time interval for which the input signal must be stable (unchanging) prior to the sampling event of the clock for the input signal to be recognized correctly. + Hold Time (Th) is the minimum time interval for which the input signal must be stable (unchanging) following the sampling event of the clock for the input signal to be recognized correctly.— AAA con Setup time and Hold time ———$—uee Setup / Hold time measured around active clock edge. tu , tha D changing D changing” — —__ - wnemaveresilican.com 205 | FRAMERD Setup or Hold time violation $$$ + A bold time violation, when a input signal change too quickly, after the clock’s active transition + A setup time violation, when a signal arrives too late, and misses the time when it should advance, + Ifthe setup or hold time parameters are violated, the output would be either logicO, logicl or metastable state. D | cu —1 Q amannmananal it 1,0 or metastable { wwvimnaven-silicon.cam 208EAMES Classification of Sequential circuits ——____—_ Circuits that includes flip flops are classified by the function they perform + Registers * Group of FFs Its basic function is to hold information within a digital system. * Used for serial addition, convolution encoders for error control coding, pseudo random binary sequence generstor. + Counters *A counter is usually coustructed from two or more flip-flops which change states in a prescribed sequence when input pulses are received nmumaver 28> secures 207 ARAVER, Register ee = * Several flip-flops may be grouped together with a common clock to form a register. + Consist of one or more FFs used to store and shift data * Two basic functions + Data storage + Binary Data shifting woe maren-silconcom 7 208Basic Register Func FF as a storage element tions _—__= issn is red i a a = 7] e D o Iv D oD } L ali \ ati—pe | femme | KLE Seale sere nt , ‘or remains 2 ‘orremains Oils i] 8 | | y = srernumavien sO RCO =F ou Q ; 8 7 pe CRAVER| ae é AVES] og ‘er Register | i Qo Qi Qz Q3 a \ Ta Tak Te Pe Ee Oh te ~ 0 , oeMAVEN, Basic Shift Register Functions —_ Basic data movement in shift register Serial In Serial Out (Right Shift ) Serial In Serial Out (LeftShitt ) ww emaven-licon.com 20 Basic Shift Register Functions EEE Basic data movement in shift register Right Rotate Rotate LeftClassifications ——_—< —_ ee + Serial in/ Serial out shift register (SISO) * Serial in/ Parallel out shift register (SIPO) Parallel in/ Serial out shifi register (PISO) Parallel in/ Parallel out shift register (PIPO) + Bi-directional Shift register ann nazensilicon.comoy SIPO shift registers EEE DQ DQ dD @ Pp aye * @ a @ @ LELA LPL LP LPL | | SIPO shift registers _—_—erSaaaa. z ; . 2% 2; 2 Oy 1 [——— | |Piso shift register mae) ‘ | PIPO shift register 005 | af oe o,—f? oa? | ty ay ip : | rH d al ad + | {— CRAVER: Bi-directional Shift register wow we 4-bit bi-directional shift register + Data can be shifted either left or right RIGHT “LEFT control line : gating logic wwvemavenssilicon.cont Bi-directional Shift register ——— EEE 4-bit bi-directional shift register + Data can be shifted either left or right + RIGHT /LEFT control line : gating logic tert / aout = 1 swnmavensiticon.com 20AMAVER, Shift Register Counter SS | A shift register with the serial output connected back (0 the serial input to produce special sequence ¢ Two of most common type of shift register counter | Johnson counter { Shift Counter / twisted ring counters] « Ring counter soe oe tee masenslcon.com zt Johnson Counter ————— ‘The neyative output of last FF connected back to the D input Fe C ]Qq} Q | QW | Qs ref Pe} be | be K 4 | . ofofololo Orato 1{1[o|[o|o GeO 241 {1} 0] 0 Ede fate def befe 3{1 [i filo (c (t (t rite . ear cI ox sjofifis onsen mee elololi|a i foto toh ‘No. of FFs 7 a wonsesmaven silicon.comJohnson Counter 8 states for 4-bit Johnson counter 10 states for S-bit Johnson counter Ring Counter SIUICo t ee The output of last FF connected back to the D input ‘10 bit Ring Coun _ nmwcatea silicon.comoli folololofofofololy 10-bit ring counter sequence tt tetetebetete Period = 10 i.e. 10 states 2/olo]1}e}o}o}olololo sfolelo{ifo]olo]o]ofo afofololeo{1i]o]olofofo sfofeolo]elo]i1fo]ofofo elo}lolo}ofofo]ilofofo 7lolole]}olofoljelrfofo alolofo]oljololofolifo efofofofofofofofofo|r werwmavenaiicon com a sieig Counters ]..— Why do we need counter? + Timing * Sequencing * Counting. Counters are classified into two categories: * Asynchronous Counters (Ripple counters) * Synchronous Counters =EE ‘There is a yreat variety of counters based on its construction. + Clock: Synchronous or Asynchronous + Clock Trigger: Positive edged or Negative edged + Counts: Binary, Decade + Count Direction: Up,Down, or Up/Down ~ ARAVERL Classification of counters ‘ I > > + Flip-flops: JK or Tor D > , ) y wosnmavenssiticoncom 27 sion % The output ofa +ve edge triggered T-flipflop will be toggled at every +ve edge in the clock signal. ‘And remaias-constant during the , period other than the instant of +ve edge of the clock: : v = 1/10NS | = 100MHz F-QO = 1/20NS = 5SOMHz @ io mie F-Qo = F-Cl/2 _ swysmaven silicon.com neronous down counter 3-bit asynchi ge triggered T-Flip Flop using +ve ed a F(Q2) = F(QI)/2 LPLEL bt FQ) = F@W/2 FQ) = FQN/? of we a = RAVER) 3-bit asynchronous up counter using -ve edge triggered T-Flip Flop FQ) = FQO/2 FQ) = FQNI2 RUD ies veyumaven-ilicon.com= A, 3-bit asynchronous up counter using +ve edge triggered T-Flip Flop F(Q®) = FCW/2 FQ) = FQO)/2 FQ) = FQ/2 a PUP ULL ew J TI J a i | i ¢ " : 7 on 0 ver | RAVER, 3-bit asynchronous down counter using -ve edge triggered T-Flip Flop FQ) = FCW/2 FQ) = FQO/2 FQ) = FEN/2 a LITSTLS1 PLP M7 ey LL Qi @ PEEEEtet tom fom fw [ont ee tw te tom 232Counters Summary of Asynchronous ~ VER $$$ | c itivity of | Edge Sensitivity of Clock Source Counting Sequence, Since, Q signal is feeding the Clock, DOWN counting will be doneSince, Q’ signal is feeding the Clock, UP counting will be done. wowwemaven-silicon.com 235, | RAVER, StLIC OW Synchronous Counters + Q gets toggled for every cycle. # When Qs is ‘0’, Q, will not get toggled. + And Q, will get toggled when Qy is ‘1’ + Q, gets toggled only if (Q; & Qo) are ‘1. ¢ Important Point : For the output of a T-flipflop to get toggled, The T- input must be supplied with logic “p> woimavenssiticoncom 6AMAVER, Synchronous Counters © Qogets toggled for every cycle. EG + So, Ty should be supplied with “1” # When Qo is 0°, Q, will not get toggled. + And Q, will get toggled when Quis ‘1 + Qpgets toggled only if (Q, & QGP * Te should be supplied with Q & Q, are ‘1? + T, should be supplied with Qy Clk Timing Diagram for 3 bit synchronous. up counter using +ve edge triggered TFF a wwvemavencalticon.comco o TLELF LIU LE LU Lt ghereo ws Timing Diagram for 3 bit synchronous up counter using tve edge triggered TFF fRAVER, 3-bit synchronous down counter using +ve edge triggered EE Flop—— Timing Diagram for 3 bit synchronous wih counter using +ve edge triggered TFF __ ~a a ae coer of LELF LE LA LE LE LPL 4 es TL 1% i v 1 Pa , Qi a b oe v \| 8 a iz “to i) mene > a 1 AO Al ‘ & ; , > et 4 0a Ko q i ’ eo ee : teour | % 81 Y6; He OH; 30; HH; 08; OF 18; HH) 00! OF; aaNAVEN, 4 Bit Synchronous Up Counter anne TQ Q Po TLE LAL... E: RAVER, Advantages of synchronous over asynchronous counter * All FF’s will change simultaneously. * Asynchronous counter can operate at much higher frequency, “but the circuitry are more complex than that of the asynchronous counter. maven-silicon.com 24MAVEN, STON pwwmavensillepmgon ARAVER, Steps for Counter design nw Step 1: Derive the State Transition Diagram Step 2: Draw State Transition Table Step 3: Choose flip-flop type for implementation Use Excitation Table to remap Next State Functions Step 4: Draw re-mapped K-Maps Step 5: Obtain minimized expressions Step 6: Implement Resulting Logic www. maven-silcon.com 26~MAVER| sree oN Counter Design ——— Example : Design a counter that goes through the states 0,2,3,5,6, Step 1: Derive the state transition diagram Count sequence: 000, 010, 011, 101, 110 Counter Design I Step 2: State Transition Table Present State Next State elo fe |e fen [oe o}ojfol|e of{ojfi{x o|1feolfo ro fa fi [os Pa | o |o |x 1fofi|s rf feo |e | 1 {1 [3 [xStep 3: Choose flip-flop type for implementation Use excitation table to remap next state functions ete lt 0 0 0 o{1 ft 1 0 I 1 i 0 0 ae Toggle Excitation Table 1 a 1 1 Counter Design 2S oc“&&s Step 4 : Draw remapped K Maps aie Ne Safa) of ol “Tolx] tat "pie fx 7 PM] 0 ee n 1 wi Step 5 : Obtain minimized Logic expressions T2= G2 QIQIA TH=QriQrsga —_ TH=QZAIQOFa! wowmavensiliconcom ———ARAVER| Counter Design ee Step 6: Implement Resulting Logic Q% Oy Oy 7 gates and 14 (input literals + Flipflop connections) wovw.taven-siicon.com 251 a ARAVER, Same design using JK FFDd, & Dy a a ay ae ak. La . La a 3 gates and § (input literals + Flipflop connections) 253 wvwimaversiliconcom Comparison —$—$ + TEEs well suited forstraightforward binary counters «But yielded worst gate and literal count for this example + JK FPs yielded lowest gate count = Tend to yield best choice for packaged logic where gate count is key * D FFs yieid simplest design procedure «Best literal count =D storage devices very much transistor efficient in VLSI + Best choice where area/literal count is the key “xywwimavensiticon.com 238Knowledge Check Design a 3-bit Gray Code Counter (using JK flip-flop) G2 GL Go 0 0 0 9 0 1 0 1 1 0 1 0 1 1 0 1 1 1 L 0 1 1 0 0 wvemavensilicon.com: 255 Knowledge Check ” Design a 3-bit Gray Code Counter.(using JK flip-flop) RAVER wee = Sar ee [Re 256Knowledge Check Design a 3-bit Gray Code Counter (using JIC flip-flop) QQ 0.0 Nan ob__tt ri fx |x Ay 01.0! Jo = 20) + G-2y' QQ or tt an OL x 3 bit Gray Code Counter ———$—$—<$<$___—_== Logic Diagram Jo =(Q: @ QN KK. 2a Je 0.08 20s, Ky Ky 20.0 D4 in CLKC AVER, counters. RA ¥ & b Frequency Division using Counters EE | + MOD number is equal to the number of states that the counter goes ) through before recycling. + ForNFF’, the number of states = 2 ex: N=4, then Mod=16 + By each FF the frequency is divided by 2 The output frequency of the last FF of any counter will be the clock frequency divided by the MOD of the counter. Example ; MOD-16 counter, last FF will have a freq =1/16 of the input clock, also called a divide by 16 counter. Modulo N counte! wonimavensilicon.com vide by N counter 260 Me pa es(RAN Coste Frequency Division using Counter: reach FF Counter waveforms showing frequency division Dy 2 fo 2 teal er CeAMAVER, ——$_—————_ ee * Systematic way of specifying any sequential logic * Ideally suited for complex sequential logic. Where FSM is needed To specify the sequential circuits which are = complex in their transition sequence and = depend on several control inputs 264 FSM Block DiagramAMAVE oreiege Moore machine © Output = £ (Present state) + Next state =f (Present state input) + Inputs don't directly affect the outputs + Output changes synchronously with the state transition and the clock leots ogi Iege tee SD) ywnsmavenssiticoncom 268 Mealy Machine SS 266 ee ea a eeMealy Machine ES + Output = f (Present state,input) + Next state = f (Present state input) + Inputs directly afffect the outputs + Outputs are asynchronous + Qutputs can change in response to any changes in the inputs, independent of clock. + Glitches can occur + Less no. of states required to implement when compared to Moore Machine. syonmemavensilican.com 267 CRAVE Generating Registered Outputs Companion = Pipetioes i _ FD foes) one = ows Pee vase ‘Outputs are synchronous seumsmavenssilicon.con 268