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 RTL Modeling with

SystemVerilog
for Simulation and Synthesis
using SystemVerilog for ASIC and FPGA design

6/15/17
 Other books authored or co-authored by Stuart Sutherland:

Verilog and SystemVerilog Gotchas: 101 Common Coding Error and How to Avoid
Them
Common coding mistakes and guidelines on how to write correct code. Co­
authored with Don Mills.
System Verilog For Design: A Guide to Using System Verilog fo r Hardware Design
and Modeling, Second Edition
Describes what SystemVerilog-2005 added to the Verilog-2001 language for RTL
modeling. Assumes the reader is familiar with Verilog-2001. Written by Stuart
Sutherland, with advice and contributions from Simon Davidmann and Peter
Flake. Includes an appendix with a detailed history of Hardware Description
Languages by Peter Flake.
Verilog-2001: A Guide to the New Features in the Verilog Hardware Description
Language
Describes what Verilog-2001 added to the original Verilog-1995 language.
Assumes the reader is familiar with Verilog-1995.
The Verilog PLI Handbook: A Tutorial and Reference Manual on the Verilog Pro­
gramming Language Interface, Second Edition
A comprehensive reference and tutorial on Verilog-2001 PLI and VPI program­
ming interfaces into Verilog simulation.
Verilog HDL Quick Reference Guide, based on the Verilog-2001 Standard
A concise reference on the syntax of the complete Verilog-2001 language.
Verilog PLI Quick Reference Guide, based on the Verilog-2001 Standard
A concise reference on the Verilog-2001 Programming Language Interface, with
complete object relationship diagrams.
 RTL Modeling with

SystemVerilog
for Simulation and Synthesis
using SystemVerilog for ASIC and FPGA design

Stuart Sutherland

published by:
Sutherland HDL, Inc.
Tualatin, Oregon, USA
sutherland-hdl.com
printed by:
CreateSpace, An Amazon.com Company
eStore: www. Create Space, com/7164313
ISBN-13: 978-1-5467-7634-5
ISBN-10: 1-5467-7634-6
Copyright © 2017, Sutherland HDL, Inc.
All rights reserved. This work may not be translated, copied, or reproduced in whole
or in part without the express written permission of the copyright owner, except for
brief excerpts in connection with reviews or scholarly analysis. Use in connection
with any form of information storage and retrieval, electronic adaptation, computer
software, or by similar or dissimilar methodology now known or hereafter developed
is forbidden.
The use in this work of trade names, trademarks, service marks, and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as
to whether or not they are subject to proprietary rights.

Sutherland HDL, Inc.

22805 SW 92nd Place
Tualatin, OR 97062-7225
E-mail: [email protected]
Phone: +1-503-692-0898
URL: sutherland-hdl.com
 V

Dedication

To my wonderful wife, LeeAnn, and my children, Ammon, Tamara, Hannah, Seth and
Samuel, and each o f their families — Families are forever!
Stuart Sutherland
Portland, Oregon, USA
 VII

About the Author

Stuart Sutherland provides expert instruction on using SystemVerilog and Ver-

ilog. He has been involved in defining the Verilog and SystemVerilog languages since
the beginning of IEEE standardization work in 1993, and is a member of the IEEE
SystemVerilog standards committee, where he has served as one of the technical edi­
tors for every version of the IEEE Verilog and SystemVerilog Language Reference
Manuals (LRMs). Stuart has more than 25 years of experience with Verilog and Sys­
temVerilog, and has authored and co-authored numerous papers on these languages
(available at www.sutherland-hdl.com). He has also authored “The Verilog PLIHand­
book”, “Verilog-2001: A Guide to the New Features o f the Verilog HDL, and “System­
Verilog fo r Design: A Guide to Using the SystemVerilog Enhancements to Verilog fo r
Hardware Design” (co-authored with Simon Davidmann and Peter Flake), and " Ver­
ilog and SystemVerilog Gotchas: 101 Common Coding Error and How to Avoid
Them" (co-authored with Don Mills) ”
Stuart is the founder of Sutherland HDL, Inc., which specializes in providing expert
SystemVerilog training and consulting services. He holds a Bachelor’s Degree in
Computer Science with an emphasis in Electronic Engineering Technology (Weber
State University (Ogden, Utah and Franklin Pierce College, Nashua, New Hampshire)
and a Master’s Degree in Education with an emphasis on eLearning course develop­
ment (Northcentral University, Prescott, Arizona).
 IX

Table of Contents

Table of Contents........................................................................................................... ix

List of Examples.......................................................................................................... xvii

List of Figures................................................................................................................xxi

Foreword....................................................................................................................... xxv

Preface......................................................................................................................... xxvii
Why this book........................................................................................................................xxvii
Intended audience for this book............................................................................................xxviii
Topics covered in this book..................................................................................................xxviii
Book examples........................................................................................................................ xxix
Obtaining copies of the examples............................................................................................ xxx
Simulators and synthesis compilers used in this book.............................................................xxx
Other sources of information.................................................................................................. xxxi
Acknowledgements................................................................................................................. xxxi

Chapter 1: SystemVerilog Simulation and Synthesis...............................................1

1.1 Verilog and SystemVerilog — a brief history.................................................................. 1
1.1.1 The Original Verilog............................................................................................ 2
1.1.2 Open Verilog and VHDL..................................................................................... 3
1.1.3 IEEE Verilog-95 and Verilog-2001..................................................................... 3
1.1.4 SystemVerilog extensions to Verilog — a separate standard..............................4
1.1.5 SystemVerilog replaces Verilog.......................................................................... 5
1.2 RTL and gate-level modeling........................................................................................... 6
1.2.1 Abstraction........................................................................................................... 6
1.2.2 Gate-level models................................................................................................. 7
1.2.3 RTL models........................................................................................................10
1.2.4 Behavioral and transaction-level models.............................................................11
1.3 Defining an RTL synthesis subset of SystemVerilog .................................................... 12
1.4 Modeling for ASICs and FPGAs.................................................................................... 12
1.4.1 Standard cell ASICs........................................................................................... 12
1.4.2 FPGAs.................................................................................................................15
1.4.3 RTL coding styles for ASICs and FPGAs...........................................................16
1.5 SystemVerilog simulation ...............................................................................................17
1.5.1 SystemVerilog simulators.................................................................................. 21
1.5.2 Compilation and elaboration............................................................................... 21
1.5.3 Simulation time and event scheduling................................................................ 23
X RTL Modeling with SystemVerilog for Simulation and Synthesis

1.6 Digital synthesis ............................................................................................................. 31

1.6.1 SystemVerilog synthesis compilers................................................................... 32
1.6.2 Synthesis Compilation....................................................................................... 33
1.6.3 Constraints......................................................................................................... 34
1.7 SystemVerilog lint checkers........................................................................................... 35
1.8 Logic Equivalence Checkers .......................................................................................... 36
1.9 Summary ........................................................................................................................ 37

Chapter 2: RTL Modeling Fundamentals................................................................39

2.1 Modules and procedural blocks.......................................................................................39
2.2 SystemVerilog language rules........................................................................................40
2.2.1 Comments.......................................................................................................... 40
2.2.2 White space........................................................................................................ 43
2.2.3 Reserved keywords............................................................................................ 44
2.2.4 Keyword backward compatibility — ‘begin_keywords....................................46
2.2.5 Identifiers (user-defined names)........................................................................ 49
2.2.6 Naming conventions and guidelines.................................................................. 50
2.2.7 System tasks and functions................................................................................ 51
2.2.8 Compiler directives............................................................................................ 52
2.3 M odules.......................................................................................................................... 52
2.4 Modules instances and hierarchy ................................................................................... 54
2.4.1 Port order connections....................................................................................... 55
2.4.2 Named port connections.................................................................................... 56
2.4.3 The dot-name inferred named port connection shortcut....................................57
2.4.4 The dot-star inferred named port connection shortcut.......................................58
2.5 Summary ........................................................................................................................ 59

Chapter 3: Net and Variable types........................................................................... 61

3.1 Four-state data values..................................................................................................... 61
3.2 Literal values (numbers)................................................................................................. 62
3.2.1 Literal integer values......................................................................................... 62
3.2.2 Vector fill literal values..................................................................................... 65
3.2.3 Floating-point literal values (real numbers)....................................................... 66
3.3 Types and data types ...................................................................................................... 66
3.3.1 Net types and variable types.............................................................................. 66
3.3.2 Two-state and four-state data types (bit and logic)............................................67
3.4 Variable types................................................................................................................. 67
3.4.1 Synthesizable variable data types.......................................................................67
3.4.2 Variable declaration rules.................................................................................. 70
3.4.3 Variable assignment rules.................................................................................. 74
3.4.4 Uninitialized variables....................................................................................... 74
3.4.5 In-line variable initialization.............................................................................. 75
3.5 Net types......................................................................................................................... 76
3.5.1 Synthesizable net types...................................................................................... 77
3.5.2 Net declaration rules.......................................................................................... 79
Table of Contents XI

3.5.3 Implicit net declarations..................................................................................... 80

3.5.4 Net assignment and connection rules................................................................. 83
3.6 Port declarations ............................................................................................................. 84
3.6.1 Synthesizable port declarations.......................................................................... 84
3.6.2 Non synthesizable port declarations.................................................................. 87
3.6.3 Module port declaration recommendations....................................................... 88
3.7 Unpacked arrays of nets and variables ........................................................................... 89
3.7.1 Accessing array elements................................................................................... 90
3.7.2 Copying arrays................................................................................................... 91
3.7.3 Array list assignments........................................................................................ 91
3.7.4 Bit-select and part-select of array elements.......................................................92
3.8 Parameter constants........................................................................................................ 93
3.8.1 Parameter dec larations....................................................................................... 94
3.8.2 Parameter overrides (parameter redefinition)....................................................97
3.9 Const variables ............................................................................................................... 99
3.10 Summary ........................................................................................................................ 99

Chapter 4: User-defined Types and Packages....................................................... 101

4.1 User-defined types......................................................................................................... 101
4.1.1 Naming conventions for user-defined types.................................................... 102
4.1.2 Local typedef definitions...................................................................................102
4.1.3 Shared typedef definitions............................................................................... 102
4.2 SystemVerilog packages ...............................................................................................102
4.2.1 Package declarations.........................................................................................103
4.2.2 Using package items.........................................................................................104
4.2.3 Importing from multiple packages................................................................... 108
4.2.4 Package chaining..............................................................................................109
4.2.5 Package compilation order............................................................................... 110
4.2.6 Synthesis considerations...................................................................................111
4.3 The $unit declaration space.......................................................................................... 112
4.4 Enumerated types ..........................................................................................................114
4.4.1 Enumerated type declaration syntax................................................................. 114
4.4.2 Importing enumerated types from packages.................................................... 117
4.4.3 Enumerated type assignment rules.................................................................. 118
4.4.4 Enumerated type methods................................................................................ 121
4.4.5 Traditional Verilog coding style without enumerated types............................ 124
4.5 Structures.......................................................................................................................124
4.5.1 Structure declarations...................................................................................... 124
4.5.2 Assigning to structure members...................................................................... 125
4.5.3 Assigning to entire structures...........................................................................125
4.5.4 Typed and anonymous structures.................................................................... 126
4.5.5 Copying structures............................................................................................127
4.5.6 Packed and unpacked structures...................................................................... 127
4.5.7 Passing structuresthrough ports and to tasks and functions............................. 129
4.5.8 Traditional Verilog versus structures............................................................... 130
 ■■
XII RTL Modeling with SystemVerilog for Simulation and Synthesis

4.5.9 Synthesis considerations..................................................................................130

4.6 Unions ...........................................................................................................................131
4.6.1 Typed and anonymous unions.........................................................................131
4.6.2 Assigning to, and reading from, union variables............................................. 132
4.6.3 Unpacked, packed and tagged unions.............................................................. 132
4.6.4 Passing unions through ports and to tasks and functions................................. 134
4.7 Using arrays with structures and unions........................................................................136
4.8 Summary .......................................................................................................................139

Chapter 5: RTL Expression Operators.................................................................141

5.1 Operator expression ru les..............................................................................................141
5.1.1 4-state and 2-state operations............................................................................142
5.1.2 X-optimism and X-pessimism........................................................................ 142
5.1.3 Expression vector sizes and automatic vector extension................................. 144
5.1.4 Signed and unsigned expressions.................................................................... 145
5.1.5 Integer (vector) and real (floating-point) expressions..................................... 145
5.2 Concatenate and replicate operators..............................................................................146
5.3 Conditional (ternary) operator.......................................................................................150
5.4 Bitwise operators...........................................................................................................153
5.5 Reduction operators.......................................................................................................158
5.6 Logical operators...........................................................................................................160
5.6.1 Difference between negate and invert operations............................................ 161
5.6.2 Short circuiting logical operations................................................................... 163
5.6.3 Non-synthesizable logical operators................................................................ 164
5.7 Comparison operators (equality and relational) ........................................................... 164
5.8 Case equality (identity) operators..................................................................................168
5.9 Set membership (inside) operator................................................................................ 171
5.10 Shift operators ...............................................................................................................173
5.10.1 Synthesizing shift operations............................................................................174
5.10.2 Synthesizing rotate operations........................................................................ 177
5.11 Streaming operators (pack and unpack) ........................................................................181
5.12 Arithmetic operators......................................................................................................184
5.12.1 Integer and floating-point arithmetic............................................................... 186
5.12.2 Unsigned and signed arithmetic might synthesize to the same gates.............. 188
5.13 Increment and decrement operators ..............................................................................189
5.13.1 Proper usage of increment and decrement operators....................................... 190
5.13.2 An example of correct usage of increment and decrement operators.............. 192
5.13.3 Compound operations with increment and decrement operators..................... 194
5.13.4 An anecdotal story on the increment and decrement operators...................... 195
5.14 Assignment operators ....................................................................................................196
5.15 Cast operators and type conversions ............................................................................198
5.15.1 Typecasting..................................................................................................... 200
5.15.2 Size casting...................................................................................................... 202
5.15.3 Signedness casting........................................................................................... 206
Table of Contents XIII

5.16 Operator precedence..................................................................................................... 209

5.17 Summary ...................................................................................................................... 210

Chapter 6: RTL Programming Statements...........................................................211

6.1 SystemVerilog procedural blocks.................................................................................. 211
6.1.1 Sensitivity lists................................................................................................. 212
6.1.2 Begin-end statement groups.............................................................................. 214
6.1.3 Using variables and nets in procedural blocks..................................................216
6.2 Decision statements...................................................................................................... 216
6.2.1 if-else statements.............................................................................................. 216
6.2.2 Case statements................................................................................................ 222
6.2.3 Unique and priority decision modifiers...........................................................227
6.3 Looping statements....................................................................................................... 228
6.3.1 For loops.......................................................................................................... 228
6.3.2 Repeat loops..................................................................................................... 233
6.3.3 While and do-while loops................................................................................ 235
6.3.4 Foreach loops and looping through arrays.......................................................236
6.4 Jump statements ........................................................................................................... 238
6.4.1 The continue and break jump statements.........................................................239
6.4.2 The disable jump statement............................................................................. 240
6.5 No-op statement ........................................................................................................... 241
6.6 Functions and tasks in RTL modeling.......................................................................... 243
6.6.1 Functions.......................................................................................................... 243
6.6.2 Tasks................................................................................................................ 248
6.7 Summary ...................................................................................................................... 249

Chapter 7: Modeling Combinational Logic...........................................................251

7.1 Continuous assignments (Boolean expressions) .......................................................... 252
7.1.1 Explicit and inferred continuous assignments.................................................254
7.1.2 Multiple continuous assignments...................................................................... 254
7.1.3 Using both continuous assignments and always procedures............................255
7.2 The always and always_comb procedures ................................................................... 256
7.2.1 Synthesizing combinational logic always procedures.....................................257
7.2.2 Modeling with the general purpose always procedure....................................257
7.2.3 Modeling with the RTL-specific always_comb procedure..............................260
7.2.4 Using blocking (combinational logic) assignments.........................................261
7.2.5 Avoiding unintentional latches in combinational logic procedures.................262
7.3 Using functions to represent combinational logic........................................................ 263
7.4 Combinational logic decision priority.......................................................................... 265
7.4.1 Removing unnecessary priority encoding from case decisions........................266
7.4.2 The unique and uniqueO decision modifiers....................................................266
7.4.3 The obsolete parallel_case synthesis pragma..................................................270
7.5 Summary ...................................................................................................................... 271
xiv RTL Modeling with SystemVerilog for Simulation and Synthesis

Chapter 8: Modeling Sequential Logic................................................................... 273

8.1 RTL models of flip-flops and registers ........................................................................ 274
8.1.1 Synthesis requirements for RTL sequential logic............................................274
8.1.2 Always procedures and always_ff procedures.................................................. 275
8.1.3 Sequential logic clock-to-Q propagation and setup/hold times........................276
8.1.4 Using nonblocking (sequential logic) assignments..........................................278
8.1.5 Synchronous and asynchronous resets............................................................. 286
8.1.6 Multiple clocks and clock domain crossing (CDC)..........................................295
8.1.7 Additional RTL sequential logic modeling considerations..............................297
8.2 Modeling Finite State Machines (FSMs) ..................................................................... 299
8.2.1 Mealy and Moore FSM architectures............................................................... 301
8.2.2 State encoding.................................................................................................. 302
8.2.3 One, two and three-procedure FSM coding styles........................................... 305
8.2.4 A complete FSM example............................................................................... 309
8.2.5 Reverse case statement one-hot decoder......................................................... 313
8.2.6 Avoiding latches in state machine decoders.................................................... 317
8.3 Modeling memory devices such as RAM s................................................................... 317
8.3.1 Modeling asynchronous and synchronous memory devices............................319
8.3.2 Loading memory models using Sreadmemb and Sreadmemh.........................320
8.4 Summary ...................................................................................................................... 322

Chapter 9: Modeling Latches and Avoiding Unintentional Latches.................323

9.1 Modeling Latches ......................................................................................................... 323
9.1.1 Modeling latches with the general purpose always procedure........................324
9.1.2 Modeling latches with the always_latch procedure.........................................325
9.2 Unintentional latch inference ....................................................................................... 327
9.3 Avoiding latches in intentionally incomplete decisions............................................... 329
9.3.1 Latch avoidance coding style trade-offs.......................................................... 330
9.3.2 A small example to illustrate avoiding unintentional latches..........................332
9.3.3 Latch avoidance style 1 — Default case item with known values..................335
9.3.4 Latch avoidance style 2—Pre-case assignment, known values.......................338
9.3.5 Latch avoidance style 3 — unique and priority decision modifiers................340
9.3.6 Latch avoidance style 4 — X assignments for unused decision values...........345
9.3.7 Latch avoidance style 5 — the full_case synthesis pragma.............................350
9.3.8 Additional notes about synthesis pragmas....................................................... 351
9.4 Summary ...................................................................................................................... 353

Chapter 10: Modeling Communication Buses — Interface Ports................... 355

10.1 Interface port concepts ................................................................................................. 356
10.1.1 Traditional Verilog bus connections................................................................ 357
10.1.2 SystemVerilog interface definitions................................................................ 361
10.1.3 Referencing signals within an interface........................................................... 365
10.1.4 Differences between modules and interfaces.................................................... 365
10.1.5 Source code declaration order.......................................................................... 366
10.2 Using interfaces as module ports.................................................................................. 366
Table of Contents xv

10.2.1 Generic interface ports..................................................................................... 366

10.2.2 Type-specific interface ports........................................................................... 367
10.3 Interface modports........................................................................................................ 367
10.3.1 Specifying which modport view to use........................................................... 368
10.3.2 Using modports to define different sets of connections..................................371
10.4 Interface methods (tasks and functions)....................................................................... 372
10.4.1 Calling methods defined in an interface.......................................................... 374
10.4.2 Synthesizing interface methods....................................................................... 375
10.4.3 Abstract, non-synthesizable interface methods............................................... 375
10.5 Interface procedural code ............................................................................................. 376
10.6 Parameterized interfaces............................................................................................... 378
10.7 Synthesizing interfaces................................................................................................. 379
10.8 Summary ...................................................................................................................... 382

List of Appendices...................................................................................................... 383

Appendix A: Best Practice Coding Guidelines....................................................385

Appendix B: SystemVerilog Reserved Keywords...............................................391

B.l All SystemVerilog-2012 reserved keywords............................................................... 391
B.2 Verilog-1995 reserved keywords ................................................................................ 393
B.3 Verilog-2001 reserved keywords ................................................................................ 394
B.4 Verilog-2005 reserved keywords ................................................................................ 394
B.5 SystemVerilog-2005 reserved keywords......................................................................395
B.6 SystemVerilog-2009 reserved keywords......................................................................396
B.7 SystemVerilog-2012 reserved keywords......................................................................396
B. 8 SystemVerilog-2017 reserved keywords......................................................................396

Appendix C: X Optimism and X Pessimism in RTL Models............................397

C. 1 Introducing My X .........................................................................................................398
C.2 How did my one (or zero) become my X? ...................................................................399
C.2.1 Uninitialized 4-state variables........................................................................ 399
C.2.2 Uninitialized registers and latches.................................................................. 400
C.2.3 Low power logic shutdown or power-up........................................................ 401
C.2.4 Unconnected module input ports.................................................................... 401
C.2.5 Multi-driver Conflicts (Bus Contention)........................................................ 401
C.2.6 Operations with an unknown result................................................................ 401
C.2.7 Out-of-range bit-selects and array indices...................................................... 401
C.2.8 Logic gates with unknown output values....................................................... 402
C.2.9 Setup or hold timing violations....................................................................... 402
C.2.10 User-assigned X values in hardware models...................................................402
C.2.11 Testbench X injection..................................................................................... 403
xvi RTL Modeling with SystemVerilog for Simulation and Synthesis

C.3 An optimistic X — is that good or bad?......................................................................403

C.3.1 If...else statements........................................................................................... 404
C.3.2 Case statements without a default-X assignment........................................... 407
C.3.3 Casex, casez and case...inside statements....................................................... 408
C.3.4 Bitwise, unary reduction, and logical operators............................................. 411
C.3.5 And, nand, or, nor, logic primitives................................................................ 412
C.3.6 User-defined primitives.................................................................................. 412
C.3.7 Array index with X or Z bits for write operations..........................................412
C.3.8 Net data types.................................................................................................. 413
C.3.9 Posedge and negedge edge sensitivity............................................................ 414
C.4 A pessimistic X — is that any better? .........................................................................415
C.4.1 If...else statements with X assignments.......................................................... 416
C.4.2 Conditional operator....................................................................................... 417
C.4.3 Case statements with X assignments.............................................................. 419
C.4.4 Edge-sensitive X pessimism........................................................................... 420
C.4.5 Bitwise, unary reduction, and logical operators............................................. 420
C.4.6 Equality, relational, and arithmetic operators................................................. 421
C.4.7 User-defined primitives.................................................................................. 422
C.4.8 Bit-select, part-select, array index on right-hand side of assignments...........423
C.4.9 Shift operations............................................................................................... 423
C.4.10 X-pessimism summary................................................................................... 424
C.5 Eliminating my X by using 2-state simulation............................................................424
C.6 Eliminating some of my X with 2-state data types .....................................................426
C.7 Breaking the rules—simulator-specific X-propagation options..................................428
C.8 Changing the rules — A SystemVerilog enhancement wish list ................................429
C.9 Detecting and stopping my X at the door....................................................................430
C. 10 Minimizing problems with my X ................................................................................ 432
C. 10.1 2-state versus 4-state guidelines..................................................................... 432
C.10.2 Register initialization guidelines.................................................................... 433
C.10.3 X-assignment guidelines................................................................................. 433
C.10.4 Trapping X guidelines.................................................................................... 433
C .ll Conclusions ................................................................................................................. 434
C. 11.1 About the author............................................................................................. 435
C.12 Acknowledgments ....................................................................................................... 435
C.13 References ................................................................................................................... 436

Appendix D: Additional Resources........................................................................437

Index 441
 XVII

List of Examples

This book contains a number o f examples that illustrate the proper usage o f System-
Verilog constructs. A summary o f the major code examples is listed in this section. In
addition to these examples, each chapter contains many code fragments, referred to as
snippets, that illustrate specific features o f SystemVerilog. The source code for the
full examples can be downloaded from http://www.sutherland-hdl.com. Navigate the
menus to “SystemVerilog Book Examples

The Preface provides more details regarding the code examples in this book.

Chapter 1: SystemVerilog Simulation and Synthesis

Example 1-1: SystemVerilog gate-level model of 1-bit adder with carry............................... 8
Example 1-2: SystemVerilog RTL model of 1-bit adder with carry......................................10
Example 1-3: SystemVerilog RTL model of 32-bit adder/subtractor....................................11
Example 1-4: Design model with input and output ports (a 32-bit adder/subtractor)............18
Example 1-5: Testbench for the 32-bit adder/subtractor model.............................................18
Example 1-6: Top-level module connecting the testbench to the design.............................. 20
Example 1-7: A clock oscillator, stimulus and flip flop to illustrate event scheduling........ 29

Chapter 2: RTL Modeling Fundamentals

Example 2-1: RTL model showing two styles of comments................................................. 41
Example 2-2: SystemVerilog RTL model with minimum white space................................. 44
Example 2-3: SystemVerilog RTL model with good use of white space.............................. 44
Example 2-4: Using 'begin_keywords with a legacy Verilog-2001 model.................. 47
Example 2-5: Using 'begin_keywords with a SystemVerilog-2012 model.................. 48

Chapter 3: Net and Variable types

Example 3-1: Example of undeclared identifiers creating implicit nets................................ 80
Example 3-2: Changing the net type for implicit nets............................................................81
Example 3-3: Module port declaration using recommended coding guidelines.................... 89
Example 3-4: Add module with parameterized port widths.................................................. 94
Example 3-5: Model of a configurable RAM using a module parameter list........................ 96
Example 3-6: Adder with configurable data types................................................................ 97

Chapter 4: User-defined Types and Packages

Example 4-1: A package definition with several package items..........................................103
Example 4-2: Using a package wildcard import...................................................................105
Example 4-3: Importing specific package items into a module............................................106
Example 4-4: Explicit package references using the :: scope resolution operator...............107
Example 4-5: Using enumerated type methods for a state machine sequencer....................123
Example 4-6: Package containing structure and union definitions.......................................134
xviii RTL Modeling with SystemVerilog for Simulation and Synthesis

Example 4-7: Arithmetic Logical Unit (ALU) with structure and union ports................... 135
Example 4-8: Using arrays of structures to model an instruction register........................... 137

Chapter 5: RTL Expression Operators

Example 5-1: Using concatenate operators: multiple input status register............................147
Example 5-2: Using concatenate operators: adder with a carry b it....................................... 149
Example 5-3: Using theconditional operator: multiplexed 4-bit register D input............... 151
Example 5-4: Using theconditional operator: 4-bit adder with tri-state outputs................. 152
Example 5-5: Using bitwise operators: multiplexed N-bit wide AND/XOR operation.....156
Example 5-6: Using reduction operators: parity checker using XOR................................. 159
Example 5-7: Using logical operators: set flag when values are within a range................. 163
Example 5-8: Using comparison operators: a relationship comparator............................... 167
Example 5-9: Using case equality operators: a comparator for high address range............ 170
Example 5-10: Using theset membership operator: a decoder for specific addresses........... 172
Example 5-11: Using theshift operator: divide-by-two by shifting right one b it.................. 175
Example 5-12: Using theshift operator: multiply by a power of two by shifting left............ 176
Example 5-13: Performing a rotate operation using concatenate and shift operators........... 179
Example 5-14: Using the streaming operator: reverse bits of a parameterized vector.......... 183
Example 5-15: Using arithmetic operators with unsigned data types................................... 186
Example 5-16: Using arithmetic operators with signed data types....................................... 187
Example 5-17: Using arithmetic operators with real data types............................................ 187
Example 5-18: Using increment and decrement operators.................................................... 192
Example 5-19: Using assignment operators.......................................................................... 197
Example 5-20: Using size casting..........................................................................................205
Example 5-21: Using sign casting for a mixed signed and unsigned comparator.................207

Chapter 6: RTL Programming Statements

Example 6-1: Using if-else to model multiplexor functionality................................... 219
Example 6-2: Using if without else to model latch functionality................................... 220
Example 6-3: Using an if-else-if series to model a priority encoder.................................... 220
Example 6-4: Using if-else-if series to model a flip-flop with reset and chip-enable........ 221
Example 6-5: Using a case statement to model a 4-to-l MUX.........................................225
Example 6-6: Using an case-inside to model a priority encoder.........................................226
Example 6-7: Using a for loop to operate on bits of vectors...............................................229
Example 6-8: Using a for loop to find the lowest bit that is set in avector........................ 231
Example 6-9: Using a repeat loop to raise a value to the power of an exponent................ 234
Example 6-10: Controlling for loop execution using continue and break..........................239

Chapter 7: Modeling Combinational Logic

Example 7-1: Add, multiply, subtract dataflow processing with registered output........... 255
Example 7-2: Function that defines an algorithmic multiply operation..............................264
Example 7-3: State decoder with inferred priority encoded logic (partial code).................267
Example 7-4: State decoder with unique parallel encoded logic (partial code)..................268
List of Examples xix

Chapter 8: Modeling Sequential Logic

Example 8-1: RTL model of a 4-bit Johnson counter..........................................................279
Example 8-2: 4-bit Johnson counter incorrectly modeled with blocking assignments......282
Example 8-3: RTL model of an 8-bit serial-to-parallel finite state machine.......................310

Chapter 9: Modeling Latches and Avoiding Unintentional Latches

Example 9-1: Using intentional latches for a cycle-stealing pipeline..................................326
Example 9-2: Simple round-robin state machine that will infer latches..............................334

Chapter 10: Modeling Communication Buses — Interface Ports

Example 10-1: Master and slave module connections using separate ports..........................358
Example 10-2: An interface definition for the 8-signal simple AMBA AHB bus............... 362
Example 10-3: Master and slave modules with interface ports.............................................363
Example 10-4: Netlist connecting the master and slave interface ports............................... 364
Example 10-5: Interface with modports for custom views of interface signals....................371
Example 10-6: Interface with internal methods (functions) for parity logic.........................373
Example 10-7: Interface with internal procedural code to generate bus functionality..........376
Example 10-8: Parameterized interface with configurable bus data word size.....................378
 xxi

List of Figures

Chapter 1: SystemVerilog Simulation and Synthesis

Figure 1-1: Verilog-95 and Verilog-2001 language features................................................... 4
Figure 1-2: Verilog-2005 with SystemVerilog language extensions....................................... 5
Figure 1-3: SystemVerilog modeling abstraction levels ..........................................................7
Figure 1-4: 1-bit adder with carry, represented with logic gates ............................................. 8
Figure 1-5: Typical RTL-based ASIC design flow ................................................................ 13
Figure 1-6: Typical RTL-based FPGA design flow ............................................................... 16
Figure 1-7: Simulation time line and time slots .....................................................................26
Figure 1-8: Simplified SystemVerilog event scheduling flow .............................................. 28
Figure 1-9: Simulation time line and time slots with some events scheduled ........................30
Figure 1-10: SystemVerilog synthesis tool flow ......................................................................31
Figure 1-11: Diagram of a simple circuit requiring synthesis constraints .............................. 34

Chapter 2: RTL Modeling Fundamentals

Figure 2-1: SystemVerilog module contents ..........................................................................53
Figure 2-2: Design partitioning using sub blocks ..................................................................54

Chapter 3: Net and Variable types

Figure 3-1: Vectors with subfields ........................................................................................73

Chapter 4: User-defined Types and Packages

Figure 4-1: State diagram for a confidence counter state machine ......................................122
Figure 4-2: Packed structures are stored as a vector ............................................................ 128
Figure 4-3: Packed union with two representations of the same storage..............................133
Figure 4-4: Synthesis result for Example 4-7: ALU with structure and union ports ............136
Figure 4-5: Synthesis result for Example 4-8: instruction register with structures ..............138

Chapter 5: RTL Expression Operators

Figure 5-1: Synthesis result for Example 5-1: Concatenate operator (status register) ........148
Figure 5-2: Synthesis result for Example 5-2: Add operator (adder with carry in/out)........149
Figure 5-3: Synthesis result for Example 5-3: Conditional operator (mux’ed register) .......151
Figure 5-4: Synthesis result for Example 5-4: Conditional operator (tri-state output).........152
Figure 5-5: Synthesis result for Example 5-5: Bitwise AND and OR operations ................157
Figure 5-6: Synthesis result for Example 5-6: Reduction XOR (parity checker) ................159
Figure 5-7: Synthesis result for Example 5-7: Logical operators (in-range compare) .........163
Figure 5-8: Synthesis result for Example 5-8: Relational operators (comparator) ..............168
Figure 5-9: Synthesis result for Example 5-9: Case equality, ==? (comparator) ................170
Figure 5-10: Synthesis result for Example 5-10: Inside operator (boundary detector)......... 172
Figure 5-11: Bitwise and arithmetic shift operations ........................................................... 174
Figure 5-12: Synthesis result for Example 5-11: Shift operator, right-shift by 1 b i t ............ 175
Figure 5-13: Synthesis result for Example 5-12: Shift operator, variable left shifts ........... 176
Figure 5-14: Rotate a variable number of times using concatenate and shift operators .......178
Figure 5-15: Synthesis result for Example 5-13: Concatenate and shift (rotate) .................179
xxii RTL Modeling with SystemVerilog for Simulation and Synthesis

Figure 5-16: Synthesis result for Example 5-14: Streaming operator (bit reversal) ............ 183
Figure 5-17: Synthesis result for Example 5-15: Arithmetic operation, unsigned .............. 187
Figure 5-18: Synthesis result for Example 5-16: Arithmetic operation, signed .................. 187
Figure 5-19: Synthesis result for Example 5-18: Increment and decrement operators......... 193
Figure 5-20: Synthesis result after mapping to a Xilinx Virtex®-7 FPG A ........................... 193
Figure 5-21: Synthesis result after mapping to a Xilinx CoolRunner™-II CPLD ............... 194
Figure 5-22: Synthesis result for Example 5-19: Assignment operators .............................. 197
Figure 5-23: Synthesis result for Example 5-20: Size casting ............................................. 205
Figure 5-24: Synthesis result for Example 5-21: Sign casting ............................................. 208

Chapter 6: RTL Programming Statements

Figure 6-1: Synthesis result for Example 6-1: if-else as a M U X ..........................................219
Figure 6-2: Synthesis result for Example 6-2: if-else as a latch ..........................................220
Figure 6-3: Synthesis result for Example 6-3: if-else as a priority encoder ........................221
Figure 6-4: Synthesis result for Example 6-4: if-else as a chip-enable flip-flop .................222
Figure 6-5: Synthesis result for Example 6-5: case statement as a 4-to-l M U X ..................226
Figure 6-6: Synthesis result for Example 6-6: case...inside as a priority encoder ...............227
Figure 6-7: Synthesis result for Example 6-7: for-loop to operate on vector bits ...............230
Figure 6-8: Synthesis result for Example 6-8: for-loop to find lowest bit set .....................232
Figure 6-9: Synthesis result for Example 6-9: repeat loop to raise to an exponent ..............234
Figure 6-10: Synthesis result for Example 6-10 .................................................................. 240

Chapter 7: Modeling Combinational Logic

Figure 7-1: Synthesis result for Example 7-1: Continuous assignment as comb, logic .......255
Figure 7-2: Synthesis result for Example 7-2: Function as combinational logic .................264
Figure 7-3: Synthesis result for Example 7-3: Reverse case statement with priority...........267
Figure 7-4: Synthesis result for Example 7-4: Reverse case statement, using unique .........268

Chapter 8: Modeling Sequential Logic

Figure 8-1: 4-bit Johnson counter diagram ........................................................................ 277
Figure 8-2: Simplified SystemVerilog event scheduling flow ........................................... 279
Figure 8-3: Synthesis result for Example 8-1: Nonblocking assignments, J-Counter..........280
Figure 8-4: Synthesis result for Example 8-2: Blocking assignments, bad J-Counter .........283
Figure 8-5: Blocking assignment to intermediate temporary variable ...............................284
Figure 8-6: Nonblocking assignment to intermediate temporary variable .......................284
Figure 8-7: Synthesis result: Async reset DFF mapped to Xilinx Virtex®-6 FPGA ..........288
Figure 8-8: Synthesis result: Async reset mapped to Xilinx CoolRunner™-II CPLD .......288
Figure 8-9: Waveform showing result of incorrectly modeled asynchronous reset ...........289
Figure 8-10: Synthesis result for a chip-enable flip-flop ..................................................... 290
Figure 8-11: External logic to create the functionality of a chip-enable flip-flop ...............290
Figure 8-12: Synthesis result for an asynchronous set-reset flip-flop .................................293
Figure 8-13: Two flip-flop clock synchronizer for 1-bit control signals .............................296
Figure 8-14: An 8-bit serial value of hex CA, plus a start bit ..............................................299
Figure 8-15: State flow for an 8-bit serial-to-parallel Finite State Machine ........................ 300
Figure 8-16: Primary functional blocks in a Finite State Machine ......................................305
Figure 8-17: Functional block diagram for a serial-to-parallel finite state machine ...........310
Figure 8-18: Synthesis result for Example 8-3: Simple-SPI using a state machine ............312
List of Figures xxiii

Chapter 9: Modeling Latches and Avoiding Unintentional Latches

Figure 9-1: Synthesis result for Example 9-1: Pipeline with intentional latches ...............327
Figure 9-2: Round-robin Finite State Machine state flow .................................................332
Figure 9-3: Synthesis result for Example 9-2: FSM with unintended latches ....................335
Figure 9-4: Synthesis result when using a default case item to prevent latches ................336
Figure 9-5: Synthesis result using a pre-case assignment to prevent latches......................339
Figure 9-6: Synthesis result when using a unique case statement to prevent latches ........343
Figure 9-7: Synthesis result using a default case X assignment to prevent latches ............347
Figure 9-8: Synthesis results when using a pre-case X assignment....................................348

Chapter 10: Modeling Communication Buses — Interface Ports

Figure 10-1: Block diagram connecting a Master and Slave using separate ports ..............357
Figure 10-2: Block diagram connecting a Master and Slave using interface ports .............361

Appendix A: Best Practice Coding Guidelines

Appendix B: SystemVerilog Reserved Keywords

Appendix C: X Optimism and X Pessimism in RTL Models

Figure C-l: Flip-flop with synchronous reset......................................................................404
Figure C-2: 2-to-l selection — MUX gate implementation................................................405
Figure C-3: 2-to-l selection — NAND gate implementation..............................................405
Figure C-4: Clock divider with pessimistic X lock-up........................................................416

Appendix D: Additional Resources

 XXV

Foreword

by Phil M oorby
The creator o f the Verilog language

Verilog is now over 30 years old, and has spanned the years of designing with
graphical schematic entry tools of a few thousand gates, to modem RTL design using
tools supporting millions, if not billions, of gates, all following the enduring predic­
tion of Moore's law. Verilog addressed the simulation and verification problems of the
day, but also included capabilities that enabled a new generation of EDA technology
to evolve, namely synthesis from RTL. Verilog thus became the mainstay language of
IC designers.
Behind the scenes, there has been a steady process of inventing and learning what
was needed and what worked (and what did not work!) to improve the language to
keep up with the inevitable growth demands. From the public's point of view, there
were the stepping-stones from one published standard to the next: the first published
standard in 1995, the eagerly awaited update of Verilog in 2001, the final of the older
Verilog standard in 2005, and the matured System Verilog standard in 2012, just to
name some of the main stones.
I have always held the belief that for hardware designers to achieve their best in
inventing new ideas they must think (if not dream) in a self contained, consistent and
concise language. It is often said when learning a new natural language that your
brain doesn't get it until you realize that you are speaking it in your dreams.
Over the last 15 years, Verilog has been extended and matured into the System Ver­
ilog language of today, and includes major new abstract constmcts, test-bench verifi­
cation, formal analysis, and C-based API’s. SystemVerilog also defines new layers in
the Verilog simulation strata. These extensions provide significant new capabilities to
the designer, verification engineer and architect, allowing better teamwork and co­
ordination between different project members. As was the case with the original Ver­
ilog, teams who adopt SystemVerilog based tools will be more productive and pro­
duce better quality designs in shorter periods. Many published textbooks on the
design side of the new SystemVerilog assumed that the reader was familiar with Ver­
ilog, and simply explained the new extensions. It is time to leave behind the stepping-
stones and to teach a single consistent and concise language in a single book, and
maybe not even refer to the old ways at all!
XXVI RTL Modeling with SystemVerilog for Simulation and Synthesis

If you are a designer or architect building digital systems, or a verification engineer

searching for bugs in these designs, then SystemVerilog will provide you with signif­
icant benefits, and this book is a great place to learn the design aspects of SystemVer­
ilog and the future of hardware design.
Happy inventing...

P hil Moorby,
M ontana Systems, Inc.
M assachusetts, 2016
 X X V II

Preface

SystemVerilog, officially the IEEE Std 1800™ standard, is a “Hardware Design

and Verification Language”. The language serves a dual purpose: to model digital
design behavior, and to program verification testbenches to stimulate and verify the
design models.
This book is based on the IEEE Std 1800-2012 and proposed IEEE Std 1800-2017
SystemVerilog standards. The 1800-2012 SystemVerilog standard was the version
currently in use at the time this book was written. The 1800-2017 standard was in the
process of being finalized.
SystemVerilog is the latest generation of what was originally called Verilog. Sys­
temVerilog adds powerful language constructs for modeling and verifying the behav­
ior of designs that are ever increasing in size and complexity. These extensions to
Verilog fall into two major groups: design modeling enhancements, and verification
enhancements.
This book, RTL Modeling with SystemVerilog fo r Simulation and Synthesis,
focuses on using SystemVerilog for modeling digital ASIC and FPGA designs at the
RTL level of abstraction. A companion book, SystemVerilog fo r Verification1, covers
verifying correct functionality of large, complex designs.

W hy this book

I (Stuart Sutherland) teach corporate-level SystemVerilog training workshops for

companies throughout the world, and provide SystemVerilog consulting services. As
a course developer and trainer, I have been disappointed with the offering of System­
Verilog books for design and synthesis. There are a few books that offer a primer-like
overview of SystemVerilog, many books that focus on the verification aspects of Sys­
temVerilog, and several books that cover the long-obsolete Verilog-2001 language for
hardware design. A few of these older Verilog based books have been updated to
show some SystemVerilog features, but the traditional Verilog roots are still evident
in the coding styles and examples of those books.
This book addresses these shortcomings. The book was written with SystemVerilog
as its starting point, rather than starting with traditional Verilog and adding System­
Verilog features. The focus is writing RTL models of digital designs, using System­
Verilog constructs that are synthesizable for both ASIC or FPGA devices. Proper
coding styles for simulation and synthesis are emphasized throughout the book.

1. Chris Spear and Greg Tumbush, “SystemVerilog for Verification, Third Edition”, New York, NY:
Springer 2012, 978-1-4614-0715-7.
X X V III RTL Modeling with SystemVerilog for Simulation and Synthesis

Intended audience for this book

This book is for all engineers who are involved with digital IC design. The book is
intended to serve as both a learning guide and a reference manual on the RTL synthe­
sis subset of the SystemVerilog language. The book presents SystemVerilog in the
context of examples, with an emphasis on correct, best-practice coding styles.

NOTE
This book assumes the reader is already familiar with digital logic design.

The text and examples in this book assume and require an understanding of digital
logic. Concepts such as AND, OR and Exclusive-OR gates, multiplexors, flip-flops,
and state machines are not defined in this book. This book can be a useful resource in
conjunction with learning and applying digital design engineering skills.

Topics covered in this book

This book focuses on the portion of SystemVerilog that is intended for representing
digital hardware designs in a manner that is both simulatable and synthesizable.
Chapter 1 presents a brief overview of simulating and synthesizing the SystemVer­
ilog language. The major differences between SystemVerilog and traditional Verilog
are also presented.
Chapter 2 provides an overview of RTL modeling in SystemVerilog. Topics include
SystemVerilog language rules, design partitioning, and netlists.
Chapter 3 goes into detail on the many data types in SystemVerilog, and which data
types are useful in RTL modeling. The appropriate use of 2-state and 4-state types is
discussed. The chapter also presents using data arrays as synthesizable, RTL model­
ing constructs.
Chapter 4 presents user-defined types, including enumerated types, structures, and
unions. The use of packages as a place to declare user-defined types is also covered.
Chapter 5 explains the many programming operators in SystemVerilog, and shows
how to use these operators to code accurate and deterministic RTL models.
Chapter 6 covers the programming statements in SystemVerilog, with an emphasis
on proper RTL coding guidelines in order to ensure the code will synthesize to the
gate-level implementation intended. Several programming statements that System­
Verilog adds to the original Verilog language make it possible to model using fewer
lines of code compared to standard Verilog.
Chapter 7 gives an in-depth look at writing RTL models of combinational logic.
Best-practice coding recommendations are given for writing models that will simulate
and synthesize correctly.
Preface X X IX

Chapter 8 examines the correct way to model RTL sequential logic behavior. Topics
include synchronous and asynchronous resets, set/reset flip-flops, chip-enable flip-
flops, and memory devices, such as RAMs.
Chapter 9 presents the proper way to model latches in RTL models, and how to avoid
unintentional latches.
Chapter 10 discusses the powerful interface construct that SystemVerilog adds to tra­
ditional Verilog. Interfaces greatly simplify the representation of complex buses and
enable the creation of more intelligent, easier to use IP (intellectual property) models.
Appendix A summarizes the best-practice coding guidelines and recommendations
that are made in each chapter of the book.
Appendix B lists the set of reserved keywords for each generation of the Verilog and
SystemVerilog standards.
Appendix C is a reprint of a paper entitled I ’m Still In Love With My X, regarding
how X values propagate in RTL models. The paper recommends ways to minimize or
catch potential problems with X-optimism and X-pessimism in RTL models.
Appendix D lists some additional resources that are closely related to the topics dis­
cussed in this book.

Book examples
The examples in this book illustrate specific SystemVerilog constructs in a realistic,
though small, context. Complete code examples list the code between two horizontal
lines, as shown below. This book use a convention of showing all SystemVerilog key­
words in bold.

SystemVerilog RTL model of 32-bit adder/subtractor (same as Example 1-3, page 11)
module rtl_adder_subtractor
(input logic elk, // 1-bit scalar input
input logic mode, // 1-bit scalar input
input logic [31:0] a, b, // 32-bit vector inputs
output logic [31:0] sum // 32-bit vector output
);
always_ff 0 (posedge elk) begin
if (mode == 0) sum <= a + b;
else sum <= a - b;
end
endmodule: rtl adder subtractor

Each chapter also contains many shorter examples, referred to a code snippets.
These snippets are not complete models, and are not encapsulated between horizontal
lines. The full source code, such as variable declarations, is not included in these code
XXX RTL Modeling with SystemVerilog for Simulation and Synthesis

snippets. This was done in order to focus on specific aspects of SystemVerilog con­
structs without clutter from surrounding code.

Obtaining copies of the examples

The complete code for all the examples listed in this book is available for personal,
non-commercial use. They can be downloaded from the Sutherland HDL website, at
sutherland-hdl.com/books/sv_rtl_synthesis/sv_rtl_synthesis_book_examples.zip.

Simulators and synthesis compilers used in this book

NOTE
This book strives to be vendor and software tool neutral. While specific
products were used to test the examples in this book, all examples should run
with any simulator or synthesis compiler that adheres to the IEEE 1800-2012
SvstemVerilog standard.

The examples in this book have been tested with multiple simulation and synthesis
tools, including (listed alphabetically by company name):

• The Cadence Genus RTL Compiler (r ) synthesis compiler.

• The Intel (formerly Altera) Quartus (r ) Prime synthesis compiler.

• The Mentor Graphics Questa™ simulator and Precision RTL Synthesis™ com­
piler.

• The Synopsys VCS ( )

simulator, DC-Ultra(
r r )
synthesis compiler, and Synplify-
Pro® synthesis compiler. The SpyGlass® Lint RTL rule checker was also used
with certain examples.

• The Xilinx Vivado (r ) synthesis compiler.

The software versions used for testing the book examples were the latest versions
available to the author in Q 1-2017. (A few tools did not support a SystemVerilog lan­
guage feature used in one or two examples, but will probably support those language
features in future versions of the tool.)
The Mentor Graphics Precision RTL Synthesis™ compiler was used to generate
the synthesis schematic output shown with many of the examples. This compiler was
selected because the schematics created by this tool were easy to capture in black-
and-white, and to adapt to the page size of the book.
Preface xxxi

Other sources of information

Some other resources which can serve as companions to this book include:
IEEE Std 1800-2012, SystemVerilog Language Reference Manual LRM)— IEEE
Standard for SystemVerilog: Unified Hardware Design, Specification and Verification
Language.
Copyright 2013, IEEE, Inc., New York, NY. ISBN 978-0-7381-8110-3. Elec­
tronic PDF form, (also available in soft cover).
This is the official SystemVerilog standard. The book is a syntax and semantics
reference, not a tutorial for learning SystemVerilog. It can be downloaded for free
from https://standards.ieee.org/getieeeZl800/download/1800-2012.pdf.
System Verilog fo r Verification—A Guide to Learning the Testbench Language Fea­
turest third edition by Chris Spear and Greg Tumbush.
Copyright 2012, Springer, New York, New York. ISBN 978-1-4614-0715-7.
The Spear and Tumbush book is a companion to this book, with a focus on the
verification side of SystemVerilog. For more information, refer to the publisher’s
web site: h ttp ://www. springer, com/engineering/circui ts+%2 6+systems/book/
978-1-4614-0714-0.
Additional resources related to the topics in this book are listed in Appendix D.

Acknowledgements
I am grateful to all those who have helped with this book. I would like to specifi­
cally thank those that provided invaluable feedback by reviewing specific chapters
the book for technical content and accuracy. These reviewers include: Leah Clark,
Clifford Cummings, Steve Golson, Kelly Larson, Don Mills and Chris Spear. I am
also grateful to Shalom Bresticker, who answered many technical questions over the
period of time that I wrote this book.
Special recognition is extended to Don Mills, who provided valuable feedback and
assistance throughout the writing process. Don recommended ideas for many of the
book examples, and helped with testing the code examples on multiple simulators and
synthesis compilers.
I am especially appreciative of Phil Moorby, the creator of the original Verilog lan­
guage and simulator, for writing the foreword for this book and for creating a long-
lasting design and verification language for the digital design industry.
I would also like to recognize and thank my wonderful wife, LeeAnn Sutherland,
for her painstaking reviews of this book for grammar, punctuation and readability.*

* * *
 1

Chapter 1
SystemVerilog Simulation and Synthesis

Abstract — This chapter explores the general concepts of modeling hardware using
SystemVerilog, and the roles of simulation and synthesis in the hardware design flow.
Some of the major topics presented in this section are:
• The difference between Verilog and SystemVerilog
• RTL and gate-level modeling
• Defining an RTL synthesis subset of SystemVerilog
• Modeling ASICs and FPGAs
• Model verification testbenches
• The role and usage of digital simulation with SystemVerilog
• The role and usage of digital synthesis with SystemVerilog
• The role and usage of SystemVerilog lint checkers

1.1 Verilog and SystemVerilog — a brief history

Verilog and System Verilog are synonymous names for the same Hardware Descrip­
tion Language (HDL). SystemVerilog is the newer name for the official IEEE lan­
guage standard, and replaces the original Verilog name.
Verilog began as a proprietary design language in the early 1980s, for use with a
digital simulator sold by Gateway Design Automation. The proprietary Verilog HDL
was opened to the public domain in 1989, and standardized by the IEEE as an interna­
tional standard in 1995 as IEEE Std 1364-1995™ (commonly referred to as “Ver-
ilog-95”). The IEEE updated the Verilog standard in 2001 as the 1364-2001™
standard, referred to as “Verilog-2001”. The last official version under the Verilog
name was IEEE Std 1364-2005™. In that same year, the IEEE released an extensive
set of enhancements to the Verilog HDL. These enhancements were initially docu­
mented under a different standards number and name, the IEEE Std 1800-2005™
SystemVerilog standard. In 2009, the IEEE terminated the IEEE-1364 standard, and
merged Verilog-2005 into the SystemVerilog standard, with the standards number
IEEE Std 1800-2009™ standard. Additional design and verification enhancements
were added in 2012, as the IEEE Std 1800-2012™ standard, referred to as System-
2 RTL Modeling with SystemVerilog for Simulation and Synthesis

Verilog-2012. At the time this book was writting, the IEEE was nearing completion
of a proposed IEEE Std 1800-2017™ standard, or SystemVerilog-2017. This version
only corrects errata in the 2012 version of the standard, and adds clarifications on the
language syntax and semantic rules.

1.1.1 The Original Verilog

Verilog began in the early 1980s as a proprietary Hardware Description Language
(HDL) from a company called Gateway Design Automation. The primary author of
the original Verilog HDL is Phil Moorby. In the early 1980s, digital simulation was
becoming popular. Several Electronic Design Automation (EDA) companies provided
digital simulators, but there were no standard Hardware Description Languages to use
with these simulators. Instead, each simulator company provided a proprietary model­
ing language specific to that simulator. Gateway Design Automation was no different.
The simulator product was named “Verilog-XL” (short for “Verification Logic,
Accelerated”), and its accompanying modeling language was called “Verilog”.
The Verilog-XL simulator and the Verilog HDL became the dominant simulator
and language for digital design in the latter half of the 1980s. Some factors that attrib­
uted to this popularity included: 1) speed and capacity, 2) ASIC timing accuracy, 3)
an integrated design and verification language, and 4) digital synthesis.
1. The Verilog-XL simulator was faster and had a larger design size capacity than
most, if not all, of its contemporary competing simulators, allowing companies to
more efficiently design larger, more complex digital integrated circuits (ICs).
2. In the latter half of the 1980s, many electronic design companies were switching
from custom ICs to Application Specific ICs (ASICs). Gateway Design Automa­
tion worked closely with major ASIC suppliers, and Verilog-XL became the
golden reference simulator for ensuring timing accurate ASIC simulations. This
preference by ASIC suppliers helped make Verilog a preferred language for com­
panies involved in designing ASICs.
3. The major digital simulators in the 1970s and early 1980s typically involved
working with two proprietary languages: a gate-level modeling language to
model the digital logic, and a separate proprietary language to model stimulus
and response checking for simulation. Gateway Design Automation departed
from this tradition, and integrated gate-level modeling, abstract functional mod­
eling, stimulus and response checking all into a single language, called Verilog.
4. The fourth reason many companies adopted the Verilog language for the design
of ASICs was the ability to synthesize abstract Verilog models into gate-level
models. In the latter half of the 1980s, Synopsys, Inc. struck an agreement with
Gateway Design Automation to use the proprietary Verilog language with the
Synopsys Design Compiler (DC) digital synthesis tool. The ability to both simu­
late and synthesize the Verilog language was a tremendous advantage over all
other proprietary digital modeling languages at that time.
Exploring the Variety of Random
Documents with Different Content
immerse the hand and arm in cold water, leaving the extreme part, at
which the agony is felt, out of it; we may have a wet compress about
the painful member, but the greater and more effective applications
must be made on other parts, contiguous to the one affected. From
these well established principles I infer that the vaginal injections,
whatever may be claimed for them, are of minor importance, when
compared with the external and more general applications to which I
have referred, as a remedy for after-pains. It is to be remembered,
likewise, that patients, from the extreme sensitiveness and soreness
of these parts after delivery, dread very much applications of this
kind. The external applications are soothing, pleasant, and
wonderfully effective in relieving soreness, but not so with the
internal applications.
Thus, then, it will be perceived, that I place great reliance upon the
shallow-bath, tepid, cool, or cold, with prolonged friction by the wet
hands, the sitting-bath, the cold wet compresses, often repeated, the
wet girdle, cold wet cloths upon the thighs and back, the folded
packing sheet, with covering sufficient to keep the patient
comfortable, tepid or cold clysters, and water-drinking, together with
good nursing throughout, as a remedy for the distressing affection of
which I have been treating.
 LETTER XXXIII.
THE LOCHIAL DISCHARGE.

The Mosaic Law concerning Purification of Women—Nature of the Lochia—

Excessive and Offensive Discharge—Treatment of Suppression of the Lochia.

We read in the New Testament, in reference to the birth of the

Saviour (Luke ii., 21, 22), that “when eight days were accomplished
for the circumcising of the child, His name was called Jesus, which
was so named by the angel before He was conceived in the womb;”
that “when the days of her purification, according to the law of
Moses, were accomplished, they brought Him to Jerusalem, to
present Him to the Lord.”
These passages refer to the Mosaic law (Leviticus, chap. xii.),
which is as follows:
“And the Lord spake unto Moses, saying, Speak unto the children
of Israel, saying, If a woman hath conceived seed, and born a male
child, then she shall be unclean seven days; according to the days of
the separation for her infirmity, shall she be unclean.
“And in the eighth day the flesh of his foreskin shall be
circumcised.
“And she shall then continue in the blood of her purifying three-
and-thirty days; she shall touch no hallowed thing, nor come into the
sanctuary, until the days of her purifying be fulfilled.
“But if she bear a maid child, then she shall be unclean two weeks,
as in her separation: and she shall continue in the blood of her
purifying threescore and six days.”
This law refers to what is called in medical science the lochia, or
lochial discharge, the term being derived from a Greek word
signifying “a woman in childbed.”
After the birth has taken place and the placenta has been removed,
the woman experiences a discharge from the womb, which is at first
red in color, consisting, probably, of little else than blood; afterward
it acquires a greenish hue, possessing a peculiar and disagreeable
odor.
The lochia is considered purifying in its character. It is a natural
discharge which oozes from the orifices of blood-vessels, laid open by
the separation of the placenta from a portion of the internal surface
of the womb. In all cases wherein a wound is made in the living body,
or wherever the blood-vessels are by any cause laid open, there must
be necessarily more or less discharge before the healing can be fully
accomplished; and the same principle holds good in the womb as in
other parts of the body.
In quantity, the lochia varies much in different cases; it may be
three or four times as abundant, apparently, in one case as in
another, both patients recovering, however, with equal facility or
difficulty.
The length of time varies also as much as the quantity of this
discharge. It may last for a few hours only, for days, but more
commonly for weeks; fourteen to twenty-one days may be stated as
its usual duration. Something, I think, depends upon the treatment;
cleanliness certainly has its effect in these cases. If a woman wash
herself three or four times daily, and keep herself at all times as
strictly clean as the circumstances will admit of, the process of
healing must be materially hastened, the discharge rendered smaller
in quantity, and less offensive in character.
Excessive Discharge.—From various causes the lochia sometimes
becomes excessive in quantity. More anciently, when the humeral
pathology was much in vogue, this discharge was studied with more
attention than in modern times, and our forefathers in medicine may
have gone to an extreme in this matter; but certain it is, the
importance of the lochia should not be overlooked.
A piece of placenta retained may augment the flow of the
discharge. If the patient experience vomiting, very offensive and too
great a quantity of lochia, or if very severe after-pains come on, there
is some reason to suspect that such is the case; so, also, portions of
the membranes may have been retained, causing some degree of
irritation. Any thing which debilitates the system, such as too much
lying in bed, overheated rooms, too much sitting up, walking, or
other exercise, and especially too much excitement in the way of
seeing company, gossiping friends, etc., may likewise cause an
excessive discharge. In those cases where a portion of the placenta is
retained, removing it is often considered the best remedy; but
according to one very able author and practitioner, Dr. Blundell,
“unless the symptoms are very urgent, it is better to refrain from
manual operations; left to its own efforts, the uterus will, perhaps,
more safely clear itself.”
Treatment.—In all these cases the general principles of
management are plain and easily understood. We must, of course, as
far as possible, remove the causes of the difficulty; we must also treat
the system constitutionally in order to improve the general strength.
Cooling wet compresses upon the abdomen and genitals, frequent
ablutions, the sitting-bath, and in some cases the packing wet-sheet,
will prove a highly useful means; vaginal injections of water, tepid
injections in the bowels, and drinking of pure, soft water, are also to
be recommended.
Offensive Discharge.—There is one condition of the lochia which is
very troublesome from its offensive smell and extremely loathsome
character. In such cases the red discharge ceases and is succeeded by
a profuse watery one of a greenish color, and which is sometimes
called by women “the green water;” it is frequently so acrid as to
excoriate the parts upon which it runs. It is often attended with a
good deal of general debility, causing, not unfrequently, a
considerable degree of hectic fever.
The water processes, practiced in a manner suited to the
exigencies of the case, cannot be too highly recommended or too
much praised, as a means of purification and cure in this offensive
and troublesome malady.
Suppression of the Discharge.—Women, in general, very much
fear a sudden cessation of the lochia, and for the reason that it is
generally well understood that this occurrence is attended with
circumstances of an unfavorable character. But while patients
should, on the one hand, always be careful and considerate in
matters pertaining to health, they should, on the other, not become
at once frightened at every little cessation of the discharge. As I have
before said, it may cease of itself spontaneously, and without harm to
the system, within a few hours after birth. Dr. Good, indeed, tells us
“that in some women who have healthy labors, there is no lochial
discharge whatever, the blood-vessels of the uterus contracting
suddenly and closely as soon as the red blood ceases to flow.” This
celebrated author points out an example of this kind that occurred to
Professor Frank, even after a third natural delivery; the patient,
moreover, having been from a girl as destitute of menstruation as
afterward of lochia; yet her health was in no respect interfered with.
Diagnosis and Treatment.—If thus, on examination, we find that
there is no increase in the frequency of the pulse, or other
unfavorable symptoms, no fear whatever need be entertained. If the
patient has taken cold, causing an inflammation of the womb, an
accident which may be known by sensations of chilliness along the
spine, accompanied, perhaps, with general rigors, by the roundness,
hardness, and tenderness of the womb, which may be easily felt
through the abdominal coverings; and, if added to all these
symptoms, there is great heat of the skin and frequency of the pulse,
rising to 110°, 120°, 130°, or even more; then we may know that the
suppression is a morbid one—one, too, which if not promptly treated,
may soon end in death.
Patients, under such circumstances, have great fears of cold; they
bundle themselves up, and heat their systems in all manner of ways,
as if their physical salvation depended wholly upon such a course.
But the truth is, the mischief has been already done; once there is a
severe inflammation or fever upon a patient, it is impossible for her
to take another cold until the previous one has been cured.
This fact, then, indicates clearly what the proper treatment of such
cases should be; we must treat them on the same general principles
of all other inflammations; and as soon as the fever and
inflammation are sufficiently removed by means of ablutions, wet
compresses, injections, water-drinking, and, if necessary, the
packing wet-sheet, the discharge—if any such be at all necessary—
must follow as inevitably as a stone falls to the ground. Thus it is,
then, that under certain circumstances, a cold may give fever and
inflammation; while under other circumstances, cold cures these
symptoms. These operations of nature, simple and beautiful as they
are, must prove highly interesting to every reflecting mind; and they
show, moreover, the goodness, benevolence, and design of the
Creator, in furnishing us everywhere, so abundantly, a remedy so
powerful and safe as pure, cold water.
In all those diseases following delivery, the excellent Dr. Good
observes, “That cleanliness and purity of air are of the utmost
importance,” and “that, without these, no plan whatever can succeed;
and with them, no other plan is often wanted.” “They are, moreover,”
he continues, “of as much moment to the infant as to the mother. It
is a striking fact that, in the space of four years, ending in 1784, there
died in the lying-in-hospital of Dublin—at that time a badly-
ventilated house—2944 children out of 7650; though after the
ventilation was improved, the deaths within a like period, and from a
like number amounted to not more than 279.”
 LETTER XXXIV.
OF CHILDBED FEVER.

Milk Fever as distinguished from Puerperal Fever—The great Danger of Childbed

Fever—Its Symptoms and Nature—Modes of Treatment—Is it a Contagious
Disease?

In the course of two or three days usually after the birth of the
child, the woman experiences more or less febrile excitement of the
system. This is what is termed milk fever, it being connected with the
coming on of the lacteal secretion. The attack sometimes amounts to
a “smart febrile fit, preceded by shivering, and going off with a
perspiration.” It is not dangerous, seldom lasts over twenty-four
hours, and during the time of its appearance the breasts are full,
hard, and painful, which distinguishes this from more dangerous
fevers.
Puerperal or childbed fever is a very different thing from the
foregoing, and is reckoned by physicians as being one of the most
fearful of maladies.
According to the celebrated Dr. Blundell, “women after their
delivery in general do pretty well, although no attentions are paid to
them;” and it is the testimony of the same distinguished author, that
“when the constitution is good, and the circumstances are not
extraordinary, the less they are interfered with the better;” and yet it
must be admitted by every candid and reflecting mind, that, do what
we may in all the known possible ways of fortifying and invigorating
the general health, woman must, ever in childbirth be subject to
some of the most fearful diseases and accidents to which the human
frame is liable. Suppose it be only one in fifty, one hundred, or one
thousand, that is to be attacked under such circumstances with a
threatening and most dangerous malady, who is there that wishes his
wife, sister, or friend to be that one—and that one, too, to be
subjected to the treatment of an ignorant or unprincipled quack,
whether of the male or female stamp? It is for the cases of exception,
then, and not the rule, that physicians should toil long and hard in
their efforts to remedy the ills to which human nature now is and
ever must be subject.
I am led to these remarks, partly from the necessity of the case, but
more from the fact, that there are those in modern times who,
through ignorance, as we must charitably conclude, would mislead
the public on this most important subject. I will go as far as any one
in encouraging woman to pursue a rational course in the preparation
for, and the consummation of, childbirth. Those who have read my
humble efforts at authorship on this subject hitherto, must, I am
confident, be aware of this. At the same time, while I would
encourage woman—encourage her even more than any of us have yet
done—I would have her to understand that there are dangers, fearful
and imminent dangers, always attending the parturient state. Be
these dangers only one in a hundred or thousand cases, they are yet
dangers; and who among us, even of the most experienced, can tell
who is to be the subject of them, and who is not? It behooves to be
ever watchful in these important matters of the healing art.
I propose, then, here to speak of that most formidable, most
fearful of all diseases to which the puerperal condition is liable, the
puerperal fever—the puerperal plague, as it has been called—so
sudden in its attack, so rapid in its progress, and so fatal in its effects
—fatal, that is, according to the old methods of treatment—
sanctioned, as they are, by the usage of ages.
Time of Occurrence.—The puerperal or childbed fever comes on
usually within the fourth day, reckoning that of delivery the first. It
happens oftenest the second or third day. It may come on the first
day, or it may, though rarely, attack the patient eight, ten, or more
days after delivery. The later the day, the less the danger, as a general
fact.
Symptoms.—Childbed fever is more commonly ushered in by a
chill, which is not, however, long in duration. This is experienced
most along the back, and sometimes about the shoulders and neck.
The chill varies in degree of intensity in different cases; with some
patients there is a degree of chattering, such as occurs in a severe
ague fit; with others there is very little of the symptom; and in some
cases no chill whatever is experienced. These last, however, must be
the exception to the rule. In almost every conceivable case, a degree
of chilliness, greater or less, is experienced. As in other
inflammations, this chill is followed by fever. The intensity of the
chill is considered no measure of the vehemence of the subsequent
fever; the most terrific fever may follow very mild chills, and the
contrary. Some regard that there is most danger to be apprehended
when the chills are of a mild character.
Here I ought to remark, that patients should not be frightened at
every little chill they may experience. The coming on of the milk—the
milk fever, as it is called—heat in the breast, and a variety of
circumstances other than those of childbed fever, may be preceded
by or attended with chills. Indeed, almost every mother with a new-
born child experiences more or less of chilly symptoms; and yet
fortunately but few are attacked with that terrible malady of which
we are treating. So much by way of encouragement in regard to the
matter of chills.
In connection with the rigors before mentioned, the patient
complains of pains in the abdomen; these may be so slight as to be
scarcely perceptible to pressure on the part, or they may be so violent
and severe that the gentlest touch of the finger is regarded with
apprehension, and the weight of the bed-clothes proves a burden
that cannot be borne. “Sometimes the pain,” says Professor Meigs,
“which is, at the onset of puerperal fever, felt in the hypogastric
region, is too intense to be borne by any human patience; and no
exhortation or recommendation can prevent the woman from crying
out aloud, or even screaming with her agony. All over the abdomen
these pains may be felt, above, below, to the right, to the left, in the
region of the diaphragm, and in the lumbar region; this diffusion,
however, is neither constant nor frequent, and it is found, especially
in the less malignant varieties of the disease, that it is in the region of
the navel, and more especially below it, that the patient complains.”
Severe after-pains may be experienced in connection with the
disease, or the reverse. Little or no fever may occur in connection
with severe pain, and so the contrary. If the pain is circumscribed, as
we say—confined mostly to one spot—it is far more favorable; but if
the pain and tenderness are spread over a large surface, beware, lest
there be mischief at hand. If the pain be even slight, and yet diffused
extensively over the surface of the abdomen, we must take heed lest
we get into trouble that will imminently endanger the patient’s life.
The pulse always rises high in childbed fever. This is one of the
most distinctive features of the disease. It is seldom lower than 115 or
120 per minute, except when it is giving way before the power of
remedial means. More commonly it rises to from 130 to 140 beats
per minute, and it has been known to rise as high as 160 or 170.
These last, however, are extreme cases—exceptions to the general
rule.
Besides the symptoms enumerated, there sometimes occurs
headache, sometimes vomiting, and at others purging, which last
symptom is probably in general a good omen.
Duration of the Disease,—Puerperal fever, like most other
diseases, is not very uniform in its duration. It is, however, in general
short. It may last for a number of days—for many days, if we reckon
the convalescence a part of the disease. On the other hand, it may,
like the plague itself carry the patient off within the first twenty-four
hours of the attack. Three or four days is reckoned to be the average
duration of childbed fever, when it occurs in the epidemic form.
Professor Meigs has well explained why it is that childbed or
peritoneal fever is so serious and dangerous a malady as it is. He
observes:
“The peritoneum (the lining, membrane of the abdomen), a serous
membrane, known for ages as one of the tissues most ready to take
on inflammation, undergoes in labor, and during lying-in, changes of
the greatest importance. Its great extent may be known by
computing the superficial contents of that portion of the serous
membrane which invests the alimentary canal. This canal is about
forty feet in length, and its outer coat is composed of peritoneum. If
cut up by the enterotome, it would be at least four inches wide and
forty feet long, affording a superficies of more than thirteen feet, to
which should be added the superficial contents of the remainder of
the membrane, where it invests the liver, the epiploon, the mesentery
and mesocolon, besides the ligamenta lata, and all the other parts
which derive from it their serous covering. This vast surface inflames
rapidly and totally, and passes through the stage of inflammation
with extraordinary speed. It cannot happen that it shall ever be
extensively inflamed without a coincident exhibition of the greatest
disorder in the functions of the nervous organs directly implicated in
its structure, or possessing with it physiological relations that could
not be safely disturbed. The peritoneum is the investiture of the
abdominal organs; the peritoneal coat of the stomach is as truly a
part of the organ as its muscular or mucous coat; the same is true as
to the peritoneum that invests the liver, that of the spleen, and the
same truth is of the utmost import when it is stated with regard to
the peritoneal coat of the whole alimentary apparatus. It is clear that
extensive or universal inflammation of the peritoneal membrane is
inflammation of all or many of the organs contained within the cavity
of the abdomen. A great puerperal peritonitis, therefore, may be
properly regarded as a complex inflammation of a vast number of
organs indispensable to existence. Why should we be astonished,
then, to see the power of the nervous mass sink under the invasion of
causes of destruction so great and so pervading?
“Seeing that the superficies of the peritoneum is equal, probably,
to thirteen or fourteen feet, we should have abundant reason to
dread so extensive an inflammation from the constitutional irritation
which it alone would produce; but when, in addition to that
consideration, we take into view the great affusions which may
ensue, the suppurations, the interruption of the intestinal functions,
the depravation of the actions of the liver, etc., which are occasioned
by it, we have still greater reason to deprecate its attack, and to seek
for the justest views of its nature, and of the remedies most
appropriate for its cure.”
Professor Meigs elsewhere judiciously remarks, that, considering
the changes that take place in the reproductive tissues at childbirth,
“there is, in fact, greater reason for surprise, when we find it not
followed by inflammation, than when we meet with the most violent
and destructive cases of that affection.”
Treatment.—In the year 1846, I treated (in connection with a
missionary friend and physician, who is now in Siam) a premature
case of childbirth, which, to say the least, threatened to become one
of severe puerperal fever. The case was an important one, and as
such I here present it to the reader. It was written out with great care
and accuracy at the time by the medical friend referred to. I give it in
his own words:
“March 19, 1846.—Desirous of availing myself of an opportunity
which Dr. Shew kindly afforded me of witnessing the hydropathic
treatment of cases of labor, I accompanied him to No. — Second
Street, where he had been summoned a few minutes before, to attend
Mrs. S., who was then in need of his services.
“We found the patient an intelligent woman, of the nervous
temperament, with her constitution much broken down—though she
was but thirty-one years of age—by the results of severe previous
labors, the last a miscarriage. After some of her former
confinements, she had been weeks and months in recovering. In one
case, when, she was treated for puerperal fever, her husband paid in
one year not less than one hundred and fifty dollars—no trifling sum
out of the earnings of a working man with a large family—to the
apothecary alone, for leeches and medicines. The patient had always
been in the habit of using strong tea and coffee; drank the mineral
water of the city wells; for some months had relished nothing but the
little delicacies sent in by her friends, and throughout the winter had
been able to do little or nothing at home.
“In consequence of excessive fatigue, a few days before, in ‘house-
hunting,’ as she called it, she had been seized on Tuesday, the 17th, at
10 A. M., at the close of the fifth month of her pregnancy, with the
pains of labor—her former miscarriage having, of course, induced a
predisposition to another. These pains increased in frequency and
severity till they caused the greatest suffering, and prevented all
sleep on Wednesday night and Thursday, up to the hour (3 P. M.)
when she sent for Dr. Shew.”
Here, then, was a patient, whose previous history, impaired
constitution, loss of sleep, and exhaustion from intense and almost
incessant suffering, protracted now for more than two days, seemed
to promise any thing but a speedy recovery, even should delivery be
safely effected. It should be added that, up to the time, she was an
utter stranger even to the hydropathic treatment.
“Her bowels having been moved the day before, all that was
deemed necessary was to render the condition of the patient more
comfortable, by resorting to sedative frictions along the spine with a
towel wrung out of cold water, and to the tepid hip-bath, with
sponging and rubbing the whole surface of the body. After this, less
complaint was made, till soon after 6 P. M., when there was a sudden
aggravation of the bearing-down pains, resulting in the delivery of a
well-formed but still-born male child, of apparently five months.
“In about fifteen minutes the after-birth was detached, and taken
away. Not even the usual amount of hemorrhage occurred. A
bandage was applied to the abdomen, as the patient expressed a wish
for it; and after resting awhile, a little panada was given her as
nourishment.
“Mrs. S. continued very comfortable through the evening; no
excess of the natural discharge; complained only of exhaustion, and
slight difficulty of passing urine. As there was some heat of the
surface—the pulse being from 90 to 100—tepid sponging was
resorted to, which proved very grateful to the patient.
“Second Day (Friday), Seven, A. M.—Found the patient had
obtained considerable sleep at intervals during the night; felt very
comfortable, though occasionally had slight pains in the abdomen;
tongue moist; pulse 81; had passed a little water during the night,
but with difficulty; had a strong desire for a cup of coffee, but
persuaded her to take a little panada in its place; had not much
appetite; was permitted to sit up for a few minutes while her bed was
made.
“Half-past Eleven, A. M.—Mrs. S. still very comfortable; found her
sitting up in the rocking-chair, the very picture of convalescence.
Sponging enjoined, if any feverishness should arise.
“Three, P. M.—Dr. S. sent for, as the patient had been seized a few
minutes before, rather suddenly, with a sharp pain in the left side.
Had been drinking a tumbler of cold lemonade. Had a natural
movement of the bowels that morning, and passed a little water. The
tepid sponging of the surface had been neglected. Pain fixed, severe,
pretty constant, remitting only for a moment or so. No
corresponding contractions of the uterine tumor observed. Some
pain also complained of in the hip, with which she had, on a former
occasion, been troubled. Up to that time had had no chill. Warm
fomentations were applied, but with little relief.
“Half-past Four, P. M.—A chilliness felt, then shivering,
prolonged, with increase of the fixed pain of the side; pulse 112,
weak; patient restless, anxious, desponding; knitting of the brows,
involuntary weeping. A bottle of warm water was applied to the feet,
and soon after, the chills ceased.
“A large warm enema was now administered; this brought away
considerable fecal matter; and fomentations were applied to the
abdomen. Next, the patient was seated in the hip-bath, at a
temperature of 95°, for fifteen minutes, when water was passed more
freely than before, and a slight nausea experienced. The result of this
was complete abatement, for the time, of the pain in the uterine
region, the diminution of the frequency of the pulse to 90, and great
comfort. The bandage to the abdomen having been removed, to allow
of the bath, was not replaced. If need be, fomentations to be kept up.
“At 7 P. M. found the patient in a profuse perspiration; pain in the
abdomen had lost its acuteness; soreness there was all now
complained of—soreness in the head, ‘in the bones, and all over.’
Abdomen swollen, and tender on pressure; breathing shallow; pulse
110–12; discharge from the womb (the lochial discharge) arrested.
Patient is to be kept quiet; to take no nourishment; no fire to be in
the room.
“At 9¼ P. M., the perspiration still continues; complains of pain in
the hip, but chiefly in the left side, as before, and shooting across the
abdomen; pain now very severe, increased by coughing; breathing
thoracic (shallow), and 28 in the minute; pulse 98; is thirsty; tongue
moistish, with a slight milky coat. Fomentations as usual.
“Half-past Ten, P. M.—Pain increasing in the abdomen and hip;
tenderness increasing; can scarce bear slight pressure on the
abdomen; knees drawn up; restless, discouraged; pulse 100, though
not very full or strong; skin still slightly moist.
“In this critical state of things, when nearly every symptom of that
fearful disease, puerperal fever, was invading the system, and when,
according to the prescribed rules of practice, the most vigorous
antiphlogistic measures would be called for, a plan of treatment was
adopted that was, as it seemed to me, far more likely to kill than to
cure, and which I could not but protest against at the time, but
which, as the result proved, was eminently calculated to turn back
the tide of disease so rapidly setting in. It certainly afforded striking
evidence of the resources of hydropathy, and its promptness and
efficiency in relieving pain, and extinguishing inflammation.
 “Mrs. S. was carefully lifted from her bed, and after being placed in
her chair, was transferred to a hip-bath, containing about one pail of
water fresh from the Croton hydrant near by, of the temperature of
42° Fah. A towel, wrung out of cold water, was applied to the
forehead at the same time. Of course she was well covered with
blankets. She had been seated there but a few minutes, when she
expressed herself as feeling very comfortable indeed. The severe
pain in her abdomen and thigh had left her as if by magic, and so
complete was the relief, that she fell into a gentle doze, from which,
awakened by nodding, she observed, ‘There, I feel so easy now, I lost
myself, I believe.’
“While in the bath, her pulse was lowered several beats in the
minute; the unimmersed parts of the body remained warm; the hips
were to her of a refreshing coolness. After remaining thus seated in
the water about twenty-five minutes—a slight addition of more cold
water, by gradual pouring, having been made during this time—she
was lifted back to the bed. Her pain had now entirely vanished; the
natural lochial discharge was soon restored; the pulse reduced to 94;
and, warm and comfortable, she had a prospect of a good night’s
rest.
“Third Day (Saturday), Seven A. M.—Found patient looking
comfortable and happy. No pain now in the abdomen, slight soreness
only; tympanitis (swelling) gone; tongue moist, and hardly coated;
pulse 79; had had no sensation of chilliness after her bath, but slept
from 12½ to 4 A. M., without waking, and another doze after that;
window had been a little raised all night, and no fire in the room,
though it was cool. Now was able to pass water without difficulty.
Was directed to take for breakfast some coarse wheaten bread,
toasted, and softened with milk, and a little scraped apple, if she
wished.
“Eleven, A. M.—Mrs. S. appears very comfortable. With the aid of a
friend has been up and changed her clothing. Pulse 84; complains of
no pain of any consequence in the abdomen.
“Half-past One, P. M.—Had been under the necessity of getting up
without assistance, and fatigued herself, and thus induced a return of
very severe pain in the uterine region. Dr. S. was sent for, when
resort was had again to the hip-bath, filled with cold water from the
hydrant, which had with such wonderful promptitude averted the
danger of puerperal fever, with which she was threatened on the
evening of the second day; as on that occasion, in less than five
minutes, the pain and feverishness was completely quelled. She was
allowed to remain in the bath half an hour, and requested to abstain
from food till evening.
“Five, P. M.—Patient doing remarkably well; cheerful; free from
pains in the abdomen, save now and then a very slight one; some
soreness on pressure; pulse 84, compressible.
“Ten, P. M.—Had slept during evening; had taken a little
nourishment. Has some difficulty in passing water, and as occasional
slight pains and soreness still continues in the abdomen, the cold
hip-bath, at 42° Fah., was again resorted to for about thirty minutes.
During this time the pulse was lowered from 80 beats in a minute to
70; water was passed freely, and pains put to flight.
“After the bath, the patient continuing warm and comfortable, was
directed, should there be any return of pains during the night, to seat
herself in the hip-bath, which was left in the room.
“Fourth Day (Sunday), Half-past Seven, A. M.—Patient had slept
most of the night; looks bright; feels ‘very comfortable;’ pulse 72, soft
and natural; had raised herself in bed without difficulty, and washed.
On account of some difficulty in passing water, the hip-bath was
used for about fifteen minutes, when the urine flowed more
copiously and freely than at any previous time. Left seated in the
rocking-chair; sitting up occasionally; she says it has rested and
refreshed her from the first.
“Appetite good; thinks even the plainest food would be relished.
Breakfast to be as before; the toasted coarse bread, soaked in milk,
with a little scraped apple. Directed to take no nourishment at any
time, unless a decided appetite, nor then oftener than three times in
a day. Is to take an enema and another hip-bath in the course of the
morning.
“Six, P. M.—Had continued to gain during the day till toward
evening. It most unfortunately happened that an intoxicated man,
mistaking the house, strayed into the room where she was lying, with
no attendant but a young girl; seating himself, without any
ceremony, in the rocking-chair, with a lighted cigar in his mouth, he
smoked away to his satisfaction, and then very deliberately
composed himself for a nap. This strange visitor, and the fumes of
the tobacco, had given poor Mrs. S. a severe headache, the first with
which she had been troubled; considerable nausea, with paleness of
the face, cold feet, etc. A towel wet with cold water was applied to the
head, and a hip-bath ordered.
“Half-past Nine, P. M.—Was rapidly recovering from the effects of
the afternoon’s unexpected visit; sat up awhile.
“Fifth Day (Monday).—At 7½ A. M., found Mrs. S. sitting up in bed
sewing; pulse 75; had rested well; has a good appetite. Breakfast to
be as before; may safely take a hip-bath at any time when suffering
from pains and is not made very chilly by sitting in it.
“Was able this morning to rise and walk about the room
unsupported. Required no assistance in getting to the bath; bowels
moved naturally; sat up several hours to-day; appears bright,
pleasant, and cheerful.
“Sixth Day (Tuesday).—Mrs. S. feels to-day as much better than
she did yesterday, as she did yesterday better than the day before. Sat
up, and was about the room nearly all day; continues the practice of
daily sponging the whole surface, and the use of the hip-bath. At
night, retention having ensued from over-distention of the bladder,
in consequence of an untimely and protracted visit from some of
patient’s friends, Dr. S. was sent for, and deemed it advisable to
resort to the catheter, which she had frequently been compelled to
use on former occasions, sometimes for months together.
“Seventh Day (Wednesday).—Mrs. S. appeared to be better in the
morning; able to rise without assistance, to walk about, and even to
sweep the room; catheter again required.
“Eighth Day (Thursday).—During the night, of her own accord,
took two or three or four cool hip-baths, and found them refreshing,
and of service in promoting easy evacuation of the bladder. At one
time dropped asleep, and remained so an hour or more—sitting in
the water. Pulse in the morning. Dressed the children and arranged
the room herself to-day; and though a week had hardly elapsed since
her confinement, felt strong enough in the morning to go down
stairs, and to do a half day’s work in sewing, etc., from which she
appeared to experience no injury. A few days after she ventured to
ride down to the lower part of the city, and having since continued to
improve, save an occasional return of an old difficulty—retention—is
most gratefully sensible, under Heaven, to her physician and
hydropathy, for a far more speedy and pleasant convalescence than
she ever experienced after any of her former confinements.”
Professor Gilman, of this city (New York), in his edition of the
Dublin Practice of Midwifery, gives us the following account of a
method of treatment which was adopted with remarkable success in
the old country:
“In an epidemic (puerperal fever), which raged at Keil in 1834, ’35,
and ’36,” says Professor G., “Michælis used ice, both externally and
internally, with excellent effect. The cases in which he gave it with
success were marked by burning pain and heat in the bowels, thirst,
painful eructations, and tenderness of the epigastrium. The brain
was clear; no delirium. The ice was given by the mouth, in bits the
size of the finger, every half hour or oftener; it was also applied over
the abdomen in a large bullock’s bladder, extending from the
epigastrium to the pelvis, in a layer half an inch thick. This
application was in some cases continued for three days, the bladder
being changed as soon as the ice melted. It was very grateful to the
patient, and Michælis thought it had cured some cases where
affusion had actually taken place into the peritoneal cavity. The use
of ice was not persisted in unless it was grateful to the patient. The
symptoms of amendment were a sudden and very great fall in the
frequency of the pulse, a peaceful sleep, relief from the painful
eructations, and diminished distention of the bowels. A profuse
watery diarrhea occurring with these favorable changes, seemed to
him to be critical.”
This treatment of Michælis is certainly a very bold one. Those who
are well acquainted with the water-treatment will be able at once to
comprehend the fact, that the applications mentioned were sufficient
to cause “a sudden and very great fall in the frequency of the pulse, a
peaceful sleep, relief from the painful eructations, and diminished
distention of the bowels.” Nor is it incredible that a cure might thus
take place, even in some cases where affusion into the peritoneal
cavity had actually taken place, since the effort of nature tends
always, so long as life lasts, necessarily to that end. It is well worthy
of remark, that the treatment of Michælis was persisted in only so
long as it was grateful to the patient. This is an important rule to
remember.
Nor do I regard it necessary, absolutely, to use ice in the treatment
of this or any other inflammatory affection. Water—even at the
temperature of rivers at this latitude in the summer—which is
usually, I believe, at about 70° Fah., may be made very effectual in
the cure of inflammatory diseases. Thus, if we wrap one or more wet
sheets about a patient, having him, at the same time, on a cool straw
bed, and neither the bed or wet sheets having any covering whatever,
we, through the natural processes of evaporation and refrigeration,
abstract in a short time a great amount of animal heat. We may
likewise change these applications as often as we desire, or pour
water upon the sheets frequently, and thus cool the patient to any
desirable extent, without the use of ice or water that is extremely
cold. It should be understood, also, that general applications—
applications over the whole or a large part of the body’s surface—are
far more effectual in reducing the inflammation of a local part, than
applications locally made can be. This fact is not generally
understood.
Is Childbed Fever a Contagion?—This disease is believed by many
to be at times contagious. It would, doubtless, be a difficult
undertaking to prove positively that such is the fact. It is the opinion
of some able writers on medicine, “that there is unquestionably an
epidemic influence, or atmospheric constitution, which sometimes,
in extensive districts of country, in villages, in towns, and cities, and
especially in crowded lying-in hospitals, determines, by an unknown
force, the attack of childbed fever, and so modifies the
pathognomonic conditions as to hurry numerous victims to the
grave, and this, notwithstanding the most reasonable methods of
cure.”
But that the disease is really communicable from one patient to
another, is not so palpable. One author—Professor Meigs—a man
whose good character and long experience entitle his opinions to
much weight, tells us that a great experience—and few have enjoyed
greater—has not enabled him to perceive that he has been the means
of disseminating this malady among lying-in women, to whom he
had given professional aid while attending upon dangerous and fatal
attacks of it, or after making or witnessing autopsic examinations of
the bodies of the dead. On the other hand, Dr. Gooch, an author
whose opinions are probably equally deserving of respect, tells us in
reference to puerperal fever, that it is not uncommon for the greater
number of cases to occur in the practice of one man, while the
practitioners of the neighborhood, who are not more skillful or busy,
meet with few or none. A practitioner opened the body of a woman
who had died of puerperal fever, and continued to wear the same
clothes. A lady whom he delivered a few days afterward was attacked
with, and died of a similar disease; two more of his lying-in patients,
in rapid succession, met with the same fate. Struck by the thought
that he might have carried the contagion in his clothes, he instantly
changed them, and met with no more cases of the kind.
A woman in the country, who was employed as washerwoman and
nurse, washed the linen of one who had died of puerperal fever; the
next lying-in patient she nursed died of the same disease; a third
nursed by her met with the same fate, till the neighborhood, getting
afraid of her, ceased to employ her. The disease has been known,
according to Dr. Gooch, to occur in some wards of a hospital, while
the others were at the same time free from it. Dr. Blundell, who is
certainly very high authority, while he admits that this fever may
occur spontaneously, and that its infectious nature may be plausibly
disputed, affirms, that in his own family he had rather that those he
esteemed the most should be delivered, unaided, in a stable—by the
manger side—than that they should receive the best help in the
fairest apartment, but exposed to the vapors of this pitiless disease.
Gossiping friends, wet-nurses, monthly nurses, the practitioner
himself—these are the channels by which, in Dr. Blundell’s
estimation, the infection is principally conveyed.
Some authors contend, also, that it is only through the influence of
the imagination, or by sympathy, that puerperal fever becomes more
prevalent by times than ordinarily; and there can be but little doubt
that these causes operate to a greater or less extent in
communicating the malady. If a weak and nervous patient fears it,
and especially if it is prevailing epidemically in the neighborhood in
which she resides, she is much more liable to an attack than if she
had no thoughts whatever of the disease. It is, moreover, under such
circumstances more likely to prove fatal than when it occurs
sporadically.
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