1. What does ASIC stand for? 5.

What type of ASIC involves no customization

of mask layers?
• A) Advanced Standard Integrated Chip
• A) Full-Custom ASIC
• B) Application-Specific Integrated Circuit
• B) Standard-Cell ASIC
• C) Automated System Integrated Chip
• C) Programmable ASIC
• D) Analog-Specific Integrated Circuit
Correct Answer: B • D) Gate-Array Based ASIC
Correct Answer: C
2. Which of the following technologies
dominated ICs in the early 1970s? 6. What is the key difference between an MGA
and CBIC?
• A) CMOS
• A) Gate arrays have customizable
• B) TTL
transistors
• C) NMOS • B) Gate arrays have fixed transistors
• D) ECL • C) Gate arrays require no interconnects
Correct Answer: B
• D) CBIC does not use fixed blocks
3. What is the primary advantage of CMOS
Correct Answer: B
technology?
7. Which is an example of a full-custom IC?
• A) High power consumption
• A) Memory chip
• B) Low power consumption
• B) Standard cell IC
• C) Easier fabrication of NMOS
• C) Microprocessor
• D) Higher voltage tolerance
Correct Answer: B • D) PLA
Correct Answer: C
4. Which IC uses predesigned logic cells?
8. What is the main advantage of standard-cell
• A) Full-Custom IC based ASICs?
• B) Standard-Cell Based ASIC • A) Low cost per unit
• C) PLA • B) Faster design time using predesigned
• D) FPGA cells
Correct Answer: B • C) Greater area efficiency
 • D) Fixed manufacturing process 13. What does PGA stand for in IC packaging?
Correct Answer: B
• A) Pin-Grid Array
9. Which of the following is a type of
• B) Programmable Gate Array
programmable ASIC?
• C) Printed Gate Array
• A) FPGA
• D) Power Grid Array
• B) ROM
Correct Answer: A
• C) SRAM
14. What is the advantage of gate-array based
• D) PLA ASICs?
Correct Answer: A
• A) Faster production turnaround
10. How many mask layers are typically
• B) High customization
customized in a full-custom IC?
• C) Improved power handling
• A) Only top layers
• D) Custom transistor layouts
• B) All mask layers
Correct Answer: A
• C) Gate mask layers only
15. What technology replaced aluminum gates
• D) None in the early 1980s?
Correct Answer: B
• A) Gold gates
11. What does NMOS stand for?
• B) Copper gates
• A) Negative MOS
• C) Polysilicon gates
• B) n-channel MOS
• D) Silicon gates
• C) Normal MOS Correct Answer: C

• D) Non-metallic Oxide Semiconductor 16. Which of the following is NOT an example

Correct Answer: B of an ASIC?

12. What innovation allowed for both p- • A) Microprocessor

channel and n-channel transistors on one IC?
• B) Toy chip
• A) Bipolar technology
• C) Modem controller chip
• B) TTL
• D) Custom memory controller
• C) CMOS Correct Answer: A

• D) Polysilicon gates 17. What type of ASIC provides the fastest

Correct Answer: C design turnaround?
 • A) Gate-array based ASIC • B) Ground

• B) Full-custom ASIC • C) Positive power supply

• C) Programmable ASIC • D) Logic gate voltage

Correct Answer: C
• D) Standard-cell ASIC
Correct Answer: C 22. Which standard cell component is used for
power distribution?
18. What term describes unused transistors in
a channelless gate array? • A) Spacer cells

• A) Base cells • B) Feedthrough cells

• B) Dummy cells • C) Row-end cells

• C) Unused feedthroughs • D) Bus cells

Correct Answer: C
• D) Redundant cells
Correct Answer: A 23. What feature does a CBIC provide
compared to an MGA?
19. What does SOG stand for in gate arrays?
• A) Reduced lead time
• A) Sea of Gates
• B) Adjustable interconnect height
• B) Structured Open Grid
• C) Fixed transistors
• C) Signal Over Grid
• D) Higher cost
• D) Silicon Overlay Grid
Correct Answer: B
Correct Answer: A
24. Which IC allows on-field reprogramming?
20. What is a key feature of structured gate
arrays? • A) ROM

• A) No predefined areas • B) PLA

• B) Fixed transistor sizes • C) FPGA

• C) Embedded custom blocks • D) SRAM

Correct Answer: C
• D) Single-use masks
Correct Answer: C 25. What determines interconnect delay in
ASICs?
21. What does VDD represent in CMOS
technology? • A) Logic cell size

• A) Negative power supply • B) Parasitic capacitance

 • C) Mask layer thickness • D) Lower power consumption
Correct Answer: D
• D) Transistor count
Correct Answer: B 30. What is the key disadvantage of a full-
custom ASIC?
26. What is the primary function of a full-
custom IC design? • A) Limited design flexibility

• A) Predefined cell usage • B) Long design and manufacturing time

• B) Completely custom logic and layout • C) High volume production cost

• C) Reduced cost over time • D) Fixed transistor sizes

Correct Answer: B
• D) Simplified mask design
Correct Answer: B 31. What does COT stand for in ASIC
development?
27. Which ASIC design type uses predesigned
logic cells? • A) Component Owned Tooling

• A) Full-Custom ASIC • B) Customer Owned Tooling

• B) Standard-Cell ASIC • C) Custom Open Technology

• C) Channeled Gate Array • D) Controlled Open Timing

Correct Answer: B
• D) Programmable ASIC
Correct Answer: B 32. What layer in a CBIC is typically used for
power buses?
28. Which term refers to unused logic cells in
gate-array designs? • A) Metal1

• A) Dead cells • B) Metal2

• B) Feedthrough cells • C) Polysilicon

• C) Base cells • D) Diffusion layer

Correct Answer: A
• D) Spare cells
Correct Answer: C 33. What do we call a logic library provided by
an ASIC vendor?
29. Which advantage does CMOS have over
bipolar technology? • A) Fixed Library

• A) Better noise immunity • B) Qualified Library

• B) Higher power consumption • C) Phantom Library

• C) Higher voltage tolerance

 • D) Compiler Library 38. What is a critical feature of channeled gate
Correct Answer: C arrays?

34. What distinguishes a CBIC from an FPGA? • A) Flexible interconnect regions

• A) Predefined interconnect • B) Fixed spaces for routing

• B) Fully customizable interconnect • C) Absence of predefined routing

channels
• C) Fixed logic cells
• D) Higher routing density
• D) Programmable logic layers Correct Answer: B
Correct Answer: B
39. What limits the logic density of channeled
35. Which of the following is an advantage of gate arrays?
gate arrays?
• A) Fixed transistor size
• A) Reduced power consumption
• B) Fixed routing areas
• B) Faster design turnaround
• C) Inflexible base cells
• C) High custom transistor design
• D) Lack of programmable regions
• D) Reduced fabrication cost Correct Answer: B
Correct Answer: B
40. What type of mask is used in channelless
36. Which IC type allows no mask gate arrays for interconnections?
customization at all?
• A) Polysilicon mask
• A) Standard-Cell ASIC
• B) Contact mask
• B) Gate-Array Based ASIC
• C) Logic mask
• C) Programmable ASIC
• D) Transistor mask
• D) Full-Custom ASIC Correct Answer: B
Correct Answer: C
41. What does SOG stand for in channelless
37. What defines the interconnection pattern gate arrays?
of an FPGA?
• A) Signal-On-Gate
• A) Contact mask layers
• B) Silicon-On-Gate
• B) Programmable interconnect matrix
• C) Sea-of-Gates
• C) Fixed routing channels
• D) Standard-Open-Gate
• D) Custom transistor sizes Correct Answer: C
Correct Answer: B
42. What is the key feature of structured gate 46. Which technology is primarily used for logic
arrays? cell libraries today?

• A) Custom blocks are embedded • A) TTL

• B) Fixed transistor patterns • B) CMOS

• C) Programmable gate logic • C) BiCMOS

• D) Lower logic density • D) Bipolar

Correct Answer: A Correct Answer: B

43. What factor allows faster turnaround in 47. What does a standard-cell based ASIC use
gate-array based ASICs? to simplify design?

• A) Prefabricated wafers • A) Fully customizable transistors

• B) Reduced logic density • B) Predesigned and optimized logic cells

• C) Fixed custom blocks • C) Flexible routing masks

• D) Programmable logic • D) Programmable logic regions

Correct Answer: A Correct Answer: B

44. What is the purpose of a wire-load model 48. Which step in ASIC design involves
in ASIC design? determining the resistance and capacitance of
the interconnect?
• A) Define physical layout constraints
• A) Extraction
• B) Estimate interconnect capacitance
• B) Floorplanning
• C) Optimize transistor sizes
• C) Placement
• D) Manage signal power distribution
Correct Answer: B • D) Routing
Correct Answer: A
45. What does a phantom library contain in
ASIC design? 49. What aspect of CMOS technology makes it
ideal for analog and digital integration?
• A) Predefined physical layouts
• A) Reduced power consumption
• B) Empty boxes with layout info
• B) Higher voltage handling
• C) Complete routing models
• C) Simpler oxide interface
• D) Optimized gate delays
Correct Answer: B
 • D) Increased transistor matching on- o B. Floorplan
chip
o C. Behavioral description
Correct Answer: D
o D. Circuit schematic
50. Which tool generates memory blocks in a
standard-cell design? Answer: B. Floorplan

• A) Logic synthesizer 4. Floorplanning allows the estimation of

which critical design parameter?
• B) Datapath compiler
o A. Transistor size
• C) Memory compiler
o B. Power dissipation
• D) Wire-load analyzer
o C. Interconnect delay
Correct Answer: c
o D. Number of gates
1. What is the input to the floorplanning step
Answer: C. Interconnect delay
in ASIC design?

o A. Gate-level netlist 5. Which factor is NOT a goal of

floorplanning?
o B. Behavioral description
o A. Minimize chip area
o C. RTL design
o B. Minimize delay
o D. Physical layout
o C. Maximize wire lengths
Answer: A. Gate-level netlist
o D. Define clock distribution
2. What is the primary purpose of
floorplanning in VLSI design? Answer: C. Maximize wire
lengths
o A. To complete the routing of
signals 6. What type of floorplan is used when
the chip can be divided into blocks by
o B. To define the logical making straight cuts?
operations
o A. Cyclic floorplan
o C. To arrange blocks physically
o B. Non-slicing floorplan
on the chip
o C. Slicing floorplan
o D. To fabricate the design
Answer: C. To arrange blocks o D. Grid-based floorplan
physically on the chip Answer: C. Slicing floorplan
3. Which of the following represents the 7. In floorplanning, what does a wire-load
physical description of an ASIC? table predict?
o A. Logical netlist
 o A. Transistor gate delay o D. Overheated parts of the chip
Answer: B. Regions with high
o B. Average interconnect channel density
capacitance
11. Which method helps to remove cyclic
o C. Chip power consumption constraints in floorplanning?
o D. Logic cell density o A. Increasing channel width
Answer: B. Average
interconnect capacitance o B. Merging flexible blocks

8. What is the function of seed cells in o C. Using multi-layer routing

flexible blocks?
o D. Clock distribution
o A. To fix the location of certain optimization
logic cells Answer: B. Merging flexible
blocks
o B. To calculate clock skew
12. What type of pads are used for tall,
o C. To maximize channel capacity thin dies to maximize pad count?
o D. To define power rails o A. Core-limited pads
Answer: A. To fix the location of
certain logic cells o B. Pad-limited pads

9. Which distribution dominates delay as o C. Hybrid pads

feature sizes shrink?
o D. Staggered pads
o A. Interconnect delay Answer: B. Pad-limited pads

o B. Gate delay 13. What is the main objective of

placement in ASIC design?
o C. Logic delay
o A. Minimize channel density
o D. Clock delay
Answer: A. Interconnect delay o B. Optimize logic synthesis

10. What does a congestion map indicate o C. Arrange logic cells within
in floorplanning? blocks

o A. Areas with excessive logic o D. Determine pad locations

gates Answer: C. Arrange logic cells
within blocks
o B. Regions with high channel
density 14. What is the term for the smallest
rectangle enclosing all terminals of a
o C. Unused sections of the die net?
 o A. Routing tree 18. Which measure is used to approximate
Manhattan routing distances?
o B. Channel map
o A. Steiner-tree measure
o C. Bounding box
o B. Complete-graph measure
o D. Congestion zone
Answer: C. Bounding box o C. Half-perimeter measure

15. What algorithm is commonly used in o D. Net density measure

constructive placement? Answer: C. Half-perimeter
measure
o A. Kernighan-Lin algorithm
19. Which placement method involves
o B. Min-cut algorithm swapping logic cells iteratively?
o C. Force-directed placement o A. Constructive placement
o D. Zero-slack algorithm
o B. Iterative placement
Answer: B. Min-cut algorithm improvement
16. Which method estimates delay for o C. Global routing
every net in timing-driven placement?
o D. Congestion-driven placement
o A. Steiner-tree approximation Answer: B. Iterative placement
o B. Half-perimeter measure improvement

o C. Zero-slack algorithm 20. What is the purpose of global routing?

o D. Force-directed method o A. Assign nets to specific layers

Answer: C. Zero-slack algorithm o B. Provide routing paths for the
17. What is a key issue in force-directed detailed router
placement without external forces?
o C. Minimize transistor size
o A. Excessive power dissipation o D. Optimize clock distribution
o B. Over-constrained placement Answer: B. Provide routing
paths for the detailed router
o C. Collapse of logic cells to a
single point 21. Which approach is used to handle large
nets during global routing?
o D. Incomplete routing paths
Answer: C. Collapse of logic o A. Top-down
cells to a single point
o B. Hierarchical

o C. Iterative improvement
 o D. Sequential 25. What does a "cut line" in placement
Answer: B. Hierarchical measure?

22. What does back-annotation involve? o A. Routing distance

o A. Predicting clock skew o B. Congestion

o B. Feeding delay estimates back o C. Chip density

to synthesis tools
o D. Number of layers
o C. Creating a netlist for routing Answer: B. Congestion

o D. Adjusting power distribution 26. What is the key advantage of a clock

networks tree over a clock spine?
Answer: B. Feeding delay
o A. Reduced power dissipation
estimates back to synthesis
tools o B. Better load balancing
23. Which type of interconnect structure o C. Lower clock latency
allows over-the-cell routing (OTC)?
o D. All of the above
o A. Horizontal channels only Answer: D. All of the above
o B. Vertical channels only 27. Which algorithm type often initializes a
o C. Channels without metal placement solution?
obstructions o A. Constructive placement
o D. Both horizontal and vertical o B. Iterative improvement
channels
Answer: C. Channels without o C. Simulated annealing
metal obstructions
o D. Path-based placement
24. What is the function of spacer cells in Answer: A. Constructive
placement? placement

o A. Improve signal strength 28. In the context of ASIC placement,

"fanout" refers to:
o B. Fill space for power bus
alignment o A. Number of gates a net
connects to
o C. Reduce chip area
o B. Routing complexity
o D. Separate clock domains
Answer: B. Fill space for power o C. Interconnect length
bus alignment
 o D. Gate size 32. Which metric is used to determine
Answer: A. Number of gates a maximum cut lines in congestion
net connects to analysis?

29. Why are "timing-driven" placement o A. Channel density

methods critical in modern designs?
o B. Fanout number
o A. To optimize area utilization
o C. Interconnect crossings
o B. To meet strict delay
o D. Power consumption
requirements
Answer: C. Interconnect
o C. To reduce clock skew crossings

o D. To simplify routing 33. How does a hierarchical global routing

Answer: B. To meet strict delay strategy simplify routing problems?
requirements
o A. By reducing channel
30. What is a potential downside of using congestion
the zero-slack algorithm in placement?
o B. By breaking routing into
o A. Over-constrained net delays smaller levels

o B. High computational cost o C. By prioritizing critical paths

o C. Increased chip area o D. By increasing wire-load

estimates
o D. Unoptimized paths Answer: B. By breaking routing
Answer: A. Over-constrained into smaller levels
net delays
34. What is the role of "order-dependent"
31. What is the purpose of "steiner-tree" algorithms in global routing?
approximations in placement?
o A. Ensure uniform channel
o A. To minimize congestion utilization
o B. To predict shortest o B. Prevent cyclic constraints
interconnect length
o C. Adjust routing based on
o C. To define critical paths sequence
o D. To optimize transistor sizes o D. Reduce clock skew
Answer: B. To predict shortest
Answer: C. Adjust routing based
interconnect length on sequence

35. What does a "pad ring" ensure in chip

design?
 o A. Power distribution 39. What is a common challenge in
iterative placement improvement?
o B. Signal I/O connections
o A. Determining initial
o C. Both A and B placement
o D. Only signal connections o B. Avoiding local optima
Answer: C. Both A and B
o C. Reducing channel density
36. Which interconnect layer typically runs
parallel to the longest side of a o D. Optimizing transistor size
channel? Answer: B. Avoiding local
optima
o A. m1
40. What is the primary purpose of "pad-
o B. m2 limited" dies?
o C. m3
o A. Maximize logic density
o D. Any available layer o B. Allow for more I/O pads
Answer: A. m1
o C. Minimize routing delays
37. What is a "meander factor" in routing?
o D. Reduce power consumption
o A. Ratio of actual to estimated Answer: B. Allow for more I/O
interconnect length pads
o B. Measure of delay

o C. Measure of congestion

o D. Ratio of metal usage to

power dissipation
Answer: A. Ratio of actual to
estimated interconnect length

38. What is "clock skew" primarily caused

by?

o A. Uneven routing lengths

o B. Buffer mismatches

o C. Variable loads

o D. All of the above

Answer: D. All of the above