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87 views2 pages

Table of Contents

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Manas Sethi
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6

GUEST EDITOR’S INTRODUCTION


Special Issue on Contemporary
Industry Products 2024
John B. Carter

NOVEMBER/DECEMBER 2024

8 17
Theme Articles

Synchronous, Low-Latency, A Latency Processing Unit:


Off-Module Interface A Latency-Optimized and Highly
for the IBM z16 Scalable Processor for Large
Telum Processor Language Model Inference
Patrick Meaney, Ashutosh Mishra, Seungjae Moon, Jung-Hoon Kim, Junsoo Kim,
and Rajat Rao Seongmin Hong, Junseo Cha, Minsu Kim,
Sukbin Lim, Gyubin Choi, Dongjin Seo, Jongho Kim,
Hunjong Lee, Hyunjun Park, Ryeowook Ko,
Soongyu Choi, Jongse Park, Jinwon Lee,
and Joo-Young Kim
Theme Articles Continued
34 Composition of Experts on the SN40L Reconfigurable Dataflow Unit
Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang,
Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Joshua Brot,
Calvin Leung, Tuowen Zhao, Mark Gottscho, Zhengyu Chen, Kaizhao Liang,
Swayambhoo Jain, Urmish Thakker, Kevin J. Brown, and Kunle Olukotun

44 Parallelization Strategies for DLRM Embedding Bag


Operator on AMD CPUs
Krishnakumar Nair, Avinash-Chandra Pandey, Siddappa Karabannavar,
Meena Arunachalam, John Kalamatianos, Varun Agrawal, Saurabh Gupta, Ashish Sirasao,
Elliott Delaye, Steve Reinhardt, Rajesh Vivekanandham, Ralph Wittig, Vinod Kathail,
Padmini Gopalakrishnan, Satyaprakash Pareek, Rishabh Jain, Mahmut Taylan Kandemir,
Jun-Liang Lin, Gulsum Gudukbay Akbulut, and Chita R. Das

52 Monza: An Energy-Minimal, General-Purpose Dataflow


System-on-Chip for the Internet of Things
Nathan Beckmann, Brandon Lucia, Graham Gobieski, Tony Nowatzki, Thomas Jackson,
Guénolé Lallement, Keyi Zhang, Amolak Nagi, Atharv Sathe, and Harsh Desai

63 DNNDaSher: A Compiler Framework for Dataflow Compatible


End-to-End Acceleration on IBM AIU
Sanchari Sen, Shubham Jain, Sarada Krithivasan, Swagath Venkataramani,
and Vijayalakshmi Srinivasan

73 AMD XDNA NPU in Ryzen AI Processors


Alejandro Rico, Satyaprakash Pareek, Javier Cabezas, David Clarke, Baris Ozgul,
Francisco Barat, Yao Fu, Stephan Münz, Dylan Stuart, Patrick Schlangen,
Pedro Duarte, Sneha Date, Indrani Paul, Jian Weng, Sonal Santan, Vinod Kathail,
Ashish Sirasao, and Juanjo Noguera

83 Puss in Boots: Formalizing Arm’s Virtual Memory System Architecture


Jade Alglave, Richard Grisenthwaite, Artem Khyzha, Luc Maranget, and Nikos Nikoleris

Columns and Departments


From the Editor-in-Chief
4 Strategic Pivot of Long-Standing x86 Rivals
Hsien-Hsin S. Lee
Micro Law
92 A Review of Wisconsin Alumni Research Foundation v. Apple—Part I
Joshua J. Yi
In Memoriam
98 Mauricio Breternitz Jr.
Lizy Kurian John
Cover image credit:
Ingram Publishing Micro Economics
100 Unpriced and Crucial
Shane Greenstein

Also in This Issue


1 Masthead
97 IEEE Computer Society Information

www.computer.org/micro

ISSN: 0272-1732

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