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VHDL

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Venkatramana Reddy K
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21 views5 pages

VHDL

Uploaded by

Venkatramana Reddy K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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1.

Dataflow modeling:
AND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;

architecture and2_data of and2 is


begin
z<=x and y;
end and2_ data;
OR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;

architecture or2_data of or2 is


begin
z<=x or y;
end or2_ data;
NAND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;

architecture nand2_ data of nand2 is


begin
z<=x nand y;
end nand2_ data;
NOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;
architecture nor2_ data of nor2 is
begin
z<=x nor y;
end nor2_ data;
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;

architecture xor2_ data of xor2 is


begin
z<=x xor y;
end xor2_ data;
XNOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;

architecture xnor2_ data of xnor2 is


begin
z<=x xor y;
end xnor2_ data;
NOT GATE:
library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;

architecture not1_ data of not1 is


begin
z<=not x;
end not1_ data;
2. Behavioral modeling:
AND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity and2 is
port (x,y: in std_logic;
z: out std_logic);
end and2;

architecture and2_behave of and2 is


begin
process(x,y)
begin
z<=x and y;
end process;
end and2_behave;
OR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity or2 is
port(x,y: in std_logic;
z: out std_logic);
end or2;

architecture or2_behave of or2 is


begin
process(x,y)
begin
z<=x or y;
end process;
end or2_behave;
NAND GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
port (x,y: in std_logic;
z: out std_logic);
end nand2;

architecture nand2_behave of nand2 is


begin
process(x,y)
begin
z<=x nand y;
end process;
end nand2_behave;
NOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity nor2 is
port(x,y: in std_logic;
z: out std_logic);
end nor2;

architecture nor2_behave of nor2 is


begin
process(x,y)
begin
z<=x nor y;
end process;
end nor2_behave;
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xor2 is
port(x,y: in std_logic;
z: out std_logic);
end xor2;

architecture xor2_behave of xor2 is


begin
process(x,y)
begin
z<=x xor y;
end process;
end xor2_behave;
XNOR GATE:
library ieee;
use ieee.std_logic_1164.all;

entity xnor2 is
port(x,y: in std_logic;
z: out std_logic);
end xnor2;

architecture xnor2_behave of xnor2 is


begin
process(x,y)
begin
z<=x xor y;
end process;
end xnor2_behave;
NOT GATE:
library ieee;
use ieee.std_logic_1164.all;

entity not1 is
port(x:in std_logic;
z:out std_logic);
end not1;

architecture not1_behave of not1 is


begin
Process(x)
begin
z<=not x;
end process;
end not1_behave;

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