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Lab11 - Data Path Main Components Design-II

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10 views

Lab11 - Data Path Main Components Design-II

Uploaded by

aljm68019
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab 10: Data Path Main Components Design-II

Objective(s)

After completing this lab, you will:


 Design a 32x 32 bit register file

Tool(s)/Software

 LOGISIM

Description

Register File

The register file consists of 32 x 32-bit registers and has the following interface as shown in
Figure 10.1:
 BusA and BusB: 32-bit output busses for reading 2 registers
 BusW: 32-bit input bus for writing a register when RegWrite is 1
 RA selects register to be read on BusA
 RB selects register to be read on BusB
 RW selects the register to be written

Thus, two registers are read, and one register is written in a single cycle. Writing happens on the
rising edge of the clock. During read operation, the register file behaves as a combinational block
and once the RA or RB have valid data, the content of the read register will appear on BusA or
BusB after a certain access time.

Figure 10.1: 32x32-bit register file interface


The 32 x 32-bit register file design is given in Figure 10.2. It should be observed that register 0 is
a constant. Each of BusA and BusB is connected to 32 tri-state buffers. Each tr-state buffer is
connected to one of the 32 registers. The tri-state buffers enable signals are driven by the outputs
of two 5x32 decoders, one with Ra input and the other with Rb input, to select which register
puts its value on the corresponding bus. The enable signals of the 31 registers (register 1 to 31)
are anded with the output of a 5x32 decoder and RegWrite signal. The 5x32 decoder input is
connected to Rw to select which register should be written.

Figure 10.2: 32x32-bit register file design

In-Lab Tasks

You are required to design a 32-bit MIPS-like processor with 31 general-purpose registers. The
first building blocks of the CPU are the ALU and the register file.

Task 1:
 Model the 32x32-bit register file given in Figure 10.2 as one single module in Logisim
 Test the register file for correct operation by writing to and reading from different register
combinations.

Deliverables(s)
 LOGISIM model file for question described in previous section.

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