Birla Institute of Technology and Science (BITS) Pilani, K K Birla Goa Campus

Sem-I, AY-2023-24
Course Handout (Part II)
Dated: August 7, 2024
In addition to Part I (General Handout for all courses appended to the timetable) this portion gives further specific details
regarding the course.

Course No.: CS F342

Course Title: Computer Architecture
Instructor-in-charge: Dr Kanchan Manna
Instructors: Dr Kunal Korgaonkar

Course Description:

The course introduces general-purpose processor’s (or computers’) architecture and organization based on J. von Neumann’s
proposed model: stored-program computer. The program consists of a set of instructions. Instructions perform the arithmetic
and logical operations, synthesized using digital arithmetic and logic circuits. This course presents a study on the methodologies
to design, execute and predict the instructions efficiently; that is, a study on methods to run the program efficiently. It discusses
not only the methods for storing, retrieving, and prefetching the instructions and the data efficiently but also how memory can
be designed and how it can be used. In addition, it can provide pointers to recent research and developments on the topic.

Course Objective: The students will be able to:

 Understand automatic computation and its computational support units.

 Design the microprocessors [single-purpose & general-purpose], the branch predictors, the storage unit and the pre-
fetcher.
 Recognize the necessity and changes to improve the performance of automatic computation.
 Understand the different types of parallelization techniques to improve performance.
 Comprehend the different type of memory supports and their optimization technique to improve the performance.
 Design a computational and storage unit.
 Use effectively measure the performance.
 Get the pointers to the latest advancement in the field of computer architecture.
Textbooks:

(T1) Computer Organization and Design: The Hardware Software Interface MIPS Edition by David
A. Patterson and John L. Hennessy.
(T2) Computer Architecture: A quantitative Approach by David A. Patterson and John L.
Hennessy.

Reference Books:

(R1) Digital Design with an Introduction to the Verilog HDL by M. Morris Mano & Michael D. Ciletti
(R2) Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar.
(R3) Computer Organisation & Architecture: Designing for performance by William Stallings.
Lecture Modules:

Module No Module Learning Objectives

 Automated computation and models
Motivation and introduction
of computation
 Single-purpose processor
 Components of the data path and its
design techniques
 Design of the components in
control-path
 Importance of interconnection
 Single-cycle, Multi-cycle, and
M1 Pipelined techniques
Processor Design Methodologies  General-purpose processor
 von Neumann computational model
 Analysis of performance and
complexity on instruction set
architecture (ISA)
 Importance of interconnection
 Controls generation techniques
 Single-cycle and Multi-cycle
techniques
 RISC-style architecture
 Pipelined methodology
 Branch Prediction methodologies
M2 Speedup the Processor’s Performance  Super-scalar architecture
 Dynamic scheduling, out-of-order
execution, Scoreboarding &
Tomasulo techniques
 Cache memory: organization,
architecture, performance and
Speedup the data and instructions’ store and retrieve
complexity analysis and Prefetching
M3 process using fast and large storage units: cache and
main memory  Main memory: organization,
architecture, performance, and
complexity

Tentative Lecture Schedule:

Module Lecture Topic Reference

No No
1-2 Motivation, introduction, past, present, and future Class Notes
Single-purpose processor design techniques: Single-
3-4 cycle, Multi-cycle and Pipelined, Data path, Control Class Notes
path, Control generation techniques.
Planning and classification of instructions, Identify
the components for data-path and its design
techniques: combinational and sequential. Identify
M1
the components for control-path and control Class Notes, T1
generation techniques. (Chapter-3,
5-8
von Neumann model: memory, Appendix-D),
processing/computation (CPU), input/output, Research papers
control unit (CU).
Complexity analysis of instruction set architecture
(ISA): CISC and RISC models.
 Case study: MIPS instructions set architecture &
Domain-specific ISA design
Processor design methodologies: single-cycle, Class notes and T2
multi-cycle and pipelined. (Appendix-C)
9-15
Case studies: MIPS Architecture, MIPS
programming
ILP: Performance analysis of pipelined-based
architecture, including Hazards, Hazards in pipeline-
based MIPS Architecture: structural, data and
Class Notes,
control, Data Hazards and its Mitigation (Software
T1 (Chapter-4,
and Hardware-based) Techniques: Stalling,
M2 16-24 Appendix-A),
Forwarding; Control Hazard and its Mitigation
T2 (Chapter-3,
Techniques: Branch Prediction Techniques, Super-
Appendix-C)
scalar architecture, Dynamic Scheduling, Out-of-
order execution, Reorder buffer, Scoreboarding &
Tomasulo technique.
Cache (SRAM): organization, architecture and
optimization: address mapping techniques, types of
Class Notes,
cache misses, cache read and write policies,
25-32 T1(Appendix-B), T2
replacement policies, the necessity of cache
(Chapter-2)
hierarchy and its management. Prefetching
techniques.
M3
Main memory (DRAM): organization and
architecture: interleaving technique for memory Class Notes,
33-40 access, communication with cache memory, row- T1(Appendix-B), T2
buffer management policies, address mapping, (Chapter-2)
refresh management and memory scheduling.
41 Summary

Evaluation guidelines:

Evaluation Duration Weightage Nature of

Date & Time
Component (Mints) (%) Component
Lab 1: Aug 6, 2024 [Demo]
Lab 2: Aug 13, 2024
Lab 3: Aug 20, 2024
Lab 4: Aug 27, 2024
Lab 5: Sep 3, 2024
Lab 6: Sep 10, 2024
Lab 7: Sep 17, 2024 [Test]
Lab.
Lab 8: Sep 24, 2024 Open Book,
Best 7 labs out - 15
Demo, and Viva
of 10 labs
Lab 9: Oct 15, 2024 [Demo]
Lab 10: Oct 22, 2024
Lab 11: Oct 29, 2024
Lab 12: Nov 05, 2024 [Demo?]
Lab 13: Nov 12, 2024
Lab 14: Nov 19, 2024 [Test]
Lab 15: Nov 28, 2024
Lab 7: Sept 17, 2024
Lab. Test 15 TBA
Lab 14: Nov 19, 2024
Midsem 90 30 As per the timetable TBA
Comprehensive 180 40 As per the timetable TBA
Lab. Assignments and Project:
 Students shall implement all the assignments.
 Assignments will be evaluated individually through a viva-voce / demonstration.
 Assignments are to be completed in time with no postponements.
 Projects will be evaluated individually through a viva-voce / demonstration.
Malpractice Regulations:
1. Any student or team of students found involved in mal-practices in working out assignments will be awarded negative
marks equal to the weightage of that assignment and will be blacklisted.
2. Any student or team of students found repeatedly – more than once across all courses – involved in mal-practices
will be reported to the Disciplinary Committee for further action. This will be in addition to the sanction mentioned
above.
3. A mal-practice - in this context - will include but not be limited to:
 Submitting some other student’s / team’s solution(s) as one’s own;
 Copying some other student’s / team’s data or code or other forms of a solution;
 Seeing some other student’s / team’s data or code or other forms of a solution;
 Permitting some other student / team to see or to copy or to submit one’s own solution;
 OR other equivalent forms of plagiarism wherein the student or team does not work out the solution and/or
uses some other solution or part thereof (such as downloading it from the web).

4. The degree of mal-practice (the size of the solution involved or the number of students involved) will not be
considered as mitigating evidence. Failure on the part of instructor(s) to detect mal-practice at or before the time of
evaluation may not prevent sanctions later on.

Online mode of content delivery: Google Meet.

Google Meet Consultation Hour: To be announced in the class.

Notice: Notice concerning this course will be displayed on Google Classroom and/or https://quantaaws.bits-goa.ac.in/

Makeup Policy:
 Permission of the Instructor-in-Charge is required to take a make-up.
 Make-up applications must be given to the Instructor-in-charge personally.
 A make-up test shall be granted only in genuine cases where - in the Instructor’s judgment - the student would be
virtually or physically unable to appear for the test.
 In case of an unanticipated illness preventing a student from appearing for a test, the student must present a Medical
Certificate from medical centre.
Requests for make-up for the comprehensive examination – under any circumstances – can only be made to In-charge,
Instruction Division.

Kanchan Manna
Instructor-in-Charge of CS F342