Peripheral interface controller microcontroller (PIC microcontroller) Timer:

Timer: A timer is a device that generates a signal pulse at specified time intervals. A time

interval is a "real-time" measure of time, such as 3 milliseconds. These devices are extremely

useful in systems in which a particular action, such as sampling an input signal or generating an

output signal, must be performed every X time units.

Internally, a simple timer may consist of a register, counter, and an extremely simple controller.

The register holds a count value representing the number of clock cycles that equals the desired

real-time value. This number can be computed using the simple formula:

Number of clock cycles = Desired real-time value / Clock cycle

For example, to obtain a duration of 3 milliseconds from a clock cycle of 10 nanoseconds (100

MHz), we must count (3x10-6 s / 10x10-9 s/cycle) = 300 cycles. The counter is initially loaded

with the count value, and then counts down on every clock cycle until 0 is reached, at which

point an output signal is generated, the count value is reloaded, and the process repeats itself.

A counter is nearly identical to a timer, except that instead of counting clock cycles (pulses on

the clock signal), a counter counts pulses on some other input signal.

PIC Timers

• Available in all PICs

• may generate interrupts on timer overflow

• Some 8 bits some 16 bits some have prescalers

• Some can connect to external clock, some to the processor clock, some to either.

• Read/write a number as the current count is possible for some.

• The device has three readable and writeable hardware timers that can increment automatically

each instruction cycle (if no prescaler is used).

• All timers can cause an interrupt on overflow, and then restart from zero.

Timer 0

 timer/counter with prescale

• Timer 1

 timer/counter with prescale

• Timer 2

 timer only with prescale and postscale

• Watch Dog Timer

Timer0:

• 8 bit timer/counter with prescaler

• Readable and writeable

• 8-bit software programmable prescaler

• Internal or external clock set

• Interrupt on overflow from 0xFF to 0x00

• Edge Select for external clock

Prescaler:

• Prescaler is a name for the part of a microcontroller which divides oscillator clock before it will

reach logic that increases timer status.

• Number which divides a clock is defined through first three bits in OPTION register.

• The highest divisor is 256. This actually means that only at every 256th clock, timer value

would increase by one.

• This provides us with the ability to measure longer timer periods .

• After each count up to 255, timer resets its value to zero and starts with a new cycle of counting

to 255.

• During each transition from 255 to zero, T0IF bit in INTCON register is set.
– If interrupts are allowed to occur, this can be taken advantage of in generating interrupts and

in processing interrupt routine.

– It is up to programmer to reset T0IF bit in interrupt routine, so that new interrupt or new

overflow could be detected.

Figure timer0 [1]

Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT.

Additional information on the Timer0 module is available in the PICmicro™ Mid-Range MCU

Family Reference Manual (DS33023). Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle

(without prescaler). If the TMR0 register is written, the increment is inhibited for the following

two instruction cycles. The user can work around this by writing an adjusted value to the TMR0

register.
Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0

will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge

is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit

T0SE selects the rising edge. The prescaler is mutually exclusively shared between the Timer0

module and the Watchdog Timer. The prescaler is not readable or writable.

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This

overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE

(INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service

Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

Using Timer0 with an External Clock:

When no prescaler is used, the external clock input is the same as the prescaler output. The

synchronization of T0CKI with the internal phase clocks is accomplished by sampling the

prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary

for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least

2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.

Prescaler:

There is only one prescaler available, which is mutually exclusively shared between the Timer0

module and the Watchdog Timer. A prescaler assignment for theTimer0 module means that there

is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable

(see Figure 5-1). The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler

assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to
the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog

Timer. The prescaler is not readable or writable

Timer1:

• 16-bit timer/counter with prescaler

• Readable and writeable

• 1, 2, 4, 8 programmable prescaler

• Internal or external clock select

• External clock can be syn. or asyn.

• Interrupt on overflow

• Second crystal permitted

The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and

TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L)

increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is

generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt

can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

• As a timer

• As a counter

The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).

In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on

every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>). Timer1 also has an internal “RESET input”. This RESET

can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the Timer1

control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2

and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored, and

these pins read as ‘0’. Additional information on timer modules is available in the PICmicro™

Mid-Range MCU Family Reference Manual (DS33023).

T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

- - T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7-6 Unimplemented: Read as '0'

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock

to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since

the internal clock is always in sync.

Timer1 Counter Operation

Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the

setting of the TMR1CS bit. When Timer1 is being incremented via an external source,

increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must

first have a falling edge before the counter begins to increment

Timer1 Operation in Synchronized Counter Mode:

Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every

rising edge of clock input on pin RC1/T1OSI/CCP2, when bit T1OSCEN is set, or on pin

RC0/T1OSO/T1CKI, when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external

clock input is synchronized with internal phase clocks. The synchronization is done after the

prescaler stage. The prescaler stage is an asynchronous ripple-counter. In this configuration,

during SLEEP mode, Timer1 will not increment even if the external clock is present, since the

synchronization circuit is shut-off. The prescaler, however, will continue to increment.

TIMER2

•8-bit timer/counter with prescaler and postscaler

• Readable and writeable

• 1,4 or 16 programmable prescaler

• 4-bit programmable postscaler

• Interrupt on overflow

• Output to port pin

Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base

for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is

cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or

1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an

8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to

00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is

initialized to FFh upon RESET.The match output of TMR2 goes through a 4-bit postscaler

(which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)). Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>), to

minimize power consumption.

Figure timer 2

T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 Unimplemented: Read as '0'

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

0010 = 1:3 Postscale

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (POR, MCLR Reset, WDT Reset, or BOR) TMR2 is not cleared when

T2CON is written.