Computer Organization Design Notes
Computer Organization Design Notes
Register Transfer Language (RTL) is a symbolic notation used to describe operations in registers
and data transfers. It provides a means to represent the sequence of micro-operations required to
- Register Transfer: Moves data from one register to another using control signals.
- Memory Transfer: Explains how data is transferred between memory and registers via a bus.
- Micro-Operations: Describes arithmetic (add, subtract), logical (AND, OR), and shift (left, right)
Example: Consider a register operation where R1 <- R2 + R3. This means that the data from
Bus Architecture:
A multiplexer connects multiple devices to the bus, allowing communication between CPU, memory,
and I/O devices. Tri-state buffers ensure that only one device uses the bus at a time.
The ALU performs all arithmetic, logical, and shift operations required by the processor. It is an
Decode, Execute.
- Input-Output Configuration: Describes how the CPU communicates with external devices.
Example: The instruction cycle in a computer consists of fetching an instruction from memory,
decoding it to determine what operation to perform, executing the operation, and then writing back
results.
- High-Level Languages: Easier for humans to understand and write, like Python or C.
The CPU executes instructions and manages operations in a computer. It consists of:
- General Register Organization: Describes the structure and function of CPU registers.
- Stack Organization: Utilizes a stack to hold temporary data in a last-in, first-out (LIFO) manner.
- Instruction Format: The format of instructions and how they are processed.
GPU Overview:
A GPU performs high-speed parallel processing and is used for graphical computations and
machine learning tasks.
2. Memory Hierarchy
- Cache Mapping: Methods include direct mapping, associative mapping, and set-associative
mapping.
- Virtual Memory: Provides the illusion of larger memory using disk storage.
Example: A fully associative cache allows any block to be placed anywhere in the cache.
The PIV processor uses multiple levels of cache to speed up memory access. AMD Opteron uses a