A magnitude digital Comparator is a combinational circuit that compares

two digital or binary numbers in order to find out whether one binary
number is equal, less than, or greater than the other binary number. The
truth table for a 2-bit comparator is given below:

From the above truth table K-map for each output can be drawn as follows:
From the above K-maps logical expressions for each output can be
expressed as follows:

A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A1’B1 + A0’B1B0 + A1’A0’B0
By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below:
4 : 2 Encoder –

The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two
outputs A1 & A0. At any time, only one of these 4 inputs can be ‘1’ in order
to get the respective binary code at the output. The figure below shows the
logic symbol of 4 to 2 encoder :

The Truth table of 4 to 2 encoder is as follows :

Logical expression for A1 and A0 :
A1 = Y3 + Y2
A0 = Y3 + Y1
The above two Boolean functions A1 and A0 can be implemented using two
input OR gates :

Priority encoder:

A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1

& A0. Here, the input, Y3 has the highest priority, whereas the input, Y0
has the lowest priority. In this case, even if more than one input is ‘1’ at the
same time, the output will be the (binary) code corresponding to the input,
which is having higher priority.

The truth table for priority encoder is as follows :

The above two Boolean functions can be implemented as :

Truth Table relating BCD to Gray Code

Decimal BCD input Gray Code output
B3 B2 B1 B0 D3 D2 D2 D0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
Boolean expression for each BCD bits can be written as
D3= m(8, 9)
D2= m(4, 5, 6, 7, 8, 9)
D1= m(2, 3, 4, 5)
D0= m(1, 2, 5, 6, 9)

Realizing code conversion using Logic Gates

Binary to Gray conversion :

 1. The Most Significant Bit (MSB) of the gray code is always equal to
the MSB of the given binary code.
2. Other bits of the output gray code can be obtained by XORing
binary code bit at that index and previous index.

Binary code to gray code conversion

Gray to binary conversion :

1. The Most Significant Bit (MSB) of the binary code is always equal to
the MSB of the given gray code.
2. Other bits of the output binary code can be obtained by checking
the gray code bit at that index. If the current gray code bit is 0, then
copy the previous binary code bit, else copy the invert of the
previous binary code bit.

t's output is HIGH, if odd number of inputs are HIGH and LOW otherwise.
A ring counter is a typical application of the Shift register. The ring counter is
almost the same as the shift counter. The only change is that the output of
the last flip-flop is connected to the input of the first flip-flop in the case of the
ring counter

So, for designing a 4-bit Ring counter we need 4 flip-

flops.

In this diagram, we can see that the clock pulse (CLK) is applied to all the
flip-flops simultaneously. Therefore, it is a Synchronous Counter. Also, here
we use Overriding input (ORI) for each flip-flop. Preset (PR) and Clear (CLR)
are used as ORI. When PR is 0, then the output is 1. And when CLR is 0,
then the output is 0. Both PR and CLR are active low signal that always
works in value 0.
PR = 0, Q = 1
CLR = 0, Q = 0
These two values are always fixed. They are independent of the value of
input D and the Clock pulse (CLK). Working – Here, ORI is connected to
Preset (PR) in FF-0 and it is connected to Clear (CLR) in FF-1, FF-2, and
FF-3. Thus, output Q = 1 is generated at FF-0, and the rest of the flip-flop
generates output Q = 0. This output Q = 1 at FF-0 is known as Pre-set 1
which is used to form the ring in the Ring
Counter.

This Preseted 1 is generated by making ORI low and that time Clock (CLK)
becomes don’t care. After that ORI is made to high and apply low clock pulse
signal as the Clock (CLK) is negative edge triggered. After that, at each clock
pulse, the preseted 1 is shifted to the next flip-flop and thus forms a Ring.
From the above table, we can say that there are 4 states in a 4-bit Ring
Counter.

Propagation delay is the time duration taken for a signal to reach its
destination.
The circuit's ability to tolerate noise signals is referred to as the noise immunity,
a quantitative measure of which is called noise margin.

Fan-in is the number of inputs a logic gate can handle.

In digital electronics, the fan-out is the number of gate
inputs driven by the output of another single logic gate.
The definition of power dissipation is the process by which an
electronic or electrical device produces heat (energy loss or
waste) as an undesirable derivative of its primary action.

The circuit diagram of CMOS NAND is shown below:

CMOS NOR
CMOS NOR logic gate is a combination of NMOS NOR and PMOS NAND.
The circuit diagram is shown below:
A hazard in a digital circuit is a temporary disturbance in ideal operation of
the circuit which if given some time, gets resolved itself. A hazard, if exists,
in a digital circuit causes a temporary fluctuation in output of the circuit.
There are three different kinds of hazards found in digital circuits
1. Static hazard : a static hazard takes place when change in an
input causes the output to change momentarily before stabilizing to
its correct value.
2. Static-1 Hazard: If the output is currently at logic state 1 and after the
input changes its state, the output momentarily changes to 0 before
settling on 1, then it is a Static-1 hazard.
3. Static-0 Hazard: If the output is currently at logic state 0 and after the
input changes its state, the output momentarily changes to 1 before
settling on 0, then it is a Static-0 hazard.

4. Dynamic hazard :When the output changes for two neighboring

input combinations at the same time, this is referred to as be
a dynamic hazard.
5. Essential hazard : This type of hazard is caused by unequal
delays along two or more paths that originate from the
same input. An excessive delay through an inverter circuit
in comparison to the delay associated with the feedback
path may cause such a hazard.

Universal shift register :

6. The first input (zeroth pin of multiplexer) is connected to the output pin
of the corresponding flip-flop.
7. The second input (first pin of multiplexer) is connected to the output of
the very-previous flip flop which facilitates the right shift.
8. The third input (second pin of multiplexer) is connected to the output of
the very-next flip-flop which facilitates the left shift.
9. The fourth input (third pin of multiplexer) is connected to the individual
bits of the input data which facilitates parallel loading.

A Counter is a device which stores (and sometimes displays) the number of

times a particular event or process has occurred. Counters are sequential
circuit that count the number of pulses can be either in binary code or BCD
form. The main properties of a counter are timing , sequencing , and
counting. Counter works in two modes
Up counter
Down counter
counter is basically used to count the number of clock pulses applied to a
flip-flop.
Ripple counter is a cascaded arrangement of flip-flops where the output of
one flip-flop drives the clock input of the following flip-flop.
Some of the features of ripple counter are:
1. It is an asynchronous counter.
2. Different flip-flops are used with a different clock pulse.
3. All the flip-flops are used in toggle mode.
4. Only one flip-flop is applied with an external clock pulse and
another flip-flop clock is obtained from the output of the previous
flip-flop.

The distinction between PLA and PAL is that, PAL have programmable AND
array and fixed or array. On the other hand, PLA have programmable AND
array and programming OR array.

Difference between PLA and PAL

S.No. PLA PAL

1. The full form of PLA is Programmable Logic The full form of PAL is Programmable Array
Array. Logic.

2. The speed of PLA is lower than PAL. The speed of PAL is higher than PLA.

3. The complexity of PLA is high as compared to The complexity of PAL is less as compared to
PAL. PLA.

4. It is expensive. It is not that expensive.

5. When it comes to availability, it is less available. PAL is more available as compared to the PLA.

6. It is less used as compared to the PAL. It is more used as compared to PLA

The resistor-transistor logic(RTL) is the first digital circuit to
construct the logic gates. It is also known as Transistor-Resistor
Logic or TRL. Here, the resistor and transistor are used to make
the logic gates. The resistor is used as the input component and
the transistor is used as the output component
In a transistor-transistor logic, logic gates are built with bipolar
junction transistors. Here, one transistor works for amplifying
while another works for switching