e-ISSN: 2582-5208

International Research Journal of Modernization in Engineering Technology and Science

( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:06/Issue:04/April-2024 Impact Factor- 7.868 www.irjmets.com

VERIFICATIONOFI2CPROTOCOLUSING
SYSTEM VERILOG CODE
AKASH KUMAR M*1, ANBUMATHI A*2, VASANTH KUMAR K*3,VIDHAYALAKSHMI P*4
*1Professor,Electronics And Communication Engineering,

Adhi College Of Engineering And Technology,Kanchipuram,

Tamil Nadu,India.
*2,3,4,5 Student,Electronics And Communication Engineering And Technology,

Kanchipuram,India.

ABSTRACT
The I2C (Inter-Integrated Circuit) protocol is widely used for communication between integrated circuits in
embedded systems. This project focuses on verifying the functionality and compliance of an I2C communication
interface using SystemVerilog. The verification process involves creating testbench and test cases to simulate
I2C communication between devices. Various scenarios, such as data transfer, addressing, clock stretching,and
error handling, aretested to ensure the robustness and reliability of the I2C implementation. The project aims
to provide a comprehensive verification solution for I2C-based systems, ensuring their proper operation in
real-world applications.

I. INTRODUCTION
The I2C (Inter-Integrated Circuit) protocol is a widely used serial communication protocol embedded
systems for connecting microcontrollers to peripheral devices. It is a simple and efficient protocol that
allows multiple devices to communicate with each other over as hared bus. However,verifying the
functionality and compliance of an I2C interface can be challenging due to its complex timing requirements
and various operating modes.
This project focuses on verifying an I2C communication interface using SystemVerilog, a hardware
description and verification language. The goal is to ensure that the I2C interface operates correctly
according to the specifications and can handle various scenarios such as data transfer, addressing, clock
stretching, and error handling. By creating a comprehensive verification environment with SystemVerilog,
this project aims to provide a reliable and efficient solution for verifying I2C-based systems, ultimately
ensuring their proper operation in real-world applications.

Figure1. Block Diagram

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 e-ISSN: 2582-5208
International Research Journal of Modernization in Engineering Technology and Science
( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:06/Issue:04/April-2024 Impact Factor- 7.868 www.irjmets.com
II. LITERATURE SURVEY

[1] The verification phase carries an important role in design cycle of a System on Chip (SoC). A
verification environment may be prepared using SystemVerilog without using any particular methodology
but that will be different for every variation of the design. There are various verification methodologies out
of which Universal Verification Methodology (UVM) is the state-of the-art and widely preferred by the
verification industry worldwide, as the verification environment created using UVM is reusable, efficient and
well structured. In this work we have compared the SystemVerilog and UVM verification environments.-
RakhiNangia, NeerajKr,Shukla–June,2014.

[2] Today’s world has reached ago which complete module can be instigated on a one chip called SOC
(system on chip).Protocols are required to combine these components. One such simple and emerging
development protocol is the I2C protocol. I2C uses only two initial fundamentals bidirectional buses of pull
up resistors configuration i.e Serial Clock Line (SCA) and Serial Data line (SDL). This protocol provides an
efficient & simple method of data transaction among the devices.- Nayana D K1, Sangeeta – 23 May 202.

III. METHODOLOGY

EXISTING SYSTEM
The existing system for verifying the I2C protocol using SystemVerilog, particularly within the Aldec Riviera-
PRO environment, comprises a comprehensive set of components and processes. Aldec Riviera-PRO serves as
the foundational simulation tool, offering functionalities ranging from RTL simulation to assertion-based
verification and waveform viewing. Within this environment, a SystemVerilog testbench is developed to
orchestrate the verification process. This testbench encompasses modules responsible for generating stimulus,
monitoring signals, and assessing protocol compliance. Central to this system is the I2C Design Under Test
(DUT), representing the RTL implementation of the I2C protocol. Instantiated within the testbench, the DUT
undergoes rigorous verification against predefined test scenarios and assertions. These scenarios encompass
various aspects of the protocol, including basic operations, error handling, and timing constraints, ensuring
comprehensive validation. Throughout simulation runs, signals are monitored, assertions are evaluated, and
coverage metrics are tracked to assess the correctness and completeness of the verification process. Finally,
documentation and reporting play a pivotal role, providing a structured means to communicate the verification
methodology, results, and insights to stakeholders and peers. This existing system provides a robust
framework for verifying the I2C protocol, facilitating the development of reliable and compliant digital
communication systems.

PROPOSED SYSTEM
A. I²C Protocol

The I²C-bus is a bidirectional serial transport which bolsters any IC manufacture handle (NMOS, CMOS,
bipolar).The exchange is continuously started by ace. It employments two wires for communication:

SDA: Transmission of any information takes places through this line.

SCL: It is a clock line which is dependable for controlling and synchronizing the communication.

A ace is the gadget which starts a information exchange on the transport and produces the clock signals to
allow that transfer. At that time, any gadget tended to is considered a slave. Clock and reset are the input lines
used to start the transport controller handle.

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B. Start and Stop Condition

To commence communication, the start condition necessitates SCL (Serial Clock) line being high, while SDA
(Serial Data) line transitions from high to low.Conversely, the stop condition is indicated when SCL is high, and
SDA transitions from low to high.During the idle state, both SDA and SCL lines maintain a high signal.

Fig,2.1 (a) “START” Sequence.(b) “STOP” Sequence

C. Acknowledgement

In the I²C protocol, upon transmitting the address byte, the master device releases the SDA line, allowing the
receiver (slave) to acknowledge by pulling the SDA line low. Following this acknowledgment, the master device
generates the clock signal to read the acknowledgment bit. If an acknowledgment (ACK) is received, the master
device proceeds with the desired read or write operation. However, if none of the slaves on the bus
acknowledge the address, the SDA line remains high, indicating a Not Acknowledged (NACK) condition. In
response to a NACK, the master device can choose to issue a STOP command to terminate the communication
or reissue the START command to attempt communication with another slave device. This protocol ensures
reliable communication between master and slave devices while allowing for error detection and recovery.

Fig. 2.2 ACK received on the SDA line

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Fig. 2.3 NACK received on the SDA line.

D. Serial Data Communication

Two transmission modes exist: Master Transmission mode and Master Receiver mode.In Master
Transmission mode, the master initiates communication by emitting the start condition followed by the 7-
bit slave address, with the most significant bit (MSB) transmitted first. The direction bit (R/W) determines
whether it's a write (W=0) or read (W=1) operation. Following each byte of data, the receiver sends an
acknowledgment. The communication concludes with a stop condition.

Fig.2.4 Master Transmission Mode

In Master Receiver mode, data is received from the slave in transmitter mode. The master transmits the slave
address followed by the direction bit indicating read mode. The slave responds with acknowledgment bit.
Subsequently, a repeated start condition is initiated, succeeded by the slave address with read mode, and the
slave transmits the data with acknowledgment. The communication concludes with a stop condition.

Fig.2.5 Master Receiver Mode

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III. VERIFICATION ENVIRONMENT

Fig.3.Verification Environment

I. Generator:The scenario generator is a crucial component of the verification environment responsible for
creating test scenarios based on input variables and random stimuli. It utilizes mailboxes as temporary data
storage,facilitating the transmission of input variables to the driver at the packet level.

II. Interface Driver: The interface driver performs the conversion of data from the packet level to pin-
level input variables. These signals are then transmitted through the interface to configure and reset the Device
Under Test (DUT). Following this, the driver forwards these input signals to the monitor and scoreboard via
transaction mailboxes.

III. Data Monitor:The data monitor analyzes the data received and transmitted by the DUT through the
interface. It tracks the Serial Clock Line (SCL) and Serial Data Line (SDA) and provides various information
corresponding to the ongoing functions, such as read or write operations, as well as start, stop, and data
transfer operations. Additionally, the monitor converts pin-level data into packet-level data, which is essential
for scoreboard operation.

IV. Result Scoreboard:The scoreboard collects data from the monitor and generator mailboxes and
compares the results of these two transactions. It verifies whether the collected information aligns with the
expected outcomes.

V. Device Under Test (DUT):The DUT represents the design conforming to the protocol specification. It
is utilized within the environment to verify the features and functions of the I²C protocol using the
SystemVerilog language.

IV. SOFTWARE DESCRIPTION

Aldec Riviera-PRO is a versatile verification platform tailored for comprehensive digital design validation,
including intricate protocols like I2C. Offering a rich set of features and capabilities, Riviera-PRO excels in RTL
simulation, SystemVerilog support, and assertion-based verification. In our project, Riviera-PRO served as the
cornerstone of our verification environment, facilitating the rigorous testing of our I2C protocol
implementation. We seamlessly integrated our SystemVerilog testbench with the platform, leveraging its
robust simulation engine to execute extensive test scenarios. With Riviera-PRO's support for assertion-based
verification, we specified intricate protocol constraints and properties to ensure compliance and correctness.
During simulation runs, the platform's intuitive debugging tools provided invaluable insights into design

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behavior, enabling prompt issue identification and resolution. Overall, Aldec Riviera-PRO proved instrumental
in our verification efforts, empowering us to deliver a reliable and compliant I2C design.

V. ANALYSIS
Verification Methodology Evaluation:
Our project aimed to validate the I2C protocol using SystemVerilog within the Aldec Riviera-PRO environment.
The chosen methodology effectively addressed the complexities of the I2C protocol by leveraging
SystemVerilog's powerful constructs and Riviera-PRO's robust simulation capabilities. The verification
environment successfully captured the intricacies of the protocol, including start and stop conditions, data
transmission, and error handling scenarios. By utilizing assertion-based verification, we were able to define
and enforce protocol constraints, ensuring compliance with the I2C specification.

Validation Results Interpretation:

The results obtained from our verification process provided valuable insights into the functionality and
robustness of the I2C protocol implementation. Through extensive simulation runs, we observed consistent and
accurate behavior of the protocol under various test scenarios. Start and stop conditions were executed
correctly, data transmission occurred without errors, and the protocol handled bus contention and arbitration
effectively. The validation results confirmed the reliability and correctness of the I2C design, meeting our
expectations and validating the efficacy of our verification methodology.

Comparison with Existing Methods:

Comparing our verification methodology with existing approaches, we found that the combination of
SystemVerilog and Aldec Riviera-PRO offered significant advantages in terms of efficiency and ease of use.
While other verification tools may offer similar capabilities, Riviera-PRO's seamless integration with
SystemVerilog and its intuitive debugging features provided a streamlined verification experience. Our
methodology demonstrated superior scalability and coverage, allowing for comprehensive validation of the I2C
protocol with minimal overhead.

Significance of Findings:
The validated I2C protocol holds significant implications for the reliability and interoperability of digital
systems utilizing the I2C communication interface. By confirming the protocol's adherence to specifications
and standards, our findings contribute to the advancement of digital communication technologies. The verified
I2C design serves as a foundation for the development of robust and dependable digital systems in various
applications, ranging from consumer electronics to industrial automation.

Limitations and Challenges:

While our verification process yielded promising results, we encountered certain limitations and challenges
during the project. These included the complexity of modeling real-world scenarios, such as timing constraints
and bus capacitance effects, within the simulation environment. Additionally, achieving complete coverage of
all protocol features and corner cases proved challenging and may require further refinement of our
verification methodology in future endeavors.

Future Directions: Moving forward, we envision several opportunities for enhancing our verification
methodology and extending our research efforts. This includes exploring advanced verification techniques,
such as formal verification and emulation, to augment our simulation-based approach. Furthermore, extending
the scope of our study to encompass other digital communication protocols and integrating hardware-in-the-
loop testing can provide a more comprehensive validation framework for digital system designs.

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VI. SIMULATION RESULTS

Fig.3.1 Clock Generation.

Fig. 3.2 Simulation result of Master for Slave1

Fig 3.3 Simulation result of Master for Slave 2

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Fig 3.4: Simulation result of Master for Slave 3

CONCLUSION

In conclusion, the verification of the I2C protocol using SystemVerilog within the Aldec Riviera-
PRO environment has been a significant undertaking with far-reaching implications. Through a
meticulous verification methodology and thorough simulation-based testing, we have successfully
validated the functionality, reliability, and compliance of the I2C protocol implementation.Our
analysis of simulation results has provided valuable insights into the intricate workings of the
protocol, confirming its correctness and robustness under various test scenarios. From basic
protocol operations to error handling mechanisms and timing constraints, the verified I2C design
has demonstrated compliance with specifications and standards, ensuring interoperability and
reliability in practical applications.This project underscores the efficacy of SystemVerilog and
simulation-based verification in ensuring the reliability of digital communication protocols. By
leveraging Aldec Riviera-PRO's advanced features and capabilities, we have established a
structured approach to protocol verification that can be applied to other digital communication
standards with ease.

Looking ahead, there are several avenues for further research and refinement of our verification
methodology. Future endeavors may explore advanced verification techniques, such as formal
verification and hardware-in-the-loop testing, to augment simulation-based validation.
Additionally, extending the scope of our study to encompass other digital communication
protocols can provide a more comprehensive understanding of digital system behaviors.Ultimately,
the successful verification of the I2C protocol represents a significant milestone in the
development of reliable digital communication systems. By ensuring the correctness and
compliance of the protocol implementation, we pave the way for the seamless integration of I2C-
based devices in a wide range of applications, from consumer electronics to industrial automation,
fostering innovation and technological advancement.

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International Research Journal of Modernization in Engineering Technology and Science
( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:06/Issue:04/April-2024 Impact Factor- 7.868 www.irjmets.com

ACKNOWLEDGEMENT

At this moment we would like to add a few heartfelt thanks for the people who made this project successful.
We would like to take this pleasant moment to thank our management for
creatinganenvironmenttocarryourproject.VeryspecialthankstourHonorable Chairman Dr.SARANRAJ S and
CEO Dr.SUJATHAMARAN,for motivating us to carry out project successfully.

With deep sense of gratitude, we thank our beloved principal Dr.DEVARAJU A who has always been a
constant Source of inspiration and has rendering his kind cooperation to complete our project.
With deep sense of gratitude to Dr. DINESH BABU K, Head of the department for his words of wisdom
and also for encouraging us in right way from the beginning and also, we thank Mr.THIRUMURUGAN R,
internal guide for constant guidance and also thanks to TEACHING AND NON-TEACHING STAFFS of our
department who rendered their valuable guidance in making this project a reality.
We also express our gratitude to our PARENTS and FRIENDS who had support us and help us to keep
the enthusiasm in completing the project successfully.

REFERENCES

[1] Nayana D K, Sangeeta,Design and Verification for I2C interface protocol Using System Verilog,Turkish
Journal of Computer and Mathematics Education: C Software & Data Engineering, Volume 12, No.12(2021), pp
80-84

[2] Rakhi Nangia and Neeraj Kumar Shukla, “Functional Verification of I2C Core Using System Verilog,”
International Journal of Engineering Science and Technology, Vol. 6, No. 4,2014, pp. 31-44.

[3] Yashaswini Pandit and Manoj P B, “Verification of I2C Single-Master Multiple Slave Bus Controller
Using System Verilog”, International Journal of Electrical,Electronics and Computer Systems, Vol. 2,Issue-
4,2014.

[4] Shivani Mehrotra, Nisha Charaya,“Design of I2C Single Master Using Verilog,” International Journal of
Science and Research, Vol. 4, Issue. 1, Jan 2015,pp. 19-64.

[5] Dr.Ch.Manohar Kumar,Mr.G.Mahesh Babu, Mr.A.Hemanth Chakradhar “Verification of UART and I2C
Protocols Using System Verilog”, International Journal of Innovative Research in Computer Science &
Technology – Volume 11, Issue 2, March 2023, Pg.58-61.

[6] Anuja Dhar, Ekta Dudi and Hema Tiwari, “Coverage Driven Verification of I2C Protocols Using System
Verilog”, International Journal of AdvancedResearch in Engineering and Technology (IJARET)-Volume 7,Issue
3,May-June 2016,pp.103-11.

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