C

UNIT V MEMORY AND PROGRAMMABLE LOGIC

RAM Memory Decoding Error Detection and Correction - ROM - Programmable Logic Array Programmable
Array Logic Sequential Programmable Devices.
Memory unit

□ A collection of cells capable of storing a large quantity of binary information and

 to which binary information is transferred for storage
 from which information is available when needed for processing

□ Together with associated circuits needed to transfer information in and out of

the device
• Write operation: storing new information into memory
• Read operation: transferring the stored

information Two major types: RAM & ROM

o RAM (Random-access memory): Read + Write- accept new information for

storage to be available

o ROM (Read-only memory): perform only read

Programmable Logic Devices (PLD)

 An integrated circuit with internal logic gates
• hundreds to millions of gates interconnected through hundreds to thousands of
internal paths
 Connected through electronic paths that behave similar to fuse
• In the original state, all the fuses are intact
 Programming the device
• blowing those fuse along the paths that must be removed in order to obtain
particular configuration of the desired logic
function. Types of PLD

□ Programmable logic array

□ Programmable array logic
□ Programmable ROM
□ Sequential PLD
Memory Decoding
RAM of m words and n bits: m*n binary storage cells
•SRAM cell: stores one bit in its internal latch
–SR latch with associated gates, 4-6 transistors
Error Detection and Correction
□ Error detection is the ability to detect errors
□ Error correction has an additional feature that enables identification and
correction of the errors
 Programmable Logic Array (PLA)
 An array of programmable AND gates
Programmable Array Logic:
 A programmable AND array and a fixed OR array

Sequential Programmable Devices

SPLD includes flip-flops and AND-OR array
 Flip-flops connected to form a register
 FF outputs could be included in product terms of AND array
Application Specific Integrated Circuits.
In order to be competitive, companies must develop new products and enhance existing
ones by incorporating the latest commercial VLSI chips; and more-and-more by designing
chips which are uniquely tailored for their own applications.
These so-called “Application Specific Integrated Circuits” (ASICs) are changing the way
electronic systems are designed, manufactured, and marketed.

RAM

□ A memory unit stores binary information in groups of bits

– 1 byte = 8 bits
– 16-bit word = 2 bytes, 32-bit word = 4 bytes
□ Interface
– n data input and output lines
– k address selection lines
– control lines specifying the direction of transfer
□ Addressing
– each word is assigned to an address
– k-bit address: 0 to 2k – 1 word
– size: K(kilo)=210, M(mega)=220, G(giga)=230
– A decoder accepts an address and opens the paths needed to selection
the word specified

Block diagram of a memory unit

 `
Example: 1K words of 16 bits

Capacity: 1K*16 bits=2K bytes=2,048 bytes

Addressing data:16 bit data and 10 bit address

Write and Read Operations
•Steps of Write operation
–Apply the binary address to the address lines
–Apply the data bits to the data input lines
–Activate the write input
•Steps of Read operation
–Apply the binary address to the address lines
–Activate the read input
• Two ways of control inputs:
–separate read and write inputs
–memory enable (chip select) + Read/write (operation select)
• widely used in commercial or multi-chip memory components

Timing Waveforms of Memory

□ Memory operation control: usually controlled by external devices such as CPU

–CPU provides memory control signals to synchronize its internal clocked
operations with memory operations
 –CPU also provides the address for the memory
□ Memory operation times
–access time: time to select a word and read it
–cycle time: time to complete a write operation
□ Both must be within a time equal to a fixed number of CPU clock cycles

Write Cycle

Memory cycle timing waveform

Types of Memories
□ Random vs. sequential
–Random-Access Memory: each word is accessible separately
•equal access time
□ Sequential-Access Memory: information stored is not immediately
accessible but only at certain intervals of time
•magnetic disk or tape
•access time is variable
•Static vs. dynamic
 □ SRAM: consists essentially of internal latches and remains valid as long as
power is applied to the unit
□ DRAM: in the form of electric charges on capacitors which are provided
inside the chip by MOS transistors
ROM:

 Permanent binary information is stored

–pattern is specified by the designer
–stays even when power is turned off and on again
 Pin
s –k address inputs and n data outputs
–no data inputs since it doses not have a write operation
–one or more enable inputs

ROM block diagram

Example: 32x8 ROM

• A 2kxn ROM has an internal k x2k decoder and n OR

• 32 words of 8 bits each
– 32*8=256 programmable internal connections
– 5 inputs decoded into 32 distinct outputs by 5x32 decoder
–Each of 8 OR gates have 32 inputs

ROM truth table

 Internal logic of 32 X 8 ROM
Types of ROM
4 methods to program ROM paths
• Mask programming ROM
– customized and filled out the truth table by customer and
masked by manufacturers during last fabrication process
– costly; economical only if large quantities
• PROM: Programmable ROM
–PROM units contain all the fuses intact initially
– Fuses are blown by application of a high-voltage pulse to the device through a
-special pin by special instruments called PROM programmers
–Written/programmed once; irreversible
• EPROM: erasable PROM
– floating gates served as programmed connections
–When placed under ultraviolet light, short wave radiation discharges
thecgates and makes the EPROM returns to its initial state
– reprogrammable after erasure
• EEPROM: electrically-erasable PROM
– erasable with an electrical signal instead of ultraviolet light
– longer time is needed to write
– flash ROM: limited times of write operations
Memory decoding

 RAM of m words and n bits: m*n binary storage cells

•SRAM cell: stores one bit in its internal latch
 SR latch with associated gates, 4-6 transistors
 Memory Cell
Example: capacity of 16 bits in 4 words of 4 bits each
•2x4 decoder: select one of the 4 words •enabled with the Memory enable signal.
•Memory with 2k words of n bits: k address lines go into a kx2k decoder.

Diagram of a 4X4 RAM

Coincident Decoding
•Decoder complexity: a decoder with k inputs and 2k outputs requires 2k AND gates
with k inputs per gate
•2-dimensional decoding: arrange cells in a square array
•2 k/2-input decoders instead of 1 k-input decoder one for row selection and
the other for column selection
•1K-word memory –a single 10x1,024 decoder: 1,024 10- input AND gates –
two 5x32 decoders: 64 5-input AND gates
 Two Dimensional Decoding Structure for a 1K word Memory

Address Multiplexing

•DRAM: large capacity requires large address decoding –Simpler cell structure
•DRAM: a MOS transistor and a capacitor per cell
•SRAM: 6 transistors –Higher density: 4 times the density of SRAM
•larger capacity
Lower cost per bit: 3-4 times less than SRAM
• Lower power requirement–Preferred technology for large memories
•64K (=216) bits and 256M(=228) bits may need 16 and 28 address inputs
• Address multiplexing: use a small set of address input pins to accommodate the
address components–A full address is applied in multiple parts at different times
•i.e. two- dimensional array: row address first and column address second
•same set of pins is used for both parts
Advantage: reducing the number of pins for larger memory

Example: 64K-word memory

1. 256 rows x 256 columns for 28x28=216=64K words
2. Address strobes: enabling row and column address into their respective registers (no
Memory enable)
3. A single data input line
 4. A single data output line
5. A Read/Write control
6. Two address strobes–RAS: enable 8-bit row register by level 0–CAS: enable 8-bit
column register by level 0.

Address multiplexing for a 64K DRAM

Error Detection and Correction

o Error detection is the ability to detect errors Error correction has an
additional feature that enables identification and correction of the errors
o Error detection always pecedes error correction Both can be achieved by
having extra/redundant/check bits in addition to data deduce that there
is an error
o Original Data is encoded with the redundant bit(s)
o New data formed is known as code word
The simplest and oldest error detection method
Parity bits
o A binary digit called parity is used to indicate whether the number of bits with “1”
in a given set of bits is even or odd
o The parity bit is then appended to original data
o Usually used to detect transmission error
o Sender adds the parity bit to existing data bits before transmission
o Receiver checks for the expected parity, If wrong parity found, the
received data is discarded and retransmission is requested.

Parity type: Even

o Forced an even number of one’s on total data sent
o 000 0001 1000 0001
o 000 0011 0001 0001
o Generating even parity bit is just an XOR function
o Data Received Examples:
 0111 1111 - incorrect
 1000 0000 - incorrect
  1000 0001 - valid
o Note that error could be in data or parity
o Not entirely fool proof

Parity type:
Odd
Forced an odd number of one’s
000 0001 0 000 0001
000 0011 1 000 0011
Odd parity is generated using a XNOR function

Hamming Distance and Error Detection

o Hamming Distance = of bit positions in which 2 code words differ
o E.g. 10001001 and 10110001 have distance of 3
o If distance is d, then d-single bit errors are required to convert any one
valid code into another
o Implying that this error would not be detected
o Could detect 1-bit error as 4 code words had hamming distance = 2
o But could not detect 2-bit error
o In general, to detect k-single bit error, minimum hamming distance D(min)
=k+1
o If there is a larger hamming distance between valid code words
o Then we may be able to determine which valid codeword was
o intended
o Suppose a code needs just 2 different values, and we use:
 One valid value = 0000 0000 and the other = 1111 1111Then distance
between these is 8
 Suppose we got 2 bit changes so that:0000 0000 became 0011 0000
 The greater the distance between valid code words, the easier it is to
figure what the correct codeword was Requires additional redundant bits
(> 1 parity bit) to chose code words that are far apart
 D(min) = 2k + 1 is required for correcting k-errors
 Hamming Code is type of Error Correcting Code (ECC)
 Provides error detection and correction mechanism
 Adopt parity concept, but have more than one parity bit
 In general hamming code is code word of n bits with m data bits and r
parity (or check bits) i.e. n = m + r
 Can detect D(min) – 1 errors
 Can correct errors
 Hence to correct k errors, need D(min) = 2k + 1
 Need a least a distance of 3 to correct a single bit error.

Determining of Parity bits for single-bit correction

o Hamming Code for single-bit error correction is the most commonly used Experiments (IBM
study) show 98% time there are single-bit errors.
o Need determine r for m-data bits that provides code words of n-bits that has single-bit
correction capabilities.
Hamming Code: Determining Parity bits for single-bit correction
o Because n = m + r, we can rewrite the inequality as: (m + r + 1) × 2 m ≤ 2
m + r or (m + r + 1) ≤ 2 r
o This inequality gives us a lower limit on the number of parity bits that we
need in our code words
o Example: Suppose we have data words of length m = 4, (4 + r + 1) ≤ 2 r
o Implies that r must be greater than or equal to 3
o To build a code with 4-bit data words that will correct single-bit errors, we
must add 3 check bits.

Example: 12-bit Code word

o Parity bits 1 and 4 both check position 5 and 7 Since parity bit 2 checks bit
7 and indicates no error occurred in the subset of bits it checked that
means that error occurred in bit 5
o If we change bit 5 to a 1, all parity bits check and our data is restored

Error Correcting Codes (ECC) in General

o Hamming Code is type of ECC
o Others include Reed-Solomon, Convolution Code
o Requires extra bits for maintaining information integrity
o E.g. in hamming code: 3 bits are added to a 4-bit data
o The overhead of extra bits does pay off
o Single-bit correction often costs less than sending the entire data twice
o If the storage is the only source of data (e.g. disk or DRAM) then we want
a error- correction to avoid crashing of programs
Combinational PLDs
Combinational programmable logic device (PLD)
 Programmable gates divided into an AND array and an OR array
 Provide an AND-OR sum of product implementation

o A fixed AND array constructed as a decoder

o A programmable OR array to implement Boolean functions in sum of minterms
o A programmable AND array: to provide the product terms for Boolean functions
o Both can be programmed
o Most flexible
 Basic Configuration of three PLDs

Programmable Logic Array

 An array of programmable AND gates

 Can generate any product terms of the inputs
 An array of programmable OR gates
 Can generate the sums of the products
 Only the needed product terms are generated (not all)
 More flexible than ROM; use less circuits than ROM
 Size of PLA: specified by # of inputs, product terms and outputs
 n inputs, k product terms and m outputs
 n buffer-inverter gates, k AND gates, m OR gates, and m
XOR gates
 Typical PLA may have 16 inputs, 48 product terms and 8 outputs
 Designing a digital system with a PLA
 Reduce the number of distinct product terms
 The number of literals in a product is not important
 Implementing PLA
 Mask programmable PLA: submit a PLA program table to the manufacturer
 Field Programmable(FPLA): by commercial hardware programmer unit

PLA Example 1
Implement: F1(A, B, C) = Σ (0, 1, 2, 4); F2(A, B, C) = Σ (0, 5, 6, 7)
1. Simply both the true and complement of the functions in sum of products
2. Find the combination with minimum number of product terms
 F1=(AB+AC+BC)’
F2=AB+AC+A’B’C’
3. Obtain the PLA Programming table

Programmable Array Logic

PAL: a programmable AND array and a fixed OR array – easier to program, but not as
flexible as PLA

Programmable Array Logic

 Example: PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure (Figure 7-16)
 each input has a buffer-inverter gate •each output is generated by a fixed OR
 gate
  4 sections of 3-wide AND-OR array – each AND gate has 10 programmable
 input connections
 A typical PAL may have 8 inputs, 8 outputs, and 8 sections, each consisting of an 8-
 wide AND-OR array
 May use two sections to implement a large Boolean function Product terms
cannot be shared
 Each function is simplified itself

Example: PAL Implementation

• Implement the following functions
w(A,B,C,D) = Σ(2,12,13)
x(A,B,C,D) = Σ(7,8,9,10,11,12,13,14,15)
y(A,B,C,D) =
Σ(0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D)
= Σ(1,2,8,12,13)

•Simplify the functions using k map

w = ABC′ +
A′B′CD′ x = A +
BCD
y = A′B + CD + B′D′
z = ABC′ + A′B′CD′ + AC′D′ + A′B′C′D
= w + AC′D′ + A′B′C′D
 Fuse Map for PAL

□ Sequential programmable devices –combinational PLD + flip-flops Perform a

Variety of sequential-circuit functions

□ Three major types
 Field-programmable logic sequencer (FPLS)
 Complex programmable logic device (CPLD)
 Field programmable gate array (FPGA)
Many commercial vendor-specific variants and internal logic of these devices is too
 complex to be shown here

Sequential (or simple) programmable logic device (SPLD)

 includes flip-flops and AND-OR array , flip-flops connected to form a register,FF
outputs could be included in product terms of AND array
 Field-programmable logic sequencer (FPLS)
First programmable device developed, FF may be of D or JK type, not
succeed commercially due to too many programmable connections.
Combinational PAL together with D flip-flops: most used
 Macrocell: a section of an SPLD, a circuit containing a sum-of-products
combinational logic function and an optional flip-flop
a typical SPLD contains 8-10 macrocells
 Features:
Programming AND array Use or bypass the flip-flop Select clock edge polarity Preset or clear for
the register Complement an output FF is connected to a common clock OE (output enable) signal
also Controls all the three-state buffers FF output is fed back to PAL inputs

Basic Macrocell Logic

CPLD - Complex Programmable Logic Device
CPLD: a collection of PLDs to be connected to each othe rthrough a programmable
switch matrix
 Input/output blocks provide connections to IC pins
 Each I/O pin is driven by a three-state buffer and can be programmed to act as input or
output
 Switch matrix receives inputs from I/O block and directs it to individual microcells
 Selected outputs from microcells are sent to the outputs as needed
 Each PLD typically contains from 8 to 16 microcells.
FPGA – Field-Programmable Gate Array

o Gate array: basic component used in VLSI–consist of a pattern of

gates fabricated in an area of silicon and repeated thousands of
times
o FPGA: an array of hundreds or thousands of logic blocks –
surrounded by programmable input and output blocks– connected
together via programmable interconnections
o A logic block consists of look-up tables, multiplexers, gates, and flip-flops
o Look-up table: a truth table stored in a SRAM and
providing combinational circuit functions for the logic block
o SRAM instead of ROM
o Advantage: the table can be programmed
o Drawback: memory is volatile, reload/reprogram required after
power on again
o Complexity
 PALs, PLAs = 10 - 100 Gate Equivalents
 FPGAs = 100 - 1000(s) of Gate Equivalents