[부록]

CMOS Fabrication Process

edited by 김창욱
CMOS inverter 구조
Mask 설계
Reference List

Lecture notes by S. Meenatchi Sundaram (MIT)

Simple process (+mask position)

Slide notes(slideshare.net) by CSIR in India + α

Classic process (manufacturing condition)

Lecture notes by Sungho Kim, Basic semiconductor manufacturing #8.1 & #8.2 CMOS Process
Summarized process (HKMG case)

Semiconductor Manufacturing Technology(prentice Hall) by M. Quirk & J. Serda

Redrawn/Edited process
※ Body에 전압을
걸어줄 수 있는 contact (GND에 연결)
※ Body에 전압을
걸어줄 수 있는 contact (Vdd에 연결)
Cross-sectional diagram, Top View, Circuit
Process 1/14

4. Develop
Mask 1
(n-well)
3. Exposure (Mask1)

2. PR coating
※ Negative-type

1. Wet Oxidation
Process 2/14

SiO2 Etching (by HF)

Process 3/14

PR strip
Process 4/14

※ 5족 원소
n well formation
(by diffusion)

※ SiO2가 Mask 역할
Process 5/14

Etching (SiO2 제거)

Process 6/14

2. Poly-Si 증착 (by LPCVD)

※ SiH4 or TEOS gas

1. Dry Oxidation
Process 7/14

5. PR strip
4. Etching
Mask 2
(Poly-Si) 3. Develop

2. Exposure (Mask2)

1. PR coating
※ Positive-type

※ 5단계의 기본 photolitho공정을 통해
Poly Si gate 형성
Process 8/14

SiO2 Thermal oxidation

※ SiO2 Protective layer 형성

(ion implantation 공정의 mask가 됨)
Process 9/14

5. PR strip
4. Etching
Mask 3
(n+ diffusion) 3. Develop

2. Exposure (Mask3)

SiO2 1. PR coating
※ Negative -type

※ SiO2 Protective layer 패터닝하여

마스크 역할을 하게 만듬
Process 10/14

Ion Implantation (5족원소)

※ SiO2 Protective layer 와 gate가

막아주는 부분 제외하고 ion doping 됨
Process 11/14

Etching으로
SiO2 protective layer 제거
Process 12/14

Mask 4
(p+ diffusion)

※ 9~11번 프로세스 반복

Ion Implantation (3족원소)

Process 13/14

※ Metal 들어갈 hole을 형성시키는

photolithography

2. PR coating
Mask 5
→Exposure
(contact)
→Develop
→Etching
→PR strip

1. Thermal Oxidation
(Thick SiO2형성)
※ 전체 표면
Process 14/14

Mask 6
(Metal)

2. Photolithography
※ Gate 부분만 open 시킴

1. Al Metal Sputtering
Reference List

Lecture notes by S. Meenatchi Sundaram (MIT)

Simple process (+mask position)

Slide notes(slideshare.net) by CSIR in India + α

Classic process (manufacturing condition)

Lecture notes by Sungho Kim, Basic semiconductor manufacturing #8.1 & #8.2 CMOS Process
Summarized process (HKMG case)

Semiconductor Manufacturing Technology(prentice Hall) by M. Quirk & J. Serda

Redrawn/Edited process
CMOS Process Flow 1/30 ※ Slideshare.net, VLSI Fabrication technology (CSIR in india)

▪ Examples of Simple CMOS Circuits

CMOS Process Flow 2/30
▪ Cross sectional view of final CMOS circuits
CMOS Process Flow 3/30
▪ Pad Oxide(SiO2) 형성 (by Thermal Oxidation)
▪ Pad Nitride(Si3N4) 형성 (by LPCVD)
▪ Photoresist spinning and baking
CMOS Process Flow 4/30
▪ Exposure through Mask#1
▪ Dry Etching of Pad Nitride(Si3N4)
▪ Photoresist remove

Mask #1 Mask #1

※ Posi-PR

MASK #1
CMOS Process Flow 5/30
▪ Isolation (LOCOS(Local oxidation of Silicon) vs STI(Shallow Trench Isolation))
▪ STI ← by trench Dry Etching and HDPCVD
CMOS Process Flow 6/30
▪ Ion implantation for well region (p-type doping)

MASK #2
CMOS Process Flow 7/30
▪ Ion implantation for well region (n-type doping)

MASK #3
CMOS Process Flow 8/30
▪ Implant 영역 원자구조배열 recovery, dopant 확산 및 well 영역 형성 (by Rapid thermal annealing)
CMOS Process Flow 9/30
▪ Ion implantation for channel (p-type doping)

MASK #4
CMOS Process Flow 10/30
▪ Ion implantation for channel (n-type doping)

MASK #5
CMOS Process Flow 11/30
▪ Remove remained Pad oxide (by Buffered Oxide Etcher, dilute HF)
▪ New gate oxide (SiO2) grown ※ High-K oxide는 ALD로 형성
CMOS Process Flow 12/30
▪ Deposition of poly-Si (by LPCVD) for poly-Si gate
CMOS Process Flow 13/30
▪ Mask#6을 이용하여 gate 부분만 남기고 anisotropic etching

MASK #6
CMOS Process Flow 14/30
▪ Low dos ion implantation for source/drain (n-type doping in P well)
→ LDD (lightly doped drain) 구조 형성을 위한 1단계

MASK #7
CMOS Process Flow 15/30
▪ Low dos ion implantation for source/drain (p-type doping in N well)
→ LDD 구조 형성을 위한 1단계

MASK #8
CMOS Process Flow 16/30
▪ SiO2 layer deposition (by LPCVD)
CMOS Process Flow 17/30
▪ Etching of SiO2 layer [Gate 주변에 side-wall spacer 형성]
→ LDD 구조 형성을 위한 2단계
CMOS Process Flow 18/30
▪ Low dos ion implantation for source/drain (n-type doping in P well)
→ LDD 구조 형성을 위한 3단계
(side-wall spacer가 mask 역할을 하여 doping이 안됨(n-유지). 노출된 영역은 두 번 doping되어 n+)

MASK #9
CMOS Process Flow 19/30
▪ Low dos ion implantation for source/drain (p-type doping in N well)
→ LDD 구조 형성을 위한 3단계
(side-wall spacer가 mask 역할을 하여 doping이 안됨(p-유지). 노출된 영역은 두 번 doping되어 p+)

MASK #10
CMOS Process Flow 20/30
▪ Rapid Thermal Annealing에 의해 doping 영역 재정렬
CMOS Process Flow 21/30
▪ Oxide를 etching하여 source/drain 및 gate contact을 open 시킴
CMOS Process Flow 22/30
▪ 반도체-금속 계면의 Silicide (Si-metal 화합물) 형성을 위한 Salicide (Self-aligned Silicide) 공정
→ Ti 등 메탈을 sputtering 공정으로 deposition 함
CMOS Process Flow 23/30
▪ N2분위기 고온에서 Silicide(TiSi2) 와 TiN 형성

TiN TiSi2
CMOS Process Flow 24/30
▪ Mask#11를 이용해서 TiN 제거하여 금속 배선과 연결할 부분 open

MASK #11
CMOS Process Flow 25/30
▪ SiO2 PMD (Pre-metal Dielectric) layer를 형성 (by LPCVD)
CMOS Process Flow 26/30
▪ CMP(Chemical Mechanical Polishing)로 평탄화 작업을 함
CMOS Process Flow 27/30
▪ Mask#12를 이용하여 metal 배선과 contact할 hole 자리를 define 함

MASK #12
CMOS Process Flow 28/30
▪ W 증착前 TiN barrier layer를 증착시킴
▪ W 증착後 CMP 공정으로 평탄화 시킴
CMOS Process Flow 29/30
▪ Al 금속배선을 형성시킴
→ 현재는 Cu배선을 주로 사용함 (Damascene 공법 적용)

Al 배선

MASK #13
CMOS Process Flow 30/30
▪ IMD (Inter-metal Dielectric) layer를 증착하고 via hole을 형성하고 금속배선을 형성하는 과정을 반복함
▪ 맨 마지막 단계로 Si3N4 passivation layer를 형성 시켜 줌

MASK #14,15,16
Reference List

Lecture notes by S. Meenatchi Sundaram (MIT)

Simple process (+mask position)

Slide notes(slideshare.net) by CSIR in India + α

Classic process (manufacturing condition)

Lecture notes by Sungho Kim, Basic semiconductor manufacturing #8.1 & #8.2 CMOS Process
Summarized process (HKMG case)

Semiconductor Manufacturing Technology(prentice Hall) by M. Quirk & J. Serda

Redrawn/Edited process
※ (100)면은 defect가 적고 공정시 단차가 적게 생김

※ TWIN well
※ 채널 보호용
※ PAD Oxide는 channeling 방지용
※ Photolithography 공정 없이 웨이퍼 전체를 균일하게 깍이 줌 (chemical etching)
Reference List

Lecture notes by S. Meenatchi Sundaram (MIT)

Simple process (+mask position)

Slide notes(slideshare.net) by CSIR in India + α

Classic process (manufacturing condition)

Lecture notes by Sungho Kim, Basic semiconductor manufacturing #8.1 & #8.2 CMOS Process
Summarized process (HKMG case)

Semiconductor Manufacturing Technology(prentice Hall) by M. Quirk & J. Serda

Redrawn/Edited process
[A] Poly-Si gate 1/38

(1) Twin Well process

• 산화막 형성: 오염물로부터 Si표면 상부 보호, Implantation 공정 시 Si의 과도한 손상 방지, 주입하는 동안 dopant의 농도조절

PR
SiN3N4
SiO2

Si, (100), P type

[A] Poly-Si gate 2/38

(1) Twin Well process

MASK #1 MASK #1

PR
SiN3N4
SiO2

Si, (100), P type

[A] Poly-Si gate 3/38

(1) Twin Well process

• Implantation 시 높은 전압 (~200KeV)으로 가속시키므로 공유결합 구조가 손상됨 → Wafer를 anneal furnace로 삽입시켜 어닐링 실시

Ion Implantation (P) + Annealing

PR
SiN3N4
SiO2

n-well

Si, (100), P type

[A] Poly-Si gate 4/38

(1) Twin Well process

MASK #2 MASK #2

n-well

Si, (100), P type

[A] Poly-Si gate 5/38

(1) Twin Well process

• Oxide는 channeling 방지용

Ion Implantation (B) + Annealing

n-well p-well

Si, (100), P type

[A] Poly-Si gate 6/38

(2) Shallow Trench Isolation process

Dry etching (with Mask #3)

PR
SiN3N4
SiO2

n-well p-well

Si, (100), P type

[A] Poly-Si gate 7/38

(2) Shallow Trench Isolation process

• Wafer를 고온 산화 furnace속에 삽입시켜 150Å정도의 선형 산화막 형성

Nitride Linear oxide

n-well p-well

Si, (100), P type

[A] Poly-Si gate 8/38

(2) Shallow Trench Isolation process

• 질화막은 CMP 단계 동안 poly-stop 물질로 작용함

Nitride Linear oxide

n-well p-well

Si, (100), P type

[A] Poly-Si gate 9/38

(2) Shallow Trench Isolation process

• LPCVD or HDPCVD

CVD Oxide

n-well p-well

Si, (100), P type

[A] Poly-Si gate 10/38

(2) Shallow Trench Isolation process

• 질화막은 CMP 단계 동안 poly-stop 물질로 작용함

CMP, planarization

Nitride
Oxide

n-well p-well

Si, (100), P type

[A] Poly-Si gate 11/38

(2) Shallow Trench Isolation process

• Nitride 제거

n-well p-well

Si, (100), P type

[A] Poly-Si gate 12/38

(3) Channel Doping process

Ion Implantation (P)

PR

n-well p-well

Si, (100), P type

[A] Poly-Si gate 13/38

(3) Channel Doping process

Ion Implantation (As)

PR

N P

n-well p-well

Si, (100), P type

[A] Poly-Si gate 14/38

(4) Poly-Si Gate Structural Process

• Gate oxide 형성

N P

n-well p-well

Si, (100), P type

[A] Poly-Si gate 15/38

(4) Poly-Si Gate Structural Process

• Poly-Si deposition using LPCVD (SiH4, Silane gas)

Poly-Si

N P

n-well p-well
[A] Poly-Si gate 16/38

(4) Poly-Si Gate Structural Process

• Lithography with Mask #4 (일반적으로 게이트 선폭이 제일 협소하므로 중요한 공정임) PR
※ PR과 Poly-Si 사이
ARC(비반사 코팅) ARC
layer를 형성
시키기도 함 Poly
-Si

Poly-Si PR PR

N P

n-well p-well
[A] Poly-Si gate 17/38

(4) Poly-Si Gate Structural Process

Anisotropic etching

PR PR

N P

n-well p-well
[A] Poly-Si gate 18/38

(5) LDD Implants Process

• LDD (lightly doped drain), Low dos ion implantation for source/drain (n-type doping in P well)

Mask #5
Ion Implantation (P)

PR

N N-
P N-

n-well p-well
[A] Poly-Si gate 19/38

(5) LDD Implants Process

• LDD (lightly doped drain), Low dos ion implantation for source/drain (p-type doping in N well)

Mask #6
Ion Implantation (B)

PR

P-
N P- N-
P N-

n-well p-well
[A] Poly-Si gate 20/38

(5) LDD Implants Process

P-
N P- N-
P N-

n-well p-well
[A] Poly-Si gate 21/38

(6) Sidewall Spacer Formation Process

• SiO2 layer deposition by LPCVD

SiO2

P-
N P- N-
P N-

n-well p-well
[A] Poly-Si gate 22/38

(6) Sidewall Spacer Formation Process

• Etching of SiO2 layer (Etchback)

P-
N P- N-
P N-

n-well p-well
[A] Poly-Si gate 23/38

(7) Source/Drain implant Process

Growth of Screen oxide (10nm) to avoid channeling

P-
N P- N-
P N-

n-well p-well
[A] Poly-Si gate 24/38

(7) Source/Drain implant Process

Mask #7
Ion Implantation (As)

P-
N P- N+
P N+

n-well p-well
[A] Poly-Si gate 25/38

(7) Source/Drain implant Process

Mask #8
Ion Implantation (B)

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 26/38

(7) Source/Drain implant Process

• Rapid Thermal Annealing에 의해 doping 영역 재정렬

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 27/38

(8) Contact Formation Process

• Oxide etching, source/drain 및 gate contact open

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 28/38

(8) Contact Formation Process

• Silicide 형성을 위한 Salicide 공정

Ti deposition by sputtering (typically 100nm)

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 29/38

(8) Contact Formation Process

• At N2 atmosphere, formation of Silicide(TiSi2) and TiN

TiSi2
TiN

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 30/38

(8) Contact Formation Process

• TiN etching

PR
TiN
P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 31/38

(9) Local Interconnect (LI) Process

SiO2 deposition by LPCVD

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 32/38

(9) Local Interconnect (LI) Process

• CMP

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 33/38

(9) Local Interconnect (LI) Process

• SiO2 etching

Mask #9

PR

SiO2

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 34/38

(9) Local Interconnect (LI) Process

• TiN은 W금속이 SiO2로 확산되는 것을 방지 하는 barrier 역할

W deposition by CVD
TiN deposition by Sputtering

W
SiO2

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 35/38

(9) Local Interconnect (LI) Process

• CMP

TIN
W
SiO2

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 36/38

(10) Metal Interconnect Formation Process

• Al deposited on wafer by sputtering and plasma etched

Al

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 37/38

(10) Metal Interconnect Formation Process

• Intermetal dielectric and second level metal are deposited

Intermetal dielectric

Al

P+
N P+ N+
P N+

n-well p-well
[A] Poly-Si gate 38/38

(12) Passivation layer formation Process

• Si3N4 is deposited by PECVD for passivation layer

Si3N4

P+
N P+ N+
P N+

n-well p-well
[B] Metal gate 1/9

Dummy gate deposition : CVD

HfO2
(ALD)

n-well p-well

Si, (100), P type

[B] Metal gate 2/9

Screen oxide

n-well p-well

Si, (100), P type

[B] Metal gate 3/9

LDD doping

p- p- n- n-

n-well p-well

Si, (100), P type

[B] Metal gate 4/9

SiO2

p- p- n- n-

n-well p-well

Si, (100), P type

[B] Metal gate 5/9

Spacer

p- p- n- n-

n-well p-well

Si, (100), P type

[B] Metal gate 6/9

Source/drain : ion implantation

p+ p+ n+ n+

n-well p-well

Si, (100), P type

[B] Metal gate 7/9

Gate area open : dry etch

ILD (inter layer dielectric) deposition : CVD

p+ p+ n+ n+

n-well p-well

Si, (100), P type

[B] Metal gate 8/9

Metal gate deposition : PVD

ILD

p+ p+ n+ n+

n-well p-well

Si, (100), P type

[B] Metal gate 9/9

Via open, Silicide process, Damascene process (Cu)

ILD

p+ p+ n+ n+

n-well p-well

Si, (100), P type