ECEN 449 – Microprocessor System Design

Verilog

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Objectives of this Lecture Unit

• Get a feel for the basics of Verilog

– The focus of this unit will be along two separate but equally relevant
axes
• We will cover the semantics of Verilog and different modeling styles
• Also we will cover syntax issues. For this portion, additional resources
are also provided on the website.
– In general Verilog is quite rich, and therefore, there are many ways to
achieve the same design goal
• We will focus on the syntax that is most common, especially from a
synthesizability point of view.

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Hardware Description Languages (HDLs)

• What is a HDL, why is it useful

• The Verilog HDL
• Modelling a simple circuit in Verilog
– Gate level
– Dataflow
– Procedural
– Synthesizable Verilog
• Testbenches
• Syntax coverage

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Hardware Description Language (HDLs)

• A HDL is a programming language which is tuned to describe

hardware
• HDLs allow us to design and simulate a design at a higher level of
abstraction
– Result = higher designer productivity
• HDLs also have accompanying synthesis tools which allow the
designer to obtain an implementation from HDL code.
– Further improvement in designer productivity
• FPGA based design flows use HDLs heavily!

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Common HDLs

• There are mainly two HDLs in use today

– Verilog HDL
– VHDL
• VHDL is the somewhat more common
– Standard developed by US DoD
– VHDL = (Very High Speed Integrated Circuit) HDL
• We choose Verilog for this class because
– It is easier to use and teach
– Resembles “C” and hence easier to learn.
• Which one is “better”?
– This is the topic of much debate

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Verilog HDL

• Verilog constructs are use defined keywords

– Examples: and, or, wire, input, output
• One important construct is the module
– Modules have inputs and outputs
– Modules can be built up of Verilog primitives or of user defined
submodules.

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A Structural Design - XOR module name

module xor_gate ( out, a, b ); port list

input a, b;
output out;
wire abar, bbar, t1, t2; declarations
Built-in gates
not invA (abar, a); statements
not invB (bbar, b);
a
and and1 (t1, a, bbar); and1 t1
out
and and2 (t2, b, abar); invB or1
or or1 (out, t1, t2); b
and2
t2
endmodule interconnections invA

Instance name
– Composition of primitive gates to form more complex module
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Another Simple Circuit (in Structural Verilog)

module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule

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Structural Verilog

• Just specifies primitive gates and wires

– In other words, the structure of a logical netlist
• Useful if you know exactly what logic you want to generate
– Not useful for large designs, where we want to specify the design at a
higher level of abstraction
• It is crucial to design at a higher level of abstraction in this case, since
structural design would be tedious and error prone
– In such a case, we will describe the circuit at a high level of
abstraction, and let the CAD tools realize the detailed design (by
performing the steps of synthesis, mapping, placement+routing, and
generation of the netlist (in an FPGA, this is the bitgen file)
– In special cases, delay or area-critical sub-blocks can be designed in
structural manner, while the rest of the logic could be at a higher level
of abstraction (typically described in the behavioral fashion).

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Simple Circuit – Comments

• The module starts with module keyword and finishes with

endmodule.
• Internal signals are named with wire.
• Comments follow //
• input and output are ports. These are placed at the start of the
module definition.
• Each statement ends with a semicolon, except endmodule.

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Adding Delays

• To simulate a circuit’s real world behaviour it is important that

propagation delays are included.
• The units of time for the simulation can be specified with
timescale.
– Default is 1ns with precision of 100ps
• Component delays are specified as #(delay)
• BUT REMEMBER – these delays will NOT synthesize.
– Useful only for simulation and verification of your design.

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Simple Circuit with Delay
module
circuit_with_delay Time Input Output
(A,B,C,x,y); (ns) ABC yex
input A,B,C; 0 000 101
output x,y; 0 111 101
wire e; 10 111 001

and #(30) g1(e,A,B); 20 111 001

or #(20) g3(x,e,y); 30 111 010

40 111 010
not #(10) g2(y,C);
50 111 011
endmodule
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Structural Model

• Built-in gate primitives:

and, nand, nor, or, xor, xnor, buf, not, bufif0, bufif1,
notif0, notif1

• Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance name
xor X1(out, in1, in2); 2-input XOR with instance name

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Dataflow modelling
• Another level of abstraction is to model dataflow.
• In dataflow models, signals are continuously assigned values using the assign
keyword.
• assign can be used with Boolean expressions.
– Verilog uses & (and), | (or), ^ (xor) and ~ (not)
• Logic expressions and binary arithmetic are also possible.
assign #10 out = i1 & i2;
• Left hand side must be a net of some kind (scalar or vector), not a register
• Right hand side can be registers, nets.
• Continuous assignments are always active. Execution hard to trace
• They are evaluated whenever a right hand side operand changes value
• Delays (inertial) can be added to represent component delays
• LHS evaluates when there is an event on the RHS (therefore independent of
ordering of assign statements in the code)

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Simple Circuit Boolean Expression

x = A.B + C
y=C

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Dataflow Description of Simple Circuit
//Circuit specified with Boolean
equations
module circuit_bln (x,y,A,B,C);
input A,B,C;
output x,y;
assign x = (A & B) | ~C;
Order does not
assign y = ~C ; matter!
endmodule

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Multiplexor

• Multiplexor is a combinational circuit where an input is chosen by a

select signal.
– Two input mux
– output =A if select =1
– output= B if select =0

A
x
B

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Dataflow description of 2-input Mux

• Conditional operator ?:takes three operands:

condition? true_expression : false_expression

module mux2x1_df (A,B,select,OUT);

input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule

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Behavioural Modelling

• Represents circuits at functional and algorithmic level.

• Use procedural statements similar in concept to procedural
programming languages (e.g. C, Java),
• Behavioural modelling is mostly used to represent sequential
circuits.
• We still specify a module in Verilog with inputs and outputs...
– But inside the module we write code to specify the behavior we want,
NOT what gates (structure) to connect to make it happen
• Why use behavioral models
– For high-level specs to drive logic synthesis tools

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Behavioural Modelling

• Behavioural models place procedural statements in a block after the

always keyword.
• The always keyword takes a list of variables which represent a
trigger condition. The block of statements is executed whenever
the trigger is TRUE.
• The target variables are of type reg. This type retains its value
until a new value is assigned.
• Behavioral models may also have initial blocks.
– The block executes only once
– By default, starts at time 0
– Often used for initialization

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Always Blocks
• Module may have any number of always blocks
• Allow us to represent parallelism in hardware.

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Behavioral Description of an XOR

module xorB(X, Y, Z);

input X, Y;
output Z;
reg Z;
always @ (X or Y)
Z = X ^ Y;
endmodule
• Unusual parts of above Verilog
– “always @ (X or Y)” => whenever X or Y changes, do
the following statement
– “reg” is only type of behavioral data that can be changed in
assignment, so must redeclare Z
– Default is single bit data types: X, Y, Z

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Behavioural description of 2-input Mux

module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule

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 Behavioral example

• Behavioral edge-triggered DFF

implem
module dff(Q, D, Clk);
output Q;
input D, Clk;

reg Q;
wire D, Clk;

always @(posedge Clk)

Q = D;

endmodule

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Another Behavioral Example

always @(res or posedge clk) begin

res if (res) begin
a Y = 0;
b Y W = 0;
end
else begin
c W Y = a & b;
W = ~c;
clk end
end

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 Blocking Assignments

• Represented with an = sign

– All blocking assignments are executed in sequence
module dummy;
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x = 0; y = 1; z = 1;
count = 0;
reg_a = 16'b0;
reg_b = reg_a;
reg_a[2] = #15 1;
reg_b[15:13] = #10 {x, y, z};
count = count + 1;
end

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 Non-blocking Assignments

• Represented with a <= sign

– All non-blocking assignments are executed in parallel
– Try not module
to mix with blocking assignments
dummy;
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x = 0; y = 1; z = 1;
count = 0;
reg_a[2] <= #15 1;
reg_b[15:13] <= #10 {x, y, z};
count = count + 1;
end

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Blocking or Non-blocking???

• Blocking is harder to reason about.

• Also hardware does not work in a blocking (sequential way)
• So generally you should use non-blocking assignments
– Easier to synthesize
– Models parallelism which is inherent in the hardware

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Two kinds of Delays in Verilog
• Inertial Delay – consider the
statement
assign #4 x = z;
– It’s delay behavior is called “inertial”
delay
– Applicable for gate level primitives
and continuous assignments z
0 9 10 19
• Transport delay – consider the x
statement 4 23

always @(z) y
4 13 14 23
y <= #4 z;
– Its delay is called “transport” delay
– Applicable in non-blocking
assignments

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Delving Deeper

• So far, we saw how some sample circuits are represented in the

three styles
• In the next part of this lecture unit, we will talk about
– Logic values in Verilog
– How to represent hierarchical designs
– Testbenches
– How to represent sequential logic
– Synthesizability Tips
– Syntax examples (will not go over in class in any detail, this portion
of the notes is for your reference)

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Four-Valued Logic
• Verilog Logic Values
– The underlying data representation allows for any bit to have one of
four values
– 1, 0, x (unknown), z (high impedance)
– x — one of: 1, 0, z, or in the state of change
– z — the high impedance output of a tri-state gate.
• What basis do these have in reality?
– z … An output is high impedance. Tri-stated outputs are a real
electrical affect.
– x … not a real value. There is no real gate that drives an x on to a
wire. x is used as a debugging aid. x means the simulator can’t
determine the answer and so maybe you should worry! All values
in a simulation start as x.
• Verilog keeps track of more values than these in some situations.
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Four-Valued Logic
• Logic with multi-level logic values
– Logic with these four values make sense
• Nand anything with a 0, and you get a 1. This includes having an x or z
on the other input. That’s the nature of the nand gate
• Nand two x’s and you get an x — makes sense!
– Note: z treated as an x on input. Their rows and columns are the same
– If you forget to connect an input … it will be seen as an z.
– At the start of simulation, everything is an x.
Input B A
B
Nand 0 1 x z
0 1 1 1 1 A 4-valued truth table for a
Input A

1 1 0 x x Nand gate with two inputs

x 1 x x x
z 1 x x x

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How to Represent Hierarchy in your Design
• First write the modules for each block of the hierarchy
– Then wire them up (next page)

module B1(a, b, c);

………………..
endmodule B1 B2
module B2(a, b, c, d);
……………….. B3
endmodule
module B3(x, y, z);
………………..
endmodule

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Port Mapping (Connecting things up)
module B1(q, w, e, f);
input q, w;
input [3:0] e;
Module B1 declared
output [1:0] f;
……………….
w q
endmodule
q w f c
B1
a e
module top(a,b,c,d);
…….
B1 b1(w, q, a, c); Module B1 instantiated,
........ instance is called myinst
endmodule in this case

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Example (Dataflow, with hierarchy)

A S
Half module half_adder(S, C, A, B);
Half output S, C;
B Adder
Adder C
input A, B;

wire S, C, A, B;
A
S assign S = A ^ B;
B assign C = A & B;
C
endmodule

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 Creating a Full Adder using Half Adder instances
in1 A Half S I1 A Half S sum
Half Half
Adder
Adder11 Adder
Adder
in2 B C I2 B C I3
ha1
ha1 ha2
ha2 cout

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule

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Hierarchical Names

ha2.A

in1 A Half S I1 A Half S sum

Half Half
Adder
Adder11 Adder
Adder
in2 B C I2 B C I3
ha1
ha1 ha2
ha2 cout

cin

Remember to use instance names,

not module names

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Verification

• Use testbench to verify your design

– Special Verilog file for simulating and testing your design
– Instantiates the module to be tested
– Contains code to apply stimulus to the module under test, and monitor
the correctness of the response

Stimulus Response
Test-Bench & &
Control Signal Verification

Module under Test

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Sample Testbench
module top_test;
wire [1:0] t_out; // Top’s signals
reg [3:0] t_in;
reg clk;

top inst(t_out, t_in, clk); // Top’s instance

initial begin // Generate clock

clk = 0;
forever #10 clk = ~clk;
end

initial begin // Generate remaining inputs

$monitor($time, " %b -> %b", t_in, t_out);
#5 t_in = 4'b0101;
#20 t_in = 4'b1110;
#20 t_in[0] = 1;
#300 $finish;
end

endmodule

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Sequential Logic
//Parallel to Serial converter
module ParToSer(LD, X, out, CLK);
input [3:0] X;
input LD, CLK;
output out;
reg out;
reg [3:0] Q; • Notes:
assign out = Q[0];
– “always @ (posedge CLK)” forces Q
always @ (posedge CLK)
register to be rewritten every
if (LD) Q=X;
simulation cycle.
else Q = Q>>1;
endmodule // mux2 – “>>” operator does right shift (shifts
in a zero on the left).
module FF (CLK,Q,D); – Shifts on non-reg variables can be
input D, CLK; done with concatenation:
output Q; reg Q; wire [3:0] A, B;
always @ (posedge CLK) Q=D; assign B = {1’b0, A[3:1]}
endmodule // FF
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Sequential Logic – another example
module mealy (A, CLK, Z);
• Notes:
input A, CLK;
output Z; – If we have a state machine updating
reg Z;
on a rising clock edge, then we
always @(posedge CLK)
Pstate = Nstate; // synchronous part create the always block (triggered
always @(Pstate or A) begin: COMBINPART
case (Pstate) on the posedge of clock).
ST0:
if(A)
begin
– Also we write the state machine
Z=1;
Nstate = ST3;
behavior as a case statement.
end
else
• For example if we are in state ST0,
Z=0; and A is 1, then we move to state
ST1: ST3 in the next clock.
if(A)
begin
Z=0;
– This kind of code for a state
end
Nstate = ST2;
machine is very similar to the state
else
Z=0;
transition diagram based behavior.
<ETC><ETC>
endcase
Hence easy to write.
end
endmodule

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Synthesizability Tips

• If you want to synthesize your Verilog code, here are some tips
– Do not use delays in your code
– Watch for blocking and non-blocking assignments (next slide)
– Watch out for complete assignments (2 slides after next)

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Blocking and Non-blocking

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 “Complete” Assignments

• If an always block executes, and a variable is not assigned

– Variable keeps its old value (this needs state!!)
– Hence latch is inserted (inferred memory)
– This is usually not what you want: dangerous for the novice!
• So to aviod this, any variable assigned in an always block should
be assigned for any (and every!) execution of the block

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Incomplete Triggers

• Leaving out an input trigger usually results in a sequential circuit

• Example: The output of this “and” gate depends on the input
history (a latch will be inferred on in2).
module and_gate (out, in1, in2);
input in1, in2;
output out;
reg out;

always @(in1) begin

out = in1 & in2;
end

endmodule

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Some Verilog Syntax Notes for Your Reference..

• You may find the following slides handy as a partial Verilog

reference.
– It is not meant to be a complete reference – see the resources on the
class website for more detailed references.
– It is meant to help you with the syntax for common Verilog
constructs.

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User Identifiers

• Formed from {[A-Z], [a-z], [0-9], _, $}, but ..

• .. can’t begin with $ or [0-9]
– myidentifier 
– m_y_identifier 
– 3my_identifier 
– $my_identifier 
– _myidentifier$ 
• Case sensitivity
– myid ≠ Myid

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Comments

• // The rest of the line is a comment

• /* Multiple line
comment */

• /* Nesting /* comments */ do NOT work */

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Numbers in Verilog (i)

<size>’<radix> <value>

No
Noof of Binary
Binary →
→bbor
orBB Consecutive chars
bits → Consecutive chars
bits Octal
Octal →ooor
orOO 0-f,
0-f,x,x,zz
Decimal
Decimal →
→ddor
orDD
Hexadecimal→
Hexadecimal →hhor
orHH

– 8’h ax = 1010xxxx
– 12’o 3zx7 = 011zzzxxx111

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Numbers in Verilog (ii)

• You can insert “_” for readability

– 12’b 000_111_010_100
– 12’b 000111010100
– 12’o 07_24 Represent the same number
• Bit extension
– MS bit = 0, x or z ⇒ extend this
• 4’b x1 = 4’b xx_x1
– MS bit = 1 ⇒ zero extension
• 4’b 1x = 4’b 00_1x

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Numbers in Verilog (iii)

• If size is ommitted it
– is inferred from the value or
– takes the simulation specific number of bits or
– takes the machine specific number of bits

• If radix is ommitted too .. decimal is assumed

– 15 = <size>’d 15

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Nets (i)

• Can be thought as hardware wires driven by logic

• Equal z when unconnected
• Various types of nets
– wire
– wand (wired-AND)
– wor (wired-OR)
– tri (tri-state)
• In following examples: Y is evaluated, automatically,
every time A or B changes

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Nets (ii)
A wire Y; // declaration
Y
B assign Y = A & B;

wand Y; // declaration
assign Y = A;
A assign Y = B;
Y
B
wor Y; // declaration
assign Y = A;
assign Y = B;

dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

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Registers
• Variables that store values
• Do not represent real hardware but ..
• .. real hardware can be implemented with registers
• Only one type: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
• Register values are updated explicitly!!

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Vectors
• Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
• Left number is MS bit
• Slice management
busC = busA[2:1]; ⇔ busC[1] = busA[2];
busC[0] = busA[1];
• Vector assignment (by position!!)
busB[1] = busA[3];
busB[2] = busA[2];
busB = busA; ⇔
busB[3] = busA[1];
busB[4] = busA[0];

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Integer & Real Data Types

• Declaration
integer i, k;
real r;
• Use as registers (inside procedures)
i = 1; // assignments occur inside procedure
r = 2.9;
k = r; // k is rounded to 3
• Integers are not initialized!!
• Reals are initialized to 0.0

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Time Data Type

• Special data type for simulation time measuring

• Declaration
time my_time;

• Use inside procedure

my_time = $time; // get current sim time

• Simulation runs at simulation time, not real time

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Arrays (i)
• Syntax
integer count[1:5]; // 5 integers
reg var[-15:16]; // 32 1-bit regs
reg [7:0] mem[0:1023]; // 1024 8-bit regs
• Accessing array elements
– Entire element: mem[10] = 8’b 10101010;
– Element subfield (needs temp storage):
reg [7:0] temp;
..
temp = mem[10];
var[6] = temp[2];
• Concatenating bits/vectors into a vector
– e.g., sign extend
– B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
– B[7:0] = {3{A[3]}, A[3:0]};
• Style: Use a[7:0] = b[7:0] + c;
Not: a = b + c; // need to look at declaration

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Arrays (ii)

• Limitation: Cannot access array subfield or entire array at once

var[2:9] = ???; // WRONG!!
var = ???; // WRONG!!

• No multi-dimentional arrays
reg var[1:10] [1:100]; // WRONG!!

• Arrays don’t work for the Real data type

real r[1:10]; // WRONG !!

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Strings
• Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated

• Escaped chars:
– \n newline
– \t tab
– %% %
– \\ \
– \“ “

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Logical Operators

• && → logical AND

• || → logical OR
• ! → logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x
• Result is ONE bit value: 0, 1 or x
A = 6; A && B → 1 && 0 → 0
B = 0; A || !B → 1 || 1 → 1
C = x; C || B → x || 0 → x

but
butC&&B=0
C&&B=0

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Bitwise Operators (i)
• & → bitwise AND
• | → bitwise OR
• ~ → bitwise NOT
• ^ → bitwise XOR
• ~^ or ^~ → bitwise XNOR

• Operation on bit by bit basis for bitwise operators.

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Bitwise Operators (ii)

c = ~a; c = a & b;

a = 4’b1010;
b = 4’b1100;

c = a ^ b;

a = 4’b1010;
b = 2’b11;

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Reduction Operators

• & → AND
• | → OR
• ^ → XOR
• ~& → NAND
• ~| → NOR
• ~^ or ^~ → XNOR

• One multi-bit operand → One single-bit result

a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

• If A = ‘b0110, and B = ‘b0100 then |B=1, &B=0, ~^A=1

• If C=4’b01x0, then ^C=x.

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Shift Operators
• >> → shift right
• << → shift left

• Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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Concatenation Operator

• {op1, op2, ..} → concatenates op1, op2, .. to single number

• Operands must be sized !!
reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
• Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101

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Relational Operators

• > → greater than

• < → less than
• >= → greater or equal than
• <= → less or equal than

• Result is one bit value: 0, 1 or x

1 > 0 →1
’b1x1 <= 0 →x
10 < z →x

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Equality Operators

• == → logical equality
Return 0, 1 or x
• != → logical inequality
• === → case equality
• !== → case inequality Return 0 or 1

– 4’b 1z0x == 4’b 1z0x →x

– 4’b 1z0x != 4’b 1z0x →x
– 4’b 1z0x === 4’b 1z0x → 1
– 4’b 1z0x !== 4’b 1z0x → 0

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Conditional Operator
• cond_expr ? true_expr : false_expr

• Like a 2-to-1 mux ..

A
1
Y
B Y = (sel)? A : B;
0
sel

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Arithmetic Operators (i)

• +, -, *, /, %

• If any operand is x the result is x

• Negative registers:
– regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524

regA/3 evaluates to 21861

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Arithmetic Operators (ii)

• Negative integers:
– can be assigned negative values
– different treatment depending on base specification or not
reg [15:0] regA;
integer intA;
..
intA = -12/3; // evaluates to -4 (no base spec)
intA = -’d12/3; // evaluates to 1431655761 (base spec)

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Verilog Operators

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Operator Precedence

Use parentheses to
enforce your
priority

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Verilog Variables

• wire
– Variable used simply to connect components together
• reg
– Variable that saves a value as part of a behavioral description
– Usually corresponds to a wire in the circuit
– Is NOT necessarily a register in the circuit
• usage:
– Don’t confuse reg assignments with the combinational
continuous assign statement!
– Reg should only be used with always blocks (sequential logic,
to be presented …)

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Verilog Module

• Corresponds to a circuit component

– “Parameter list” is the list of external connections, aka “ports”
– Ports are declared “input”, “output” or “inout”
• inout ports used on tri-state buses
– Port declarations imply that the variables are wires
module name ports

module full_addr (A, B, Cin, S, Cout);

input A, B, Cin;
output S, Cout; inputs/outputs

assign {Cout, S} = A + B + Cin;

endmodule

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Verilog Continuous Assignment
• Assignment is continuously evaluated
• assign corresponds to a connection or a simple component
with the described function
• Target is NEVER a reg variable
• Dataflow style
use of Boolean operators
(~ for bit-wise, ! for logical negation)
assign A = X | (Y & ~Z);
bits can take on four values
assign B[3:0] = 4'b01XX; (0, 1, X, Z)

assign C[15:0] = 4'h00ff; variables can be n-bits wide

(MSB:LSB)
assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;
use of arithmetic operator
multiple assignment (concatenation)
delay of performing computation, only used by simulator, not synthesis

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Verilog if

• Same as C if statement
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel == 2’b00) Y = A;
else if (sel == 2’b01) Y = B;
else if (sel == 2’b10) Y = C;
else if (sel == 2’b11) Y = D;

endmodule

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Verilog if
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel[0] == 0)
if (sel[1] == 0) Y = A;
else Y = B;
else
if (sel[1] == 0) Y = C;
else Y = D;
endmodule

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Verilog case

• Sequential execution of cases

– Only first case that matches is executed (no break)
– Default case can be used
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
case (sel)
2’b00: Y = A;
2’b01: Y = B; Conditions tested in
2’b10: Y = C; top to bottom order
2’b11: Y = D;
endcase
endmodule

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Verilog case
• Without the default case, this example would create a latch for Y
• Assigning X to a variable means synthesis is free to assign any value
// Simple binary encoder (input is 1-hot)
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (A)
8’b00000001: Y = 0;
8’b00000010: Y = 1;
8’b00000100: Y = 2;
8’b00001000: Y = 3;
8’b00010000: Y = 4;
8’b00100000: Y = 5;
8’b01000000: Y = 6;
8’b10000000: Y = 7;
default: Y = 3’bX; // Don’t care when input is not 1-hot
endcase
endmodule

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Verilog case (cont)
• Cases are executed sequentially
– The following implements a priority encoder
// Priority encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (1’b1)
A[0]: Y = 0;
A[1]: Y = 1;
A[2]: Y = 2;
A[3]: Y = 3;
A[4]: Y = 4;
A[5]: Y = 5;
A[6]: Y = 6;
A[7]: Y = 7;
default: Y = 3’bX; // Don’t care when input is all 0’s
endcase
endmodule

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Parallel case
• A priority encoder is more expensive than a simple encoder
– If we know the input is 1-hot, we can tell the synthesis tools
– “parallel-case” pragma says the order of cases does not matter
// simple encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (1’b1) // synthesis parallel-case
A[0]: Y = 0;
A[1]: Y = 1;
A[2]: Y = 2;
A[3]: Y = 3;
A[4]: Y = 4;
A[5]: Y = 5;
A[6]: Y = 6;
A[7]: Y = 7;
default: Y = 3’bX; // Don’t care when input is all 0’s
endcase
endmodule
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Verilog casex
• Like case, but cases can include ‘X’
– X bits not used when evaluating the cases
– In other words, you don’t care about those bits!

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casex Example
// Priority encoder
module encode (A, valid, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
output valid; // Asserted when an input is not all 0’s
reg [2:0] Y; // target of assignment
reg valid;

always @(A) begin

valid = 1;
casex (A)
8’bXXXXXXX1: Y = 0;
8’bXXXXXX10: Y = 1;
8’bXXXXX100: Y = 2;
8’bXXXX1000: Y = 3;
8’bXXX10000: Y = 4;
8’bXX100000: Y = 5;
8’bX1000000: Y = 6;
8’b10000000: Y = 7;
default: begin
valid = 0;
Y = 3’bX; // Don’t care when input is all 0’s
end
endcase
end
endmodule

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Verilog for
• for is similar to C
• for statement is executed at compile time (like macro expansion)
– Useful for parameterized designs.
// simple encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

integer i; // Temporary variables for program only

reg [7:0] test;

always @(A) begin

test = 8b’00000001;
Y = 3’bX;
for (i = 0; i < 8; i = i + 1) begin
if (A == test) Y = N;
test = test << 1;
end
end
endmodule

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Verilog while/repeat/forever

• while (expression) statement

– Execute statement while expression is true
• repeat (expression) statement
– Execute statement a fixed number of times
• forever statement
– Execute statement forever

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full-case and parallel-case

• // synthesis parallel_case
– Tells compiler that ordering of cases is not important
– That is, cases do not overlap
• e. g., state machine - can’t be in multiple states
– Gives cheaper implementation

• // synthesis full_case
– Tells compiler that cases left out can be treated as don’t cares
– Avoids incomplete specification and resulting latches

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