CSE DEPARTMENT - BCS

BCS303 OPERATING SYSTEMS II Year – III Sem (2024

(2024-25 ODD)

BCS
BCS303 OPERATING SYSTEMS
Module
Module-4: MEMORY MANAGEMENT
Ch. 8. Memory Management: Memory management strategies: Background; Swapping; Contiguous
memory allocation; Paging; Structure of page table; Segmentation.
Ch. 9. Virtual Memory Management:
Management Background; Demand and paging; Copy-on-write;
Copy Page
replacement; Allocation of frames; Thrashing.
Textbook 1: Chapter -8 (8.1-8.6),
8.6), 9 (9.1-9.6)
(9.1
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Chapter 8. Memory Management
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Background
 Program must be brought (from disk) into memory and placed within a process for it to be run
 Main memory and registers are only storage CPU can access directly
 Memory unit only sees a stream of addresses + read requests, or address + data and write
requests
 Register access in one CPU clock (or less)
 Main memory can take many cycles
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation
Base and Limit Registers
 A pair of base and limit registers define the logical address space
space.
 Hardware Address Protection with Base and Limit Registers.
Registers

Address Binding
 Inconvenient to have first user process physical address always at 0000
o How can it not be?
 Further, addresses represented in different ways at different stages of a program’s life
o Source code addresses usually symbolic
o Compiled code addresses bind to relocatable addresses
 i.e. “14 bytes from beginning of this module”
o Linker or loader will bind relocatable addresses to absolute addresses
 i.e. 74014
o Each binding maps one address space to another
Binding of Instructions and Data to Memory
 Address binding of instructions and data to memory addresses can happen at three different stages
 Compile time:: If memory location known a priori, absolute code can be generated; must recompile
code if starting location changes
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

 Load time: Must generate relocatable code if memory location is not known at compile time
 Execution time: Binding delayed until run time if the process can be moved during its execution
from one memory segment to another
o Need hardware support for address maps (e.g., base and limit registers)
Multistep Processing of a User Program

Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a separate physical address space is central
to proper memory management
 Logical address – generated by the CPU; also referred to as virtual address
 Physical address – address seen by the memory unit
 Logical and physical addresses are the same in compile-time and load-time address-binding
schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme
 Logical address space is the set of all logical addresses generated by a program
 Physical address space is the set of all physical addresses generated by a program
Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical address
 To start, consider simple scheme where the value in the relocation register is added to every
address generated by a user process at the time it is sent to memory
o Base register now called relocation register
o MS-DOS on Intel 80x86 used 4 relocation registers
 The user program deals with logical addresses; it never sees the real physical addresses
o Execution-time binding occurs when reference is made to location in memory
o Logical address bound to physical addresses
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

Dynamic relocation using relocation register

Dynamic Loading
 Routine is not loaded until it is called
 Better memory-space utilization; unused routine is never loaded
 All routines kept on disk in relocatable load format
 Useful when large amounts of code are needed to handle infrequently occurring cases
 No special support from the operating system is required
o Implemented through program design
o OS can help by providing libraries to implement dynamic loading
Dynamic Linking
 Static linking – system libraries and program code combined by the loader into the binary program
image
 Dynamic linking –linking postponed until execution time
 Small piece of code, stub, used to locate the appropriate memory-resident library routine
 Stub replaces itself with the address of the routine, and executes the routine
 Operating system checks if routine is in processes’ memory address
o If not in address space, add to address space
 Dynamic linking is particularly useful for libraries
 System also known as shared libraries
 Consider applicability to patching system libraries
o Versioning may be needed
Swapping
 A process can be swapped temporarily out of memory to a backing store, and then brought back
into memory for continued execution
 Total physical memory space of processes can exceed
physical memory
 Backing store – fast disk large enough to
accommodate copies of all memory images for all
users; must provide direct access to these memory
images
 Roll out, roll in – swapping variant used for priority-
based scheduling algorithms; lower-priority process is
swapped out so higher-priority process can be loaded
and executed
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

 Major part of swap time is transfer time; total transfer time is directly proportional to the amount
of memory swapped
 System maintains a ready queue of ready-to-run processes which have memory images on disk
 Does the swapped out process need to swap back in to same physical addresses?
 Depends on address binding method
o Plus consider pending I/O to / from process memory space
 Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)
 Swapping normally disabled
o Started if more than threshold amount of memory allocated
o Disabled again once memory demand reduced below threshold
Context Switch Time including Swapping
 If next processes to be put on CPU is not in memory, need to swap out a process and swap in target
process
 Context switch time can then be very high
 100MB process swapping to hard disk with transfer rate of 50MB/sec
o Plus disk latency of 8 ms
o Swap out time of 2008 ms
o Plus swap in of same sized process
o Total context switch swapping component time of 4016ms (> 4 seconds)
 Can reduce if reduce size of memory swapped – by knowing how much memory really being used
o System calls to inform OS of memory use via request memory and release memory
Contiguous Allocation
 Main memory usually into two partitions:
o Resident operating system, usually held in low memory with interrupt vector
o User processes then held in high memory
o Each process contained in single contiguous section of memory
 Relocation registers used to protect user processes from each other, and from changing operating-
system code and data
o Base register contains value of smallest physical address
o Limit register contains range of logical addresses – each logical address must be less than the
limit register
o MMU maps logical address dynamically
o Can then allow actions such as kernel code being transient and kernel changing size
Hardware Support for Relocation and
Limit Registers

 Multiple-partition allocation
o Degree of multiprogramming limited
by number of partitions
o Hole – block of available memory;
holes of various size are scattered
throughout memory
o When a process arrives, it is allocated memory from a hole large enough to accommodate it
o Process exiting frees its partition, adjacent free partitions combined
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

o Operating system maintains information about:

a) allocated partitions b) free
f partitions (hole)

Dynamic Storage
Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
 First-fit:: Allocate the first hole that is big enough
 Best-fit:: Allocate the smallest hole that is big enough; must search entire list, unless ordered by
size
o Produces the smallest leftover hole
 Worst-fit:: Allocate the largest hole; must also search entire list
o Produces the largest leftover hole
Note: First-fit and best-fit
fit better than worst
worst-fit
fit in terms of speed and storage utilization
Fragmentation
 External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous
 Internal Fragmentation – allocated memory may be slightly larger than requested memory; this
size difference is memory internal to a partition, but not being used
 First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
o 1/3 may be unusable -> 50 50-percent rule
 Reduce external fragmentation by compaction
o Shuffle memory contents to place all free memory together in one large block
o Compaction is possible only if relocation is dynamic, and is done at execution time
o I/O problem
 Latch job in memory while hile it is involved in I/O
 Do I/O only into OS buffers
 Now consider that backing store has same fragmentation problems
Paging
 Physical address space of a process can be noncontiguous; process is allocated physical memory
whenever the latter is available
 Divide physical memory into fixed
fixed-sized blocks called frames
o Size is power of 2, between 512 bytes and 16 Mbytes
 Divide logical memory into blocks of same size called pages
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and load program
 Set up a page table to translate logical to physical addresses
 Backing store likewise split into pages
 Still have Internal fragmentation
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

Address Translation Scheme

Address generated by CPU is divided into
into:
 Page number (p) – used as an index into a page table which contains base address of each page in
physical memory
 Page offset (d) – combined with base address to define the physical memory address that is sent to
the memory unit

 For given logical address space 2m and page size 2n

Paging Hardware

Paging Model of Logical and Physical Memory

Paging Example
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

n=2 and m=4 32-byte memory and 4-byte pages

 Calculating internal fragmentation

o Page size = 2,048 bytes
o Process size = 72,766 bytes
o 35 pages + 1,086 bytes
o Internal fragmentation of 2,048 - 1,086 = 962 bytes
o Worst case fragmentation = 1 frame – 1 byte
o On average fragmentation = 1 / 2 frame size
o So small frame sizes desirable?
o But each page table entry takes memory to track
o Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
 Process view and physical memory now very different
 By implementation process can only access its own memory
Free Frames

Before allocation
After allocation
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

Implementation of Page Table

 Page table is kept in main memory
o Page-table
table base register (PTBR) points to the page table
o Page-table
table length register (PTLR) indicates size of the page table
 In this scheme every data/instruction access requires two memory accesses (1- (1 page table, 1- for
the data / instruction)
 The two memory access problem can be solved by the use of a special fast fast-lookup
lookup hardware cache
called associative memory or translation look
look-aside buffers (TLBs)
 Some TLBs store address-spacespace identifiers (ASIDs) in each TLB entry – uniquely identifies each
process to provide address-space
space protection for that process
o Otherwise need to flush at every context switch
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access next time
o Replacement
placement policies must be considered
o Some entries can be wired down for permanent fast access

Associative Memory
o Associative memory – parallel search

o
o Address translation (p, d)
o If p is in associative register, get frame # out
o Otherwise get frame # from page table in memory

Paging Hardware With TLB

Effective Access Time

 Associative Lookup =  time unit
o Can be < 10% of memory access time
 Hit ratio = 
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

o Hit ratio – percentage of times that a page number is found in the associative registers; ratio
related to number of associative registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 Effective Access Time (EAT) = (1 + )  + (2 + )(1 – ) = 2 +  – 
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
o EAT = 0.80 x 120 + 0.20 x 220 = 140ns
 Consider slower memory but better hit ratio ->  = 98%,  = 20ns for TLB search, 140ns for
memory access EAT = 0.98 x 160 + 0.02 x 300 = 162.8ns

Memory Protection
 Memory protection implemented by associating protection bit with each frame to indicate if read-
only or read-write access is allowed
o Can also add more bits to indicate page execute-only, and so on
 Valid-invalid bit attached to each entry in the page table:
o “valid” indicates that the associated page is in the process’ logical address space, and is thus a
legal page
o “invalid” indicates that the page is not in the process’ logical address space
o Or use PTLR
 Any violations result in a trap to the kernel

Valid (v) or Invalid (i) Bit in a Page Table

Shared Pages
 Shared code : One copy of read-only (reentrant) code shared among processes (i.e., text editors,
compilers, window systems)
 Similar to multiple threads sharing the same process space
 Also useful for interprocess communication if sharing of read-write pages is allowed
 Private code and data
 Each process keeps a separate copy of the code and data
 The pages for the private code and data can appear anywhere in the logical address space
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

Two-Level Page-Table Scheme

Address-Translation Scheme

64-bit Logical Address Space

 Even two-level paging scheme not sufficient
 If page size is 4 KB (212)
o Then page table has 252 entries
o If two level scheme, inner page tables could be 210 4-byte entries
o Address would look like
o Outer page table has 242 entries or 244 bytes
o One solution is to add a 2nd outer page table
o But in the following example the 2nd outer page table is still 234 bytes in size
o And possibly 4 memory access to get to one physical memory location

Three-level Paging Scheme

 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

Hashed Page Tables

 Common in address spaces > 32 bits
 The virtual page number is hashed into a page table
o This page table contains a chain of elements hashing to the same location
 Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a
pointer to the next element
 Virtual page numbers are compared in this chain searching for a match
o If a match is found, the corresponding physical frame is extracted

Inverted Page Table

 Rather than each process having a page table
and keeping track of all possible logical pages,
track all physical pages
 One entry for each real page of memory
 Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page
 Decreases memory needed to store each page
table, but increases time needed to search the
table when a page reference occurs
 Use hash table to limit the search to one — or
at most a few — page-table entries
o TLB can accelerate access
 But how to implement shared memory?
o One mapping of a virtual address to the shared physical address
Segmentation
 Memory-management scheme that supports user view of
memory
 A program is a collection of segments
 A segment is a logical unit such as: main program, procedure,
function, method, object, local variables, global variables,
common block, stack, symbol table, arrays
User’s View of a Program
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

Logical View of Segmentation

Segmentation Architecture
 Logical address consists of a two tuple: <segment-number, offset>,
 Segment table – maps two--dimensional
physical addresses; each table entry has:
 base – contains the starting physical address
where the segments reside in memory
 limit – specifies the length of the segment
 Segment-table base register er (STBR) points
to the segment table’s location in memory
 Segment-table
table length register (STLR)
indicates number of segments used by a
program; segment number s is legal if s <
STLR
 Protection With each entry in segment table
associate:
o validation bit = 0  illegal segment , read/write/execute privileges
 Protection bits associated with segments; code sharing occurs at segment level
 Since segments vary in length, memory allocation is a dynamic storage
storage-allocation
allocation problem
 A segmentation example is shown in the following diagram
Example of Segmentation

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 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

9. Virtual Memory Management

Background; Demand paging; Copy-on-write; Page replacement; Allocation of frames; Thrashing
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Background
 Code needs to be in memory to execute, but entire program rarely used
o Error code, unusual routines, large data structures
 Entire program code not needed at same time
 Consider ability to execute partially-loaded program
o Program no longer constrained by limits of physical memory
o Program and programs could be larger than physical memory
 Virtual memory – separation of user logical memory from physical memory
o Only part of the program needs to be in memory for execution
o Logical address space can therefore be much larger than physical address space
o Allows address spaces to be shared by several processes
o Allows for more efficient process creation
o More programs running concurrently
o Less I/O needed to load or swap processes
 Virtual memory can be implemented via: Demand paging, Demand segmentation
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Virtual Memory That is Larger Than Physical Memory Virtual-address Space

 Enables sparse address spaces with holes left for growth, dynamically linked libraries, etc
 System libraries shared via mapping into virtual address space
 Shared memory by mapping pages read-write into virtual address space
 Pages can be shared during fork(), speeding process creation
Shared Library Using Virtual Memory
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

Demand Paging
 Could bring entire process into memory at load time Or bring a page into memory only when it is
needed
o Less I/O needed, no unnecessary I/O , Less memory needed, Faster response,
response More users
 Page is needed  reference to it.. invalid reference  abort. not-in-memory  bring to memory
 Lazy swapper – never swaps a page into memory unless page will be needed - Swapper that deals
with pages is a pager
Transfer of a Paged Memory to Contiguous Disk Space

Valid-Invalid Bit
 With each page table entry a valid valid–invalid bit is associated
(v  in-memory – memory resident resident, i  not-in-memory)
 Initially valid–invalid bit is set to i on all entries
 Example
ample of a page table snapshot:
 During address translation, if validvalid–invalid bit in page table entry
is I  page fault
Page Table When Some Pages are not in Main Memory
 CSE DEPARTMENT - BCS
BCS303 OPERATING SYSTEMS II Year – III Sem (2024
(2024-25 ODD)

Page Fault
 If there a reference to a page, first reference to that page will trap to operating system: page fault.
 Operating system looks at another table to decide: Invalid reference  abort, Just not in memory
 Get empty frame
 Swap page into frame via scheduled disk operation
 Reset tables to indicate page now in memory
Set validation bit = v
 Restart the instruction that caused the page fault
Aspects of Demand Paging
 Extreme case – start process with no pages in memory
 OS sets instruction pointer to first instruction of process, non
non-memory-resident ->
- page fault
 And for every other process pages on first access : Pure demand paging
 Actually, a given instruction could access multiple pages -> multiple page faults
 Pain decreased because of locality of reference
 Hardware support needed for demand paging
 Page table with valid / invalid bit
 Secondary memory (swap device with swap space)
 Instruction restart
Instruction Restart
 Consider an instruction that could access several different locations
o block move
o auto increment/decrement location
o Restart the whole operation?
 What if source and destination overlap?
Steps in Handling a Page Fault

Performance of Demand Paging

Stages in Demand Paging
1. Trap to the operating system
2. Save the user registers and process state
3. Determine that the interrupt was a page fault
4. Check that the page reference was legal and determine the location of the page on the disk
5. Issue a read from the disk to a free frame:
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

o Wait in a queue for this device until the read request is serviced
o Wait for the device seek and/or latency time
o Begin the transfer of the page to a free frame
6. While waiting, allocate the CPU to some other user
7. Receive an interrupt from the disk I/O subsystem (I/O completed)
8. Save the registers and process state for the other user
9. Determine that the interrupt was from the disk
10. Correct the page table and other tables to show page is now in memory
11. Wait for the CPU to be allocated to this process again
12. Restore the user registers, process state, and new page table, and then resume the interrupted
instruction
Copy-on-Write
 Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in
memory - If either process modifies a shared page, only then is the page copied
 COW allows more efficient process creation as only modified pages are copied
 In general, free pages are allocated from a pool of zero-fill-on-demand pages
 vfork() variation on fork() system call has parent suspend and child using copy-on-write address
space of parent - Designed to have child call exec() - Very efficient.

Before Process 1 Modifies Page C After Process 1 Modifies Page C

What Happens if There is no Free Frame?

 Used up by process pages

 Also in demand from the kernel, I/O buffers, etc
 Page replacement – find some page in memory, but not really in use, page it out
 Performance – want an algorithm which will result in minimum number of page faults
 Same page may be brought into memory several times
Page Replacement
 Prevent over-allocation of memory by modifying page-fault service routine to include page
replacement
 Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to
disk
 Page replacement completes separation between logical memory and physical memory – large
virtual memory can be provided on a smaller physical memory
Need For Page Replacement
 Find the location of the desired page on disk
 Find a free frame: - If there is a free frame, use it
If there is no free frame, use a page replacement algorithm to select a victim frame - Write victim
frame to disk if dirty
 CSE DEPARTMENT - BCS303 OPERATING SYSTEMS II Year – III Sem (2024-25 ODD)

 Bring the desired page into the (newly) free frame; update the page and frame tables
 Continue the process by restarting the instruction that caused the trap
 Note now potentially 2 page transfers for page fault – increasing EAT

Page Replacement

Page and Frame Replacement Algorithms

 Frame-allocation algorithm determines
o How many frames to give each process
o Which frames to replace
 Page-replacement algorithm
o Want lowest page-fault rate on both first access and re-access
 Evaluate algorithm by running it on a particular string of memory references (reference string) and
computing the number of page faults on that string
o String is just page numbers, not full addresses
o Repeated access to the same page does not cause a page fault
 In all our examples, the reference string is
o 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1

***