LAB MANUAL

DIGITAL SYSTEM DESIGN LABORATORY

III SEMESTER- II YEAR- ECE
REGULATION: 2021
SUBJECT CODE: EC3352
ANNA UNIVERSITY CHENNAI

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING
SARANATHAN COLLEGE OF ENGINEERING
TRICHY-620012
 INDEX
S.NO DATE NAME OF THE EXPERIMENT SIGNATURE
DATE:
EX.NO:

STUDY OF BASIC GATES

AIM:
To study the functions of the basic logic gates.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7432, IC7408, IC 7400, IC 7402, IC7404 , IC 7486 1 each
3 IC 7411, IC 7410 1 each
4 Patch cords As Required
5 Connecting wires As Required

THEORY:
The basic elements that make up a digital system are Logic Gates. The most common
gates are AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR gates. The NAND and NOR
gates are called as the universal gates because all the other gates can be implemented using these
two gates. A simple logic element whose binary output is a Boolean function (AND, OR...) of
the input is known as a GATE.
AND GATE:
In AND gate, the output Y is the product of the two inputs A and B. Hence, even
if one input is zero, the output becomes zero. If both the inputs are equal to one then the
output is also one.
Y=A B
OR GATE:
In OR gate, the output Y is the sum of the two inputs A and B.Hence, even if any
one of the input is one or both the input is one the output becomes one. The output
becomes zero only when both the inputs are zero.
Y = A+B

NOT GATE:
In NOT gate, the output Y is the complement of the input A. Hence, the output is
one when the input is zero and vice versa.
Y = A'
NAND GATE:
In NAND gate, the output Y is the complement of the product of two inputs A
and B. Hence, the output is one if any one of the input is zero. The output is zero if both
the inputs are one.
Y = (A B)'
 NOR GATE:
In NOR gate, the output Y is the complement of the sum of two inputs A and B.
Hence, if any one of the input is one, the output is zero and if both inputs are zero, the
output is one.
Y = (A+B)'
EXCLUSIVE OR GATE:
In EX-OR gate, the output Y is zero when both the inputs A and B are same (Both
are zero or both are one) otherwise the output is one.
Y=A B
EXCLUSIVE NOR GATE:
In EX-NOR gate, the output Y is one when both the inputs A and B are same
(Both are zero or both are one) otherwise the output is zero.
Y = (A B)'

PROCEDURE:
1. Make connections as per the logic diagram.
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for logic zero
connect the input pin to Ground.
3. Verify the corresponding outputs for the given inputs, using the truth table of AND gate.
4. Verify the truth tables for all the other gates.
AND GATE:
SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:
SYMBOL: PIN DIAGRAM:

X-OR GATE:
SYMBOL: PIN DIAGRAM:
NAND GATE:
SYMBOL: PIN DIAGRAM:

NOR GATE:
3-INPUT AND GATE:

3-INPUT NAND GATE:

RESULT:
DATE:
EX.NO:

DESIGN AND IMPLEMENTATION OF ADDER AND SUBTRACTOR USING LOGIC

GATES

AIM:
To design and implement the following Combinational circuits using logic gates.
A. Half Adder
B. Half Subtractor
C. Full Adder and
D. Full Subtractor.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7432, IC7408, IC7404 , IC 7486 1 each
3 Patch cords As Required
4 Connecting wires As Required

THEORY:

COMBINATIONAL CIRCUIT:
A Combinational circuit is a circuit in which the output is a direct immediate response of
the input stimuli. Each combination of these inputs is known as a minterm and can be plotted on
a truth table or Karnaugh map. Maps can be reduced by combining minterms into 2 n squares and
then reading the results either in Sum of product (SOP) form or in Product of Sum (POS) form.
A. HALF ADDER:
Half adder is combinational circuit which is capable of adding two binary bits
producing SUM (S) and CARRY(C) outputs. The disadvantage of this circuit is that it
can add only 2 bits.
S=X'Y+XY'
C=XY
B. FULL ADDER:
Full adder is a combinational circuit which is capable of adding three binary bits
producing SUM(S) and CARRY(C) outputs.
S=X'Y'Z+X'YZ'+XY'Z'+XYZ
C=XY+YZ+ZX
C. HALF SUBTRACTOR:
Half Subtractor is a combinational circuit which is capable of subtracting two
binary bits producing DIFFERENCE (D) and BORROW (B) outputs.
 D=X'Y+XY'
B=X'Y

D. FULL SUBTRACTOR:
Full Subtractor is a combinational circuit which is capable of subtracting three
binary bits producing DIFFERENCE (D) and BORROW (B) outputs.
D=X'Y'Z+X'YZ'+XY'Z'+XYZ
B=X'Y+YZ+X'Z'

PROCEDURE:

1. Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.

3. Verify the corresponding truth table.

HALF ADDER
TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

=A B
LOGIC DIAGRAM:

FULL ADDER
TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A’(B’C+BC’)+A(B’C’+BC)

=A’(B C)+A(B C)’
=A B C
K-Map for CARRY:

CARRY = AB + BC + AC
=A’BC+AB’C+ABC+ABC’=AB(C+C’)+C(A’B+AB’)
=AB+C( A B)

LOGIC DIAGRAM:

HALF SUBTRACTOR
TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

=A B
K-Map for BORROW:

BORROW = A’B
LOGIC DIAGRAM:

FULL SUBTRACTOR
TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC= A’(B’C+BC’)+A(B’C’+BC)

 =A’(B C)+A(B C)’
=A B C
K-Map for Borrow:

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

RESULT:
DATE:
EX.NO:

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING

LOGIC GATES

AIM:
To design and implement the following code converters using logic gates.
a. BINARY code to GRAY code and vice versa.
b. BCD to EXCESS-3 code and vice versa.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7432, IC 7408, IC 7404 , IC 7486 1 each
3 Patch cords As Required
4 Connecting wires As Required

THEORY:

BINARY CODE:
Any discrete element of information distinct among a group of quantities can be
represented with a binary code. The code must be in binary because computers can hold only 0’s
and 1’s. Binary codes merely change the symbol and not the meaning of the elements of
information that they represent. An n-bit binary code is a group of “n” bits that assumed up to 2 n
distinct combinations of 0’s and 1’s with each representing one element of the set that is being
coded. In general, a set of 2n elements can be coded with n bits. The bit combination of n-bit
code is determined from the count in binary form 0 to 2 n-1.

GRAY CODE:
It is convenient to use gray code to represent the digital data when it is converted from
analog data. The advantage of the Gray code over the straight binary number sequence is that
only one bit in the code group changes when going from one number to the next. The gray code
is used in applications where the normal sequence of binary numbers may produce error or
ambiguity during the transition from one number to the next. A typical application occurs when
the analog data are represented by continuous change in the shaft position.

BCD CODE:
It is possible to perform arithmetic operations directly with decimal numbers when they
are stored in the computer in a coded form. Different binary codes can be obtained by arranging
four bits in 10 distinct combinations. The code most commonly used for the decimal digits is the
straight binary assignment. This is called Binary coded decimal (BCD). It is a weighted code.
EXCESS-3 CODE:
The excess-3 code has been used in some older computers because of its self-
complementing property. Such codes have the property that the 9’s complement of a decimal
number is obtained directly by changing 1’s to 0’s and 0’s to 1’s in the code. This is an un-
weighted code where each coded combination is obtained from the corresponding binary value
added with 3.

PROCEDURE:

1. Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.

3. Verify the corresponding truth table.

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-Map for B3:

B3 = G3
K-Map for B2:

B2= G3’G2+G3G2’,

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTER
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3:

G3 = B3
K-Map for G2:

G2=B3’B2+B3B2’,
K-Map for G1:

G1=B2B1’+B2’B1,

K-Map for G0:

G0=B1’B0+B1B0’,

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTER:

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

X1 X2 X3 X4 A B C D

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map for A:

A = X1 X2 + X3 X4 X1=X1(X2+X3X4)
K-Map for B:

B=X2X3X4+X2’X3’+X2’X4’=X2X3X4+X2’(X3’+X4’)
=X2(X3’+X4’)’+X2’(X3’+X4’) =(X2 X3X4)’
K-Map for C:

C=X3’X4+X3X4’,
K-Map for D:

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

K-Map for E3:

E3 = B3+B2B0+B2B1=B3 + B2 (B0 + B1)

K-Map for E2:

E2= B2B1’B0’+B2’B0+B2’B1 =B2(B1+B0)’+B2’(B1+B0) =B2 (B1+B0)

K-Map for E1:

E1=B1’B0’+B1B0=
K-Map for E0:
LOGIC DIAGRAM:

RESULT:
DATE:
EX.NO:

DESIGN AND IMPLEMENTATION OF MAGNITUDE

COMPARATOR

AIM:
To design and implement magnitude comparator using logic gates.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7486, IC 7485 1
3 IC 7404 , IC 7408, IC 7432 2 each
4 Patch cords As Required
5 Connecting wires As Required

THEORY:
A magnitude comparator is a combinational circuit that compares two numbers A and B
and determines their relative magnitude. The comparison of two numbers is an operation that
determines whether one number is greater than, less than or equal to the other number.
The circuit for comparing two n-bit numbers has 22n entries in the truth table and
becomes too cumbersome even when n=3. On the other hand as one may suspect, a comparator
circuit possess a certain amount of regularity.
Digital functions that possess an inherent well-defined regularity can usually be designed
by means of an algorithm procedure. The equality of two numbers, A and B is displayed in a
combinational circuit by an output binary variable that we designate by symbol. This binary
variable is equal to 1 if the input numbers A and B are equal and it is zero otherwise.
To determine if A is greater or lesser than B we inspect the relative magnitude of pairs of
significant bits starting from the most significant bit position. If MSB of both A and B are equal
we compare the next lower significant pair of bits.

PROCEDURE:

1. Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.

3. Verify the corresponding truth table.

2-BIT MAGNITUDE COMPARATOR
TRUTH TABLE
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

SIMPLIFICATION USING K MAP

= A0B0’ (B1’+A1) +A1B1’

= A0’B0 (A1’+B1) +A1’B1

 A=B=A1’A0’B1’B0’+A1’A0B1’B0+A1A0’B1B0’+A1A0B1B0
= A1’B1’(A0’B0’+A0B0)+A1B1(A0’B0’+A0B0)
= (A0’B0’+A0B0)(A1’B1’+A1B1)=(A0 B0)(A1 B1)

LOGIC DIAGRAM:
4-BIT MAGNITUDE COMPARATOR

PIN DIAGRAM FOR IC 7485:

TRUTH TABLE:
A B A>B A=B A<B
0000 0000 0 1 0
0101 0000 1 0 0
0000 1001 0 0 1

LOGIC DIAGRAM:

RESULT:
DATE:
EX.NO:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DE-MULTIPLEXER

USING LOGIC GATES AND STUDY OF IC 74150 AND IC4154

AIM:
To design and implement multiplexer and De-multiplexer using logic gates and study of
IC 74150 (Multiplexer IC), IC 74154 (De-Multiplexer IC).

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7404 1
3 IC 7411 2
4 IC 7432, IC 74150, IC 74154 1 each
5 Patch cords As Required
6 Connecting wires As Required

THEORY:

MULTIPLEXER:
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input lines and n selection lines
whose bit combinations determine which input is selected.
A multiplexer function like an electronic switch that selects one of the multiple sources.
It suggests visually how a selected one of multiple data source is directed into a single
destination.
In a 4-to-1 line multiplexer, each of the four input lines (I 0 to I3) is applied to one input of
AND gate. Selection lines A and B are decoded to select a particular AND gate. The outputs of
the AND gates are applied to a single OR gate that provides the one output line. As a multiplexer
selects one of many input lines and steers the binary information to the output line, it is also
called as “Data selector”. The AND gates and inverters in the multiplexer resemble a decoder
circuit and indeed they decode the selection input lines.
IC 74150 is 16-to-1 Multiplexer IC. It has 16 input lines (E 0 to E15), 4 selection lines (A,
B, C, D) and 1 output line. The output of IC 74150 is active low.
DE-MULTIPLEXER:
A De-multiplexer is a combinational logic circuit that receives information on a single
input line and transmits it through anyone of the 2n output lines (where ‘n’ is the number of
selection lines).The word de-multiplexer means one into many. De-multiplexing is a process
of taking information from one input line and transmitting the same over one of the several
output lines.
The operation of a de-multiplexer is opposite to that of a multiplexer. The circuit has one
input line, n selection lines and 2n output lines. The selection inputs determine to which output
line the input data will be connected. As the serial data is changed to a parallel data , i.e. the
input caused to appear on any one of the 2n output lines, the de-multiplexer is also called as a
“Distributor” or a serial-to-parallel convertor.
1-to-4 De-multiplexer can be implemented using four 3-input NAND gates and two NOT
gates. Here the input data line is connected to all the AND gates. The two selection lines enable
only one gate at a time and the data that appears on the input line passes through the selected
gate to the associated output line.

PROCEDURE:

1. Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.
3. Verify the corresponding truth table.
4:1 MULTIPLEXER USING LOGIC GATES:
BLOCK DIAGRAM:

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

DESIGN: Y=S1’S0’D0+S1’S0D1+S1S0’D2+S1S0D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER USING LOGIC GATES:

BLOCK DIAGRAM:

TRUTH TABLE:

DATA SELECT OUTPUTS

S1 S0 D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
LOGIC DIAGRAM FOR DEMULTIPLEXER:

Design: D0=S1’S0’D, D1=S1’S0D, D2=S1S0’D, D3=S1S0D

PIN DIAGRAM FOR MULTIPLEXER IC 74150:

E0-E15 are inputs, ABCD are selection lines & Q is output. ST(strobe) is enable
input.
TRUTH TABLE:

ST D C B A Q
1 X X X X 0
0 0 0 0 0 E0’
0 0 0 0 1 E1’
0 0 0 1 0 E2’
0 0 0 1 1 E3’
0 0 1 0 0 E4’
0 0 1 0 1 E5’
0 0 1 1 0 E6’
0 0 1 1 1 E7’
0 1 0 0 0 E8’
0 1 0 0 1 E9’
0 1 0 1 0 E10’
0 1 0 1 1 E11’
0 1 1 0 0 E12’
0 1 1 0 1 E13’
0 1 1 1 0 E14’
0 1 1 1 1 E15’

PIN DIAGRAM FOR DEMULTIPLEXER IC 74154:

Q0-Q15 are outputs, ABCD are selection inputs and Data is input. ST(strobe) is enable signal.
TRUTH TABLE:

ST Data D C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15

1 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

RESULT:
 DATE:
EX.NO:
STUDY OF JKFF, DFF & RSFF
AIM:
To study and verify the function table of JKFF, DFF & RSFF.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7474, IC 7476,IC7400 1 each
3 Patch cords As Required
4 Connecting wires As Required

THEORY:
A memory cell is the simplest sequential circuit. It has only two states either 1 or 0. Such
two state sequential circuits are called ‘Flip flops’ as they flip from one state to another and then
flop back. A Flip flop is also known as bi-stable multivibrator, a latch or toggle.
D-FLIP FLOP:
The D-flip flop has only one input called the delay (D) input and two outputs q and q'. It
can be constructed from an SR-flip flop by inserting an inverter between S and R and assigning
the symbol D to the S input. It consists of four NAND gates. When the clock input is low, the D
input has no effect as set and reset input of the NAND gates are kept high. When the clock input
goes high, the q output will take the value of the D input. The characteristic equation for a D-flip
flop is q (t+1) = D
JK-FLIP FLOP:
A JK-flip flop is similar to that of an SR-flip flop. In addition, the indeterminate
condition of the SR-flip flop is permitted in it. Inputs J and K behave like inputs S and R to set
an reset the flip flop respectively. When J=K=1, the flip flop output toggles i.e. output switches
to its complement state. A JK-flip flop can be obtained from the clocked SR-flip flop by
augmenting two AND gates. The characteristic equation of a JK-flip flop is q(t+1) = Jq'+K'q
RS FLIP-FLOP:
S represents set and R represents reset. When SR=11 output will be indeterminate to
avoid that we go for JKFF.

PROCEDURE:
1) Make connections as per the logic diagram.
2) Give input signals. For logic 1, connect the input pin to +5V and for logic zero;
connect the input pin to Ground.
3) Give Clock pulse one by one and verify the corresponding outputs for the given
inputs using the indication lamps.
JKFF IC 7476:

TRUTH TABLE:
Q(t)(previous J K Q
CLR PRE CLK output)
0 1 1 0 X X 0

1 1 1 0 0 0 0

1 1 1 0 0 1 0

1 1 1 0 1 0 1

1 1 1 0 1 1 1

1 1 1 1 0 0 1

1 1 1 1 0 1 0

1 1 1 1 1 0 1

1 1 1 1 1 1 0
DFF IC 7474:

TRUTH TABLE:
Q(t)(previous D Q
CLR PRE CLK output)

0 1 1 0 X 0

1 1 1 0 0 0

1 1 1 0 1 1

1 1 1 1 0 0

1 1 1 1 1 1

RSFF LOGIC DIAGRAM:

TRUTH TABLE:
CP Q(t) S R Q Q’
1 0 0 0 0 1
1 0 0 1 0 1
1 0 1 0 1 0
1 0 1 1 INVALID INVALID
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 INVALID INVALID
RESULT:
DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF 4-BIT
SYNCHRONOUS AND ASYNCHRONOUS COUNTERS
USING FLIP FLOP

AIM:
To design and implement 4-bit synchronous and asynchronous counters using flip flop.
COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7476 2

3 IC 7408 1 each

4 Patch cords As Required

5 Connecting wires As Required

THEORY:
COUNTER:
A register that goes through a prescribed sequence of states upon the application of input pulses is
called counter. The input pulses may be clock pulses or they may originate from external source. The
sequence of states may follow the binary number sequence or any other sequence of states. A counter that
follows the binary number is called binary counter.
Counters are available in two categories
 Ripple counter
 Synchronous counter
4-BIT RIPPLE COUNTER:
In a Ripple counter, the flip-flop output transition from a previous stage serves as the source of
triggering the flip-flop in the successive stage. The count starts with binary ‘0’ and increments by one
with each clock pulse input. After the count 15, the counter goes to 0. The least significant bit is
complemented at each clock pulse input. Every time A0 goes from 1 to 0, A1 is complemented. Similarly
every time A1 goes from 1 to 0, A2 is complemented and A3 gets complemented when A2 goes from 1 to
0. Output of one FF will act as clock pulse to next FF. There will be no common clock pulse.
SYNCHRONOUS COUNTER:
It also counts from 0 to 15 binary numbers but it has common clock pulse to all FFs. These
counters can be designed using state table and K-Map simplification. Delay will be common for each
clock pulse.
PROCEDURE:

1. Make connections as per the logic diagram.

2. Give input signals. For logic 1, connect the input pin to +5V and for logic zero; connect
the input pin to Ground.
3. Give Clock pulse one by one and verify the corresponding outputs for the given inputs
using the indication lamps.
4 BIT RIPPLE COUNTER:
TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

 4-BIT SYNCHRONOUS COUNTER

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TRUTH TABLE:

Present State Next State A B C D

Q A Q B QCQD Q A+1 Q B+1 QC+1QD+1 JA KA JB KB JC KC JD KD

0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1

Simplification using K MAP

LOGIC DIAGRAM:

RESULT:
DATE:
EX.NO:
IMPLEMENTATION OF SIPO, SISO, PISO AND PIPO SHIFT
REGISTERS USING D-FLIP FLOP
AIM:

To implement SIPO, SISO, PISO and PIPO shift registers using D-flip flop.

COMPONENTS REQUIRED:

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

2 IC 7474, IC 7408 2 each
3 IC 7404, IC 7432 1 each
4 Patch cords As Required
5 Connecting wires As Required

THEORY:

A register that is used to store binary information is known as a memory register. A Shift
register is a register which is capable of shifting binary information either to right or to the left.

SERIAL IN SERIAL OUT SHIFT REGISTER (SISO):

This type of shift register accepts data serially i.e. one bit at a time on a single input line.
It produces the store information on its single output also in serial form. Data may be shifted left
(from low to higher order bits) or right (from high to lower order bits) using shift left and shift
right registers respectively.

a) SHIFT LEFT REGISTER:

Using D-flip flops input of the rightmost flip flop is used as a serial input
line. For input data ‘1’, one is applied at the D input and for input data ‘0’, a zero
is applied at the D input. The clock pulse is applied to all the flip flops
simultaneously. When the shift or clock pulse occurs each flip flop is set or reset
according to the data at the respective flip flop input.

b) SHIFT RIGHT REGISTER:

A shift right register can also be constructed using D-flip flop. Entry of 4-
bits 1101 into the register, beginning with the right most bit. One is applied at the
 serial input line i.e. at Delay input of the first flip flop. When the first clock pulse
is applied, flip flop A is set storing 1. Then a zero is applied to the serial input,
making D = 0 for flip flop A and D = 1 for flip flop B because D input of flip flop
B is connected to qA output. Similarly every bit is shifted right serially.

SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO):

It consists of one serial input and the outputs taken from all the flip flops are parallel. In
this register data is shifted in serially but shifted out in parallel. In order to shift the data out in
parallel it is necessary to have all the data available at the outputs at the same time. One the data
is stored, each bit appears on its respective output line and all the bits are available
simultaneously.

PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO):

A 4-bit parallel in serial out register has four parallel input data lines (A, B, C, D) and a
control input (SHIFT/LOAD') that allows the four bits of data at the input lines to enter into the
register in parallel or shift the data in serial. When SHIFT/LOAD' is low, AND gates G 1 through
G3 are enabled allowing the data at the parallel inputs B,C and D to the Delay input of its
respective flip flop. The A input is directly connected to the Delay input of the first flip flop.
When the clock pulse is applied, the flip flops with D = 1 will be set and the flip flops with D = 0
will be reset, there by restoring all 4-bits simultaneously. When SHIFT/LOAD' is high, AND
gates G1 through G3 are disabled and the remaining AND gates G4 through G6 are enabled
allowing the data bits to shift right from one stage to the next. The OR gates allow the normal
shifting operation depending on which the AND gates are enabled by the level on the
SHIFT/LOAD' input.

PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO):

In this type of register, data inputs can be shifted in or out of the register in parallel. The
parallel entry of the data is carried out and the output is also taken parallel. In this register, there
is no interconnection between successive flip flops since no serial shifting is required. Therefore
the moment the parallel entry of the input data is accomplished, the respective bits will appear at
the parallel output.

PROCEDURE:

1. Make connections as per the logic diagram.

2. Give input signals. For logic 1, connect the input pin to +5V and for logic zero; connect
the input pin to Ground.

3. Give Clock pulse one by one and verify the corresponding outputs for the given inputs
using the indication lamps.
SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK DATA IN DATA

OUTPUT

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
OUTPUT
CLK DATA Q3 Q2 Q1 Q0

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 1 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK A B C D O/P
SHIFT/
LOAD
1 0 1 1 0 1 0

0 1 X X X X 1

0 2 X X X X 0

0 3 X X X X 1

0 4 X X X X 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
DATA INPUT OUTPUT
CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

LOGIC DIAGRAM:

RESULT: