INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad - 500 043

ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

Course Title VLSI DESIGN

Course Code AECB27
Program B.Tech
Semester VII ECE
Course Type CORE
Regulation IARE-R18
Theory Practical
Course Structure Lecture Tutorials Credits Laboratory Credits
3 1 4 3 2
Course Coordinator Mrs. KS Indrani, Assistant Professor

COURSE OBJECTIVES:
The students will try to learn:

I Principles of hierarchical VLSI design from the metal oxide semiconductor

transistor up to the system level and impact of scaling trends on the device
parameters fabrication and testing.
II Data path subsystems incorporating into a VLSI chip with contemporary
techniques for achieving high-speed, low-power and low area overhead.
III Chip design through a practical approach using advanced modern tools such as
vivado and cadence for front end and back end.

COURSE OUTCOMES:
After successful completion of the course, students should be able to:
CO 1 Describe the MOSFET fundamentals & latest trends in the understand
technology in line with forecast made by Moore for computing the
parameters with constant or combined scaling models.
CO 2 Examine the conditions for optimum performance of inverters Analyse
using the volt- ampere and threshold voltage characteristics of
MOSFETS
 CO 3 Explain the oxidation, diffusion, ion implantation & lithography Understand
processes for pmos, nmos, cmos and BiCMOS transistors
fabrication.
CO 4 Build for pmos, nmos, cmos and BiCMOS transistors fabrication. apply
using lambda, absolute and Euler physical design rules..
CO 5 Summarize the reliability issues in interconnects, latching and Understand
electro migration for formulating remedial measurements to increase
lifetime.
CO 6 Compare static and dynamic CMOS logic circuits in terms of Analyze
power consumption and speed of operation.
CO 7 Distinguish the structure, implementation approaches for full Analyse
custom and semicustom design on the basis of speed, cost,
reconfiguration and time to market parameters..
CO 8 outline the role of Programmable logic devices such as PLA, PAL, Understand
PROM, FPGA and CPLD for realization of complex boolean
functions.
CO 9 Develop data path subsystems such as shifters, adders, multipliers, Apply
ALUs, parity generators, counters and comparators using stick
diagrams and layouts.
CO 10 Summarize working principle of memory units and its peripheral understand
circuitry using different models.
CO 11 Develop test strategies suitable for the integrated circuits in analog Apply
and mixed signal domain.
CO 12 Construct simulation, synthesis and design verification of logic Create
circuits using the key elements of VLSI design flow.

QUESTION BANK:
Q.No QUESTION Taxonomy
How does this subsume CO’s
the level
MODULE I
BASICS OF MOSFETS
PART A-PROBLEM SOLVING AND CRITICAL THINKING QUESTIONS
1 An nMOS transistor is Understand The learner to recall the CO 1
operating in saturation formula for an nMOS
region with the following transistor operating in
parameters. VGS =5V, saturation region and
VT=1.2V, W/L =110, interpret the values of
UnCox=110 u A/V2. Show trans-conductance and
the values of output conductance of the
trans-conductance and device.
output conductance of the
device.

Page 2
2 Describe the effect of Understand The learner todescribe the CO 1
substrate bias voltage on effect of substrate bias and
threshold voltage for infer it for threshold
n-MOSFET enhancement voltage of n-MOSFET.
transistor.
3 Consider the nMOS Understand The learner to recall the CO 1
transistor in a 180 nm concepts of nMOS
process with a nominal transistors and
threshold voltage of 0.4 V demonstrate the value of
and a doping level of threshold voltage change at
8Ö10-17 cm–3. The body is room temperature with the
tied to ground with a given parameters.
substrate contact. Show the
value of the threshold
change at room temperature
if the source is at 1.1 V
instead of 0? Assume
tox=10.5x10-8 cm, q =
1.6x10-19 coul, Ersi =11.7,
Ersio = 3.9, Eo =8.85
x10-14 F/cm. Assume ni
(Intrinsic concentration) =
1.45x1010 cm-3, VT =
kT/q = 0.026V.
4 Consider an nMOS Understand The learner to recall the CO 1
transistor in a 0.6 um concepts of nMOS
process with W/L = 4/2. In transistors andoutline a
this process, the gate oxide plot of Ids versus Vds with
thickness is 100 A and the the given parameters.
mobility of electrons is 350
cm2/V· s. The threshold
voltage is 0.7 V. Plot Ids vs.
VDS for VGS = 1. Assume
tox=10.0x10-8 Ersio = 3.9,
Eo =8.85 x10-14 F/cm.
5 An nMOS transistor is Understand The learner to recall the CO 1
operating in saturation concept and formulas of
region with the following nMOS transistors in
parameters. Vgs =4V, saturation region and
VT=1.0V, W/L =100, illustrate the values of
UnCox=90 uA/V2. Find drain current and drain to
drain current and drain to source resistance.
source resistance

Page 3
6 Illustrate the relationship Understand The learner to recall the CO 1
between IDS versus VDS of concept of transistors and
for various region of illustrate the relationship
operations between Ids versus Vds.
7 A pMOS transistor is Understand The learner torecall the CO 1
operating in non-saturation concept and formulae for
region with the following pMOS transistors and
parameters. Vgs = - 4.5V, demonstrate the values of
Vt = - 1.0V, W/L =95, drain current and drain to
UpCox=95 uA/V2. Find source resistance.
drain current and drain to
source resistance.
8 A pMOS transistor is Understand The learner torecall the CO 1
operating in saturation concept and formulae for
region with the following pMOS transistors under
parameters. Vgs = - 4.5V, various regions and
Vt = - 1.0V, W/L =95, demonstrate the values of
upCox=95 u A/V2. Find drain current and drain to
drain current and drain to source resistance.
source resistance
9 An nMOS transistor is Understand The learner to recall the CO 1
operating in saturation concept and formulae for
region with the following nMOS transistors and
parameters. VGS =5V, demonstrate the
VT=1.2V, W/L =10, trans-conductance value
unCox=110 uA/V2. Find with the help of given
trans-conductance of the parameters.
device
10 For a CMOS inverter, Show Understand CO 2
the shift in the transfer
characteristic curve when
Bn / Bp ratio is varied from
1/1 to 10/1
PART-B LONG ANSWER QUESTIONS
1 Outline the Derivation of Understand The learner to recall the CO 1
the expression for drain various models of MOSFET
current of MOSFET in analysis and then
Linear/Non saturation demonstrate the
region mathematical expression in
a particular region of
mosfet.

Page 4
2 Explain the operation of Understand The learner to describe the CO 1
nMOS enhancement structure and functions of a
MOSFET and draw V-I particular model of
characteristics MOSFET and then outline
its characteristics in the
form of a graph.
3 Relate the effect of Understand The learner to recall the CO 1
substrate bias on threshold concepts of NMOS
voltage for NMOS enhancement transistor and
enhancement transistor. then explain the effect of
substrate bias on the
threshold voltage.
4 Interpret Body Effect in Understand The learner to list the Short CO 1
MOSFETs Body Effects in MOSFETs
and summarize them.
5 Outline the formulae for Understand The learner to define the CO 1
MOS transistor concept of
trans-conductance and trans-conductance and
figure of merit with figure of merit of a MOS
derivations transistor and outline the
respective formulae.
6 Outline Bi-CMOS Understand The learner to describe CO 1
fabrication in an n-well the Bi-CMOS fabrication in
process an n-well process and
illustrate the fabrication
procedure.
7 Compare CMOS and Understand The learner to describe CO 1
bipolar technologies. the theory of CMOS and
Bipolar technologies and
compare both technologies.
8 Describe enhancement mode Understand The learner to describe CO 1
transistor action for the working of the transistor
different cases of Vgs, Vds ? in enhancement mode and
extend the concept for
different voltage conditions.
9 Relate the effect of positive Understan The learner to recall the CO 1
or negative substrate bias effects of substrate bias and
on the threshold of an demonstrate them
nMOS transistor
10 Explain NMOS fabrication Understand The learner to describe CO 2
Process with neat diagrams the NMOS fabrication
process and illustrate the
concept with diagrams.

Page 5
11 Explain PMOS fabrication Understand The learner to describe the CO 3
Process with neat diagrams PMOS fabrication process
andillustrate the concept
with diagrams.
12 Outline MOS inverter Understand The learner to describe the CO 2
operation with neat circuit MOS inverter operation
diagram? andillustrate the concept
with diagrams.
13 Interpret the CMOS Understand The learner to describe the CO 2
inverter DC characteristics CMOS inverter DC
and elaborate the characteristics and explain
relationship for output the relationship for output
voltage at different regions voltage at different regions
in the transfer in the transfer
characteristics characteristics
14 Discover the various forms Analyze Learner to choose the CO 2
of pull-ups with circuit relevant MOSFETs then
diagram and characteristics? discover the necessary
modifications to form the
pull-ups
15 Show various forms of Remember - CO 2
Bi-CMOS inverter and
bring out the advantages
and dis-advantages.
16 List the draw backs of Remember - CO 2
simple Bi-CMOS inverter.
How to overcome the draw
backs using modifications.
17 Outline nMOS inverter Understand The learner to describe CO 2
transfer characteristics with the NMOS inverter transfer
neat diagram? characteristics and
illustrat— the concept
with suitable diagrams.
18 Compare CMOS and Understand The learner to recall the CO 2
bipolar technologies. concepts of CMOS and
Describe the advantages of bipolar technologies and
Bi-CMOS Technology compare them. Also the
learner should illustrate
the advantages of Bi-CMOS
technology.
19 Enumerate about various Understand The learner to recall the CO 3
steps in n-well process of n-well process of CMOS and
CMOS? demonstrate them in a
step-wise manner

Page 6
20 Demonstrate various forms Understand The learner to state CO 2
of Bi CMOS inverter for various forms of Bi-CMOS
satisfactory operation. inverter and extend the
concept for satisfactory
operation.
PART-C SHORT ANSWER QUESTIONS
1 Compare enhancement and Understand The learner to list the CO 1
depletion mode of MOSFET features of mosfets and then
compare n and p
MOSFETs based on their
characteristics
2 What is BiCMOS Remember - CO 1
technology
3 How MOSFET is better Remember - CO 1
than BJT?
4 Define body effect Remembe - CO 1
5 Outline mathematical Understand The learner to recall the CO 1
expression of drain current various models of MOSFET
saturation region of analysis and then outline
operation in MOSFET the mathematical expression
in a particular region of
mosfet.
6 Define inversion of MoS Remember - CO 1
structure
7 Recall mathematical Remember - CO 1
expression of drain current
non saturation region of
operation in MOSFET
8 Why nMOS technology is Remembe - CO 1
preferred more than pMOS
technology
9 What is the structure of Remember - CO 1
depletion MOSFET
10 Define gate capacitance? Remember - CO 1
11 List the different types of Remember - CO 2
CMOS processes
12 What is pull down device in Remember - CO 2
CMOS inverter
13 What is pull up device in Remember - CO 2
CMOS inverter
14 Show the steps involved in Remember - CO 3
twin-tub process

Page 7
115 Interpret the advantages of Understand The learner to recall the CO 2
CMOS configuration concepts of CMOS and
illustrate the advantages of
CMOS configuration.
16 show the pass transistor Understand The learner to draw the CO 2
logic symbol for NMOS and transistor logic symbols of
PMOS transistor NMOS and PMOS
transistors and explain
them.
17 Which circuit is normally Remember - CO 2
used as level restorer
18 Show the transfer Understand
The learner to recall the CO 2
characteristic of inverter concept of enhancement
using nMOS enhancement mode of nMOS transistor
mode transistor pull-up? and infer the concept to
show the transfer
characteristic of an inverter.
19 Summarize the limitations Understand The learner to recall the CO 2
of nMOS inverter circuit concept of nMOS inverter
using enhancement mode circuit in enhancement
transistor pullup mode and summarize the
limitations.
20 Show the transfer Understand The learner to recall the CO 2
characteristic of inverter concept of depletion mode
using nMOS depletion mode of nMOS transistor and
transistor pull-up? infer the concept to show
the transfer characteristic of
an inverter.
MODULE II
VLSI CIRCUIT DESIGN PROCESSES
PART-A PROBLEM SOLVING AND CRITICAL THINKING QUESTIONS
1 Draw the nMOS diagram Understand The learner to recall the CO 5
and stick diagram for concept of stick diagram
y=(AB + CD)1 anddemonstrate it for the
given logical equation.
2 Draw the circuit schematic Understand The learner to recall the CO 5
and stick diagram of CMOS concept of stick diagram
2-Input NAND Gate and illustrate the schematic
and stick diagram for
CMOS 2-Input NAND gate.

Page 8
3 Describe EX-OR gate? Understand The learner to recall the CO 5
Draw the stick diagram concept of stick diagram
with transistor schematic in and EX-OR gate and
CMOS style illustrate the stick diagram
with transistor schematic in
CMOS style.
4 Write the truth table for Apply Learner to explain EX-OR CO 5
EX-OR gate and draw the gate truth table and then
stick diagram along with model the stick diagram.
transistor schematic
5 Show the stick diagram for UnderstandThe learner to draw the CO 5
CMOS EX-NOR gate along stick diagram and
with transistor schematic illustrate it specifically for
CMOS EX-NOR gate.
6 Show the effect of scaling on Understand The learner to recall the CO 1
channel résistance and concept of effects of scaling
maximum operating and illustrate it for
frequency, Power dissipation channel resistance,
per gate maximum operating
frequency and power
dissipation per gate.
7 Draw a stick diagram in Understand The learner to recall the CO 5
pMOS logic for the Boolean concept of stick diagram
expression Y= andillustrate it in pMOS
(AB+AC+BC)’. logic for a given boolean
expression.
8 Outline the truth table for Understand The learner to state the CO 5
two input NOR gate and truth tables and outline
draw the stick diagram. the stick diagram for two
input NOR gate.
9 Draw the stick diagram and Understand The learner to recall the CO 5
layout for a CMOS inverter concept of a stick diagram
and interpret the stick
diagram and layout for a
CMOS inverter.
10 Construct the layout Apply Learner to explain n MOS CO 5
diagram for nMOS inverter inverter and then develop
along with circuit diagram the layout diagram
PART-B LONG ANSWER QUESTIONS
1 Illustrate the nMOS Design Understand The learner to recall the CO 5
rules for a simple Boolean concept of nMOS design
expression rules and infer it for a
simple boolean expression.

Page 9
2 Describe the CMOS Design Understand The learner to recall the CO 5
rules with an example. concept of CMOS design
rules and illustrate it with
an example.
3 What are contact cuts? Remember - CO 5
Explain buried and but
contacts with necessary
diagrams
4 Describe CMOS design Understand The learner to recall the CO 5
style. Compare it with concept of CMOS design
NMOS design style. style and compare it with
nMOS design style.
5 Draw the transistor level Understand The learner to draw the CO 5
diagram for the expression transistor level diagram for
Y=(AB+CD)’ and also a given expression and also
draw the corresponding illustrate the stick diagram
Stick diagram representation using CMOS
representation using CMOS logic for the same.
logic.
6 What is stick diagram and Remember - CO 5
list the rules for drawing
Stick Diagrams?
7 Describe the design rules for Understand The learner to recall the CO 5
wires (nMOS and CMOS) concept of design rules for
wires andillustrate them
for CMOS and nMOS.
8 Describe the design rules for Understand The learner to recall the CO 5
nMOSET, pMOSFET concept design rules and
transistors illustrate them for
nMOSFET and pMOSFET
9 Explain about Euler’s rule Understand The learner to state the CO 5
for physical design with an concept of Euler’s rule for
example? physical design and
demonstrate it with an
example.
10 Outline design rules for Understand The learner to recall the CO 5
wires, n-diffusion, concepts of design rules for
p-diffusion and metals. wires, n-diffusion,
p-diffusion, metals and
outline them in detail.

Page 10
11 What are the different Remember - CO 1
scaling models and describe
in detail about the effects of
scaling on any four
parameters
12 Interpret transistor scaling Understand The learner to describe CO 1
and any four device the concepts of transistor
parameters. scaling and device
parameters and relate
them.
13 Interpret the projections in Understand The learner to recall the CO 1
VLSI design and technology history and evolution of
with the help of Moore’s law VLSI design and technology
and textbf interpret the
development through
Moore’s law.
14 What is CMOS Remember - CO 1
nanotechnology?
Summarize the latest trends
15 Compare CMOS technology Understan The learner to define the CO 1
and nano technology? CMOS and Nano
technologies andcompare
the two owing to their
positives and negatives.
16 Describe with neat diagrams Understand The learner to recall the CO 5
about 2 µm CMOS Design concept of CMOS design
rules for wires rules and illustrate it for
2um CMOS for wires
17 Outline design rules for Understand The learner to state the CO 5
transistors (nMOS, pMOS, concept design rules
CMOS) andinfer the concepts for
nMOS, pMOS and CMOS.
18 Relate the effect of scaling Understand The learner to define the CO 1
on gate delay and gate area various scaling models and
then outline the effect on
the device parameters
19 Relate the effect of scaling Understand The learner to define the CO 1
on channel resistance, max various scaling models and
frequency then outline the effect on
the device parameters
20 Relate the effect of scaling Understand The learner to define the CO 1
on gate capacitance and various scaling models and
gate resistance then outline the effect on
the device parameters

Page 11
 PART-C SHORT ANSWER QUESTIONS
1 Summarize transistor design Understand The learner to describe CO 5
rules for NMOS the NMOS concept and
summarize the transistor
design rules.
2 Draw layout diagram for Remember - CO 5
nMOS inverter
3 State Lambda based rules Remember - CO 5
for n diffusion wires by
specifying its spacing and
width?
4 Infer Lambda based rules Understan The learner to recall the CO 5
for VDD and VSS contacts? lambda rules and infer the
rules for VDD and VSS
contacts in detail.
5 Explain Moore’s Law Understand The learner to recall the CO 1
evolution of VLSI
technology and then
explain the Moore’s law
6 Interpret the effect of Understand The learner to define the CO 1
scaling on channel resistance various scaling models and
thenoutline the effect on
the device parameters
7 When the Moore’s law is Remember - CO 1
likely to end ?
8 Relate the effect of scaling Understand The learner to define the CO 1
on gate area scaling effects on gate
area,and to relate those
phenomena.
9 Show mathematically the Understand The learner to state the CO 1
effect of scaling on IDSS effect of scaling on Idss and
and channel resistance, explain the concept
current density and mathematically.
switching energy
10 Define Stick Diagram? Remember - CO 5
11 What is the use of Stick Remember - CO 5
diagram
12 Draw the schematic Remembe - CO 5
diagram of nMOS depletion
mode inverter?
13 What stick encoding? Remember - CO 5
14 State the properties of stick Remember - CO 5
diagram?

Page 12
15 Draw the stick diagram for UnderstandThe learner to recall the CO 5
2 input nMOS nor gate. concept of stick diagrams
and show them for 2 input
nMOS nor gate.
16 List out the components not Understand The learner to recall the CO 5
shown by stick diagram concept of stick diagrams
and classify the components
that are not shown by stick
diagrams.
17 Show the color Understand The learner to recall the CO 5
representation of various concept of stick diagrams
layers? and show the color
representation of various
layers.
18 Relate the effect of scaling Understand The learner to define the CO 1
on gate delay scaling effects on gate delay
concepts and to relate
those phenomena.
19 Relate the effect of scaling Understand The learner to define the CO 1
on channel resistance scaling effects on gate area,
channel resistance and to
relate those phenomena.
20 Relate the effect of scaling Understand The learner to define the CO 1
on gate capacitance scaling effects on gate
capacitance and to relate
those phenomena.
MODULE III
BASIC CIRCUIT CONCEPTS AND GATE LEVEL DESIGN
PART A-PROBLEM SOLVING AND CRITICAL THINKING QUESTIONS
1 Discover the Pull-up to Analyze Learner to make use of CO 2
pull-down ratio (Zpu/Zpd) Ids-Vds equations of
for an nMOS inverter driven MOSFETs to form the
through one or more Pass relationships
Transistors
2 Interpret the Pull-up to Understand The learner to recall the CO 2
pull-down ratio (Zpu/Zpd) pull-up to pull-down ratio
for an nMOS inverter driven concept and infer it to an
by another nMOS inverter nMOS inverter driven by
another nMOS inverter.
3 Develop the expression for Apply Learner to recall CMOS CO 7
rise and fall time of CMOS inverter, then explain the
inverter. Comment on the rise and fall times and solve
expression derived. for the functions

Page 13
4 Calculate the gate Apply Learner torecall CMOS CO 7
capacitance value of 5 mm inverter, then explain the
technology minimum size gate capacitance and
transistor with gate to calculate the values
channel capacitance value is
0.0004 pF/um2.
5 Two NMOS inverters are Apply Learner to recall nMOS CO 7
cascaded to drive a inverter, then describe the
capacitive load CL=14Cg. gate capacitance and
Calculate the pair delay Vin calculate the values
to Vout interms of T for the
data given. Inverter
A:Lpu=12 Lamda Wpu=4
Lamda Lpd=1 Lamda
Wpd=1 Lamda Inverter B:
Lpu=4 Lamda Wpu=4
Lamda Lpd=2 Lamda
Wpd=8 Lamda

CIE-II
1 Show the function f = Understand
The learner to state CMOS CO 4
(AB+CD)’ using nMOS and and nMOS logics and
CMOS logic. interpret the given function
using the logics.
2 Build the function f Apply Learner to outline CO 7
=A+BC using pseudo–nMOS logic and
pseudo–nMOS logic. then build the function
3 Show the circuit for Understand The learner to recall the CO 7
function f=A+B+C+D concept of domino logic and
using domino logic. demonstrate a circuit for
a given function.
4 Show the circuit for Understan The learner to state the CO 7
function f=(A+B)’ using functioning of clocked
clocked C MOS logic CMOS logic andinterpret
the given function.
5 Show 4:1MUX using Understan The learner todescribe the CO 4
transmission gate. concept of transmission
gates and infer it to a 4:1
MUX.
PART-B LONG ANSWER QUESTIONS
1 How delay that occurs due Remember - CO 6
to interconnects in VLSI?

Page 14
2 What is cross talk and Remember - CO 6
elaborate the effects on the
performance
3 Discuss the effect of Understand The learner to recall the CO 6
resistance in interconnects concept of vlsi design and
while interfacing different summarize the effect of
layers? resistance in interconnects
while interfacing different
layers.
4 Define time delay unit and Remember - CO 7
derive the expression for
nMOS inverter pair time
delay
5 Define time delay unit and Remember - CO 7
derive the expression for
CMOS inverter pair time
delay
6 Write the conditions for Remember - CO 7
equal rise and fall times for
CMOS inverter
7 Describe in detail different Understand The learner to recall the CO 7
types of capacitances in concept of MOSFETs and
MOSFETs demonstrate in detail
different types of
capacitances in MOSFETs.
8 Outline different factors Understand The learner to state— the CO 7
influencing choice of layers. concept of choice of layers
and outline the different
factors influencing it.
9 Examine the formula for Analyze Learner to make use of CO 2
Zpu/Zpd when nMOS Ids-Vds equations of
inverter is driven by another MOSFETs to form the
nMOS inverter with relationships
mathematical derivations?
10 What is the formula for Remember - CO 2
Zpu/Zpd when nMOS
inverter is driven by one or
more pass gates with
mathematical derivations
CIE-II

Page 15
1 Discuss the latch up in Understand The learner to recall the CO 6
CMOS in detail with neat concept of CMOS design
diagram and demonstrate the
concept of latch up in
CMOS with a suitable
diagram.
2 Explain various reliability Understand The learner to state the CO 6
issues in CMOS VLSI using reliability issues in CMOS
bathtub curve design and illustrate it
with bathtub curve concept.
3 What are the Interconnects Remember - CO 5
and outline their effect in
circuit?
4 Discuss various failure Remember - CO 6
mechanisms that occurs in
VLSI?
5 Draw the transistor-level Understand The learner to recall the CO 5
schematic for a compound concept of transistor-level
CMOS logic gate for each of schematic and
the following functions: Y = demonstrate it for a given
(AB + C) · D. interfacing function.
different layers
6 What is pass transistor Remember - CO 2
logic? List the advantages
and disadvantages of it?
7 Show 2-input multiplexer Understand The learner to recall the CO 4
using CMOS transmission concept of CMOS
gates transmission gates and
illustrate a 2-input
multiplexer using CMOS
transmission gates.
8 Compare clocked CMOS Understand The learner to state the CO 7
logic and n-p CMOS logic. concepts of clocked CMOS
Mention their advantages logic and n-p CMOS logic
and disadvantages and explain their
advantages and
disadvantages.
9 Explain CMOS domino Understand The learner to state the CO 7
logic and give its advantages CMOS domino logic and
and disadvantages explain its advantages and
disadvantages

Page 16
10 Show three input nand and Understand The learner to recall the CO 4
nor gates in pseudo nMOS concepts of pseudo nMOS
Logic and elaborate the logic and infer it using
operation three input nand and nor
gates.
PART-C SHORT ANSWER QUESTIONS
1 Describe the effect of Understand The learner to recall the CO 5
resistance of a wire on delay concept of effect of
resistance of a wire on delay
and describe it in detail
2 Write the equation for Mean Understand The learner to write the CO 6
time to Failure (MTTF) equation and explain the
terms in detail.
3 Explain the advantage of Understand The learner to recall the CO 7
pseudo n-MOS logic various types of nMOS
compared to n-MOS logic ? logics and explain the
advantage of pseudo nMOS
logic over nMOS logic.
4 What is fall time in digital Remember - CO 2
circuits
5 State the formula for Remember - CO 7
n-MOS inverter pair time
delay
6 State the formula for Remember - CO 7
p-MOS inverter pair time
delay
7 Explain fringe field Understand The learner to recall the CO 7
capacitance concept of field capacitance
and explain it in detail.
8 Explain interlayer Understand The learner to recall the CO 7
capacitance concept of interlayer
interference and explain it
in detail.
9 Explain peripheral Understand The learner to recall the CO 7
capacitance concept of peripheral
capacitance and explain
the concept in detail
10 Compare fan-in and fan-out Understand The learner to recall the CO 7
concepts of fan-in and
fan-out and compare
both with the help of
different parameters.
CIE-II

Page 17
1 Draw the standard Remember - CO 4
configuration of any logic
circuit in C MOS logic
2 Draw the standard Remember - CO 4
configuration of any logic
circuit in NMOS logic
3 Compare dynamic and Understan The learner to state the CO 7
static CMOS logic? dynamic and static CMOS
logic and compare them.
4 Describe dynamic CMOS Understand The learner should recall CO 7
logic? the concept of dynamic
CMOS logic and
demonstrate the concept
in a detailed manner
5 Describe the disadvantages Understand The learner should state CO 7
of dynamic logic the concept of dynamic
logic and explain the
disadvantages.
6 What are the causes of Remember - CO 7
dynamic power dissipation
7 Why single phase dynamic Remember - CO 7
logic structure cannot be
cascaded?
8 How total power Remember - CO 2
consumption is calculated
9 Define leakage power Remember - CO 2
consumption
10 Define switching power Remember - CO 2
consumption
MODULE IV
DATA PATH SUBSYSTEMS
PART A- PROBLEM SOLVING AND CRITICAL THINKING QUESTIONS
1 Demonstrate how Understand The learner to recall the CO 10
Manchester carry chain concept of Manchesther
enhances speed of operation carry chain and illustrate
? how it enhances the speed
of operation.
2 Compare 4 x 4 barrel shifter Understand The learner to state the CO 10
with normal shifter and operations of barrel shifter
explain the operation and normal shifter and
compare the operations
based on various
parameters.

Page 18
3 Model the carry expression Apply Learner to describe the CO 10
in carry look ahead adder boolean addition and
construct the carry look
ahead adder.
4 Illustrate the operation of Understand The learner to recall the CO 10
parity generator with the concept of logic and stick
help of logic and stick diagrams and illustrate the
diagrams operation of parity
generator with the help of
them.
5 Explain how read 0 Understand The learner to state how CO 11
operation is destructive in the read 0 operation is
DRAMs and corrective destructive and
measures demonstrate the
corrective measures.
6 Compare Serial-Parallel Understand The learner to textbf recall CO 10
multiplier with Parallel the concepts of multipliers
multiplier and compare the
serial-parallel multiplier
with parallel multiplier
using different parameters.
7 Demonstrate how data is Understand The learner to recall the CO 11
retained in EPROMs with concept of EPROMS and
double gate technology demonstrate how the data
is retained using double
gate technology.
8 Describe the role of the Understand The learner to state the CO 11
precharge circuit in concept of precharge circuit
memories and what are it’ in memories and illustrate
advantages ? its advantages.
9 Identify how counting delay Apply Learner to compare CO 10
is minimized in synchronous various the counters
counters multiplication and identify
the causes.
10 Interpret the similarity Understand The learner to recall the CO 11
between comparator and concept of comparators and
zero detectors zero detectors and outline
the similarities between the
two.
PART-B LONG ANSWER QUESTIONS
1 What is Manchester carry Remember - CO 10
chain? How it speeds up
addition operation?

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2 Construct the circuit of 4 x Apply Learner to textbf recall CO 10
4 barrel shifter and explain nMOS inverter, then
the operation describe the shifters and
develop the barrel shifter
3 How generate and Remember - CO 10
propagate concepts are used
in carry look ahead adder to
speed up the carry chain ?
Elaborate
4 Describe carry select adder Understand The learner to state the CO 10
with functional diagram functioning of carry select
adder and textbf
demonstrate it with a
proper functional diagram.
5 Write about implementation Remember - CO 10
of ALUs and Comparators
6 Explain parity generator Understand The learner to textbf recall CO 10
with the help of stick the concept of a parity
diagram generator and illustrate it
with the help of a stick
diagram
7 What is comparator? Show Remember - CO 10
its’ implementation
8 Describe Zero detector and Understand The learner to textbf state CO 10
four bit ripple carry adder the concept of Zero detector
and four bit ripple carry
adder, and demonstrate
their functioning.
9 Construct the block Apply Learner to describe the CO 10
diagram of Serial Parallel boolean multiplication and
multiplier and elaborate it’s textbf construct the
operation multiplier
10 Outline 4-bit synchronous Understand The learner to state the CO 10
Up-Counter with JK functioning of 4-bit
Flip-Flops. synchronous Up-Counter
and textbf outline it by
using JK Flip-Flops.
11 What is 3T DRAM cell ? Remember - CO 11
Explain read, write and
store operations
12 Draw the 6T SRAM cell Remember - CO 11
and elaborate read, write
and store operations

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13 Differentiate between Understan The learner to describe the CO 11
NAND and NOR based NAND and NOR based
ROMs ROMs and contrast the
both by verifying various
parameters.
14 Classify serial access Understand The learner to recall the CO 11
memories and discuss their concepts of serial access
configurations memories and textbf classify
their
15 Outline 4-bit asynchronous Understand The learner to textbf state CO 10
Up-Counter with T the functioning of 4-bit
Flip-Flops asynchronous Up-Counter
and illustrate it by using T
Flip-Flops.
16 Construct the block Apply Learner to describe the CO 10
diagram of Braun Array boolean multiplication and
multiplier and elaborate it’s construct the Braun
operation multiplier
17 Outline 4-bit synchronous Remember - CO 10U
Up-Counter with T
Flip-Flops.
18 Compare 1T and 2T DRAM Understand
The learner to recall the CO 11
memories with circuit concept of DRAM memories
diagrams and compare 1T and 2T
DRAM memories by
verifying various
parameters.
19 Outline 4-bit asynchronous Understand The learner to state the CO 10
Up-Counter with JK functioning of 4-bit
Flip-Flops. asynchronous Up-Counter
and illustrate it by using
JK Flip-Flops.
20 Explain double gate concept Understand The learner to recall the CO 11
used in flash memories concept of flash memories
and demonstrate the
concept of double gate used
in flash memories.
PART-C SHORT ANSWER QUESTIONS
1 What is bit-sliced design? Remember - CO 10
2 What are different Remember - CO 10
data-path operators?
3 Draw the logic diagram for Remember - CO 10
even parity generator

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4 State the expression for Pk Remember - CO 10
in Carry look ahead adder
5 Draw asynchronous counter Remember - CO 10
using JK flip flop
6 Infer the disadvantage of Understand The learner to textbf CO 10
ripple carry adder describe the ripple carry
adder and infer its
disadvantages.
7 Draw 4 bit ripple carry Remember - CO 10
adder functional diagram
8 Compare SRAM and Understand The learner to state the CO 11
DRAM memory elements SRAM and DRAM memory
elements and compare
both using several
parameters and conditions.
9 What is 1T (one transistor) Remember - CO 11
DRAM cell?
10 List the disadvantages of 1T Remembe - CO 1
(one transistor) DRAM cell
2 Draw 2T (two transistor) Remember - CO 11
DRAM cell
12 Show the pre-charge circuit Remember - CO 11
of SRAM cell
3 Draw the SRAM Remember - CO 11
6T(6Transistor) cell
4 How operation read is done Remember - CO 11
in SRAM?
5 How write operation is done Remember - CO 11
in SRAM?
6 Explain Standby Mode in Remember - CO 11
SRAM
7 What are the disadvantages Remember - CO 11
of 2T (two transistor)
DRAM cell ?
8 Draw synchronous counter Remember - CO 10
using JK flip flop
9 State the expression for Gk Remember - CO10
in Carry look ahead adder
10 Draw asynchronous counter Remember - CO 10
using JK flip flop
MODULE V
LOGIC DESIGN AND TESTING STRATEGIES
PART A-PROBLEM SOLVING AND CRITICAL THINKING QUESTIONS)

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1 Show the following Understand The learner to recall the CO 8
functions using PLA concept of PLA and
F1=AB’C’+AB’C+ABC; interpret the given
F2=A’BC+AB’C+ABC functions using PLA.
2 Show JK flip flop using PLA Understand The learner to describe CO 8
the concept of PLA and
demonstrate it using JK
flip flop.
3 Implement 4 to 2 encoder Understand The learner to recall the CO 8
using PROM, Draw the concept of PLA and
truth table and interpret the given
implementation diagrams functions using PROM
4 Show the following functions Understand The learner to recall the CO 8
using PLA F1=A’B’+C; concept of PLA and
F2=A’BC+AB’C, F3= interpret the given
A’B’C’ functions using PLA.
5 Implement 2 bit comparator Understand The learner to recall the CO 7
using PROM, Draw the concept of PLA and
truth table and interpret the given
implementation diagrams functions using PROM
6 Model the sequential circuit Apply The learner to outline CO 11
with n inputs and q outputs sequential circuits and
with m feed- back lines. Identify the quantity of
Assess how many test test vectors
vectors are needed
7 Outline how layout design Understand The learner to recall the CO 11
can be done for improved concept of layout design and
testability explain the measures for
improving testability .
8 Outline the issues to be Understand - CO 11
considered while
incorporating BIST in
Chipdesin
9 Show the following functions Understand
The learner to recall the CO 8
using PLA F1=AB+C; concept of PLA and
F2=A’BC+AB’C interpret the given
functions using PLA.
10 Show the following Understand The learner to recall the CO 8
functions using PAL concept of PAL and
F1=(A’+B+C) (A+B’+C) interpret the given
functions using PLA.
PART-B LONG ANSWER QUESTIONS

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1 Draw and explain the Remember - CO 8
functional block diagram of
CPLD with its applications
2 Differentiate the properties Understand The learner to recall the CO 8
of full custom and semi design properties and
custom design. contrast between the
properties of full custom
and semi-custom design.
3 Describe and differentiate Understand The learner to state the CO 8
the properties of full custom properties of full custom
and semi-custom design and semi-custom design and
contrast between them.
4 Outline the design style Understand The learner to textbf recall CO 8
classification of the concept of Semi custom
Semi-custom design ASICs design ASIC’s and textbf
outline its design style
classification
5 Describe and compare Understand The learner to recall the CO 8
between channeled gate concept of gate arrays and
array and channel less gate compare channelled gate
array array and channel less gate
array using various
parameters.
6 Describe the features of Understand CO 7
FPGA with functional block
Diagram
7 Illustrate Boolean function Understand The learner to state the CO 8
realization using PLA with features of FPGA and
two examples demonstrate its features
using a functional block
diagram.
8 Illustrate an boolean Understand The learner to describe CO 8
function realization using the concept of boolean
PAL with an example function realization with a
PAL and illustrate the
concept with an example.
9 Explain Channel-less gate Understand The learner to describe CO 8
arrays with neat sketches gate arrays and explain
the Channel-less gate
arrays.
10 The learner to describe gate Understand The learner to describe CO 8
arrays and explain the gate arrays and textbf
Channel-less gate arrays. explain the Channelled
gate arrays.

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11 Draw and explain the Understand The learner to describe gate CO 8
functional block diagram of arrays and explain the
FPGA with its applications FPGA applications
12 Explain Controllability, Understand The learner to recall the CO 11
Observability and Fault faults causing wrong output
Coverage and explain how these
faults can be
monitored/controlled
13 Describe various categories Understand The learner to recall CO 11
of DFT Techniques testing methods and
explain importance of DFT
14 Outline ASIC design Understand The learner to textbf recall CO 8
aspects in VLSI with the chip design strategies
necessary diagrams. and outline the properties
of ASIC
15 Compare Semi custom and Understand The learner to recall the CO 8
Full custom design in terms chip design strategies and
turnaround time and time contrast between the
to market parameters properties of full custom
and semi-custom design.
16 Compare between Understand The learner to recall CO 11
Functional Test and testing methods and
Manufacturing Tests compare Functional Test
and Manufacturing Tests
17 Explain the advantages of Understand The learner to recall CO 11
BIST compared to external testing methods and textbf
testing for SoC Explain the advantages of
BIST
18 Demonstrate Understand The learner to recall the CO 11
Stuck-at-Faults in 6T faults causing wrong output
SRAM cell and explain how output
gets stucked
19 Classify PLDs with Understand The learner to recall logic CO 8
functional diagrams and gates and Classify PLDs
Explain PLA with neat
sketch
20 Classify PLDs with Understand The learner to recall logic CO 8
functional diagrams and gates and Classify PLDs
Explain PAL with neat
sketch
PART-C SHORT ANSWER QUESTIONS
1 What are the advantages of Remember - CO 7
PLAs ?

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2 How four input AND gate is Remember - CO 8
represented in PLA
3 What is Channelled Gate Remember - CO 8
Array?
4 How four input OR gate is Remember - CO 8
represented in PLA
5 Describe Channel-less Gate Understand - CO 8
Array
6 Recall important elements Remember - CO 8
of FPGA
7 Show PAL with a neat Remember - CO 8
block diagram
8 Show PLA with a neat Remember - CO 8
block diagram
9 Recall important elements Remember - CO 8
of CPLD
10 Show PAL with a neat Remember - CO 8
block diagram
11 Show PLA with a neat Remember - CO 8
block diagram
12 What is the role of LUT in Remember - CO 8
FPGA
13 Explain Stuck- at -one Fault Understand The learner to recall the CO 11
faults causing wrong output
and explain how output
always remains at logic level
1
14 Explain Stuck- at -zero Understand The learner to recall the CO 11
Fault faults causing wrong output
and explain how output
always remains at logic level
0
15 Describe Stuck-at-open Understand CO 11
Fault
16 Explain How AND gate can Understand The learner to recall the CO 11
tested for SAT faults faults causing wrong output
and explain how output
gets stucked
17 Explain How OR gate can Understand The learner to recall the CO 11
tested for SAT faults faults causing wrong output
and explain how output
gets stucked

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 18 How EX-NOR gate can be Remember - CO 11
tested for SAT faults
19 What is BIST role in testing Remember - CO 11
of SOC
20 How EX-OR gate can be Remember - CO 11
tested for SAT faults

Course Faculty : HOD ECE

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