DIGITAL DESIGN

FOR THE LABORATORY SIMULATION LABS

1SIMULATION LAB 1: HALF ADDER, INCREMENT &

TWO'S COMPLEMENT CIRCUIT

Prerequisites: Before beginning this laboratory experiment you must be able to:
• Use LogicWorks™.
• Interpret and construct schematic diagrams from Boolean algebraic expressions using
AND/OR/NOT logic gates.

Equipment: Personal computer and LogicWorks™.

Objective: In this experiment you will gain some experience building and debugging combinational
logic circuits using LogicWorks™.

Outcomes: When you have completed the tasks in this experiment you will be able to:
• Describe the truth tables that characterize the addition of two single bit numbers.
• Write the Boolean algebraic expressions that characterize the sum and carry functions for the
half adder.
• Build and debug a simulation of a circuit that will perform the half-adder operation.
• Build and debug a simulation of a circuit that will perform the 4-bit increment operation.
• Build and debug a simulation of a circuit that will perform the 2's-complement operation.

Lab Report Guidelines

Before you begin this laboratory exercise, make sure you understand the reporting requirements your
instructor has specified. If you understand the reporting requirements then you will know the observations
that are important to record in your lab notebook and the tests that need to be performed on the circuits you
construct. For this lab, it is recommended that you use a task-oriented format when organizing your lab
report. (If your instructor is using the report writing guidelines contained in this manual, you can review
them by clicking on the blue text: Task-Oriented Report Writing Guidelines.)

Prologue
The exercises contained in this software manual are meant to lead you step-by-step through the
construction of an elementary microprocessor. At this point in your digital design course, this may seem

©1999 Daniel J. Tylavsky

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like an immense feat, but don't worry, we'll take it one step at a time, and before you know it, you'll have
constructed the complete simulation. Some people feel overwhelmed by the prospect of having to "build a
complete microprocessor." Let me assure you that more than 4,000 students, with no knowledge of digital
circuits, have started these laboratory exercises (while taking a course in digital design) and completed
them successfully – and you will too!

To complete the microprocessor design, you will need to complete the first five software labs in this
manual. In each of the first five laboratory exercises, you will either build pieces that will make up your
microprocessor, or put the pieces together to form major subunits of your microprocessor. In the first two
laboratory exercises, you will systematically design and simulate some elementary functions from AND,
OR, NAND, NOR, and NOT gates that will be building blocks for subsequent exercises. In the third
laboratory exercise, you will combine the circuits built in exercise 1 and 2 to form an Arithmetic and
Logical Unit (ALU), which handles all the data manipulation operations in a microprocessor. In laboratory
exercise 4 you will add memory and other simple circuitry to your ALU, to form a ‘brainless’
microprocessor. You will act at the brains of this microprocessor and control it to perform actions on
stored data. In the fifth laboratory exercise, you will add control circuitry to complete your microprocessor
design.

Beyond the first five exercises, there are two additional software laboratory exercises included in this
manual. These are more advance exercises that allow you to enhance the functionality to your
microprocessor.

As you work your way through these simulation exercises, notice that a large fraction (greater than 95%) of
all the devices used are AND/NAND, OR/NOR, or NOT gates. At the completion of these exercises it is
hoped that you will realize that all digital computers are merely complex combinations of these simple
primitive logic devices.

In these exercises you are asked to build a simulation of a microprocessor rather than a hardware
realization. Building a hardware realization of the microprocessor as prescribed in these exercises from
discrete IC's (integrated circuits) requires several hundred IC's. The complexity of wiring together several
hundred IC’s puts a hardware realization beyond the scope of an introductory laboratory exercise. Further,
when any circuit of this degree of complexity is to be constructed, a simulation of it is always completed
first. Simulating a design before building it with hardware allows the conceptual design to be easily,
reliably, and quickly built, tested, and modified. In practice, all complex systems are simulated before they
are built. It is hoped that as you build the simulations in the subsequent laboratory experiments you will
define for yourself the role that simulation plays in the construction of any large complex system.

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Introduction
In this laboratory exercise you will be building three circuits from primitive logic gates that will provide
part of the functionality of a complete microprocessor. These circuits will allow you add two 1-bit1
numbers (i.e., the half-adder function), increment a 4-bit number2, and perform the two's complement
operation on a 4-bit number. In this exercise you will also be modularizing the circuits you build so that
they can be easily used and their functions easily understood. Creating modules from complex circuits and
using these modules to create more complex modules is a powerful concept that will allow you to create
complex circuits whose modularized diagrams can easily be interpreted and used.

Pre-Lab Knowledge
In your lectures you have been introduced to primitive logic devices such as AND, OR, NAND, NOR, and
NOT gates. If you are still unsure about the input/output relationships associated with these gates or how to
construct a schematic diagram from a Boolean algebraic expression, refer to Hardware Lab 1: Debugging a
Half and Full Adder or your textbook.

Half Adder
The microprocessor we wish to design will need the capability of adding binary numbers. In this
laboratory exercise we will build a simple arithmetic circuit known as a half adder. The half adder is used
to add two 1-bit binary numbers and produce a sum and carry output. (If you have completed Hardware
Lab 1 or have studied how to create a schematic diagram for a half adder, you may wish to skip the next
section on Binary Addition.)

Binary Addition
Using “B” to denote binary numbers (as opposed to "D" for decimal numbers), the addition of two 1-bit
binary numbers is defined by the following equations:

1 (Carry)

0B 0B 1B 1B

+0B +1B +0B +1B

00B 01B 01B 10B

Carry Bit Sum Bit

1
Bit is the shortened form of the expression “Binary Digit.”
2
Your completed microprocessor will operate on 4-bit numbers or operands. Typical microprocessors operate on 8-, 16-, or 32-bit
operands. We choose 4-bit, rather than 32-bit, operands because there is no conceptual insight gained by using large (e.g., 32-bit)
operands. There is, however, significant advantage gained when using 4-bit circuitry; it is much less tedious to construct and debug.

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The only equation above that may be difficult to justify is 1B + 1B = 10B – let’s justify it. In the binary
system, the symbol with the largest value is 1B, in the base-ten system the largest symbol is 9D. When we
add two numbers in the base-ten system whose sum exceeds our largest symbol, we generate a carry of 1D
to the next more significant position. Similarly, when we add two numbers in the binary number system
whose sum exceeds our largest symbol, 1B, we generate a carry of 1B. This carry is added to the numbers
residing in the more significant position (which are 0’s in our example). If we assign the most significant
bit of our 1-bit addition to be the carry (CRY) bit and the least significant bit to be sum (SUM) bit, we can
represent the addition operation of two one-bit operands, A and B, using the binary-valued, addition-
definition table of Figure 1-1. With digital logic gates we simulate truth values, not binary numbers;
however, (and this is a subtle yet important isomorphism), if we reinterpret the binary values of Figure 1-1
as truth (or logical) values, then we get the truth table of Figure 1-2– and we do know how to simulate truth
values with digital logic gates!

A B A+B A B CRY SUM

0B 0B 00B 0 0 0 0
0B 1B 01B 0 1 0 1
1B 0B 01B 1 0 0 1
1B 1B 10B 1 1 1 0

Figure 1-1. Half-adder definition table. Figure 1-2. Half-adder truth table.

To build a circuit that will add two 1-bit numbers, A and B, and give a 2-bit result, we will need to build
the two digital logic functions defined in Figure 1-2, the SUM and CRY. There are two common
canonical3 forms we can use to realize these two functions: Sum-of-Products (SOP) and Product-of-Sums
(POS) canonical form.

Let’s use the SOP canonical form to realize the SUM function of Figure 1-2. To do this, define two
auxiliary functions, K and L, whose values are 1 for one and only one of the input combinations that cause
the SUM function to be 1. These auxiliary functions are shown in Figure 1-3. If we OR the K and L
functions together we get the result K+L4 shown in the truth table of Figure 1-3. By inspection we can see
that SUM = K+L. This means that if we can realize the K and L functions, we can realize the SUM
function as the OR combination of K and L. By inspection we can see that we want K to be 1 when A=0
and B=1. Clearly, this will be the case if we set K = A • B . Further, K must be equal to 1 ONLY when
A=0 and B=1. The function K = A • B is consistent with that requirement; hence K can be realized using

3
A canon is a fundamental law or axiom. A canonical form is a form that is in some sense fundamental. The forms we use here are
canonical in the sense that each AND or OR term contains every variable used in defining the function.
4
We will use the standard Boolean algebraic notation in which “+” is used to indicate the OR operation, “•” is used to represent the
AND operation, and an over-bar “” is used to indicate a NOT (inverting or complementing) operation.

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the circuit shown in Figure 1-3. Similarly, the function L must equal 1 when and only when A=1, and B=0.
By inspection, the function L = A • B meets this requirement and can be realized using the circuit of
Figure 1-3. If we connect the functions K and L to the inputs of a 2-input OR gate of Figure 1-3, we get the
SUM function that we want. This circuit is the hardware equivalent to the Boolean algebra expression

SUM = A B + AB .

A
K = AB
A B K L B
0 0 0 0
0 1 1 0
1 0 0 1
1 1 0 0 A
L = AB
B

A
A B K L SUM = K+L K=AB
0 0 0 0 0
0 1 1 0 1 SUM
1 0 0 1 1
1 1 0 0 0 L=AB
B

Figure 1-3. SOP implementation of sum for 1-bit half adder.

Similarly the CRY (carry) output can be expressed using the canonical SOP and canonical POS forms. The
SOP form, as shown in Figure 1-4, requires only one logic (AND) gate for its realization. (Verify for
yourself that this schematic diagram describes a circuit that could be used to realize CRY.)

A B CRY
0 0 0
A
0 1 0 CRY = AB
B
1 0 0
1 1 1

Figure 1-4. SOP implementation of CRY for 1-bit half adder.

Building the Half Adder

The circuit realizing the SUM and CRY functions that define the 1-bit half adder is shown in Figure 1-5.

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1-Bit Half-Adder Circuit

Truth Table A
K=AB
A B CRY SUM
0 0 0 0
OUT
0 1 0 1
1 0 0 1
L=AB
1 1 1 0 B

CRY

Subcircuit Symbol

A OUT
HA_1
B CRY

Figure 1-5. HA_1: 1-bit half adder.

Task 1: Build and Test the 1-Bit Half-Adder

Use LogicWorks™ to build and test the 1-bit half-adder circuit as shown in Figure 1-55. (If you are not sure
how to use LogicWorks™ refer to Simulator Tutorial: Using LogicWorks™ 4 for Windows® or
Macintosh®.) To test this circuit, place switches on the inputs (A and B) and put binary probes on the
outputs (SUM and CRY). Toggle the input switches through every (A, B) combination and compare the
SUM and CRY outputs observed from the binary probe with those prescribed by the truth table of Figure
1-5. Record the results of these tests in your notebook. If the outputs your circuit generates agree with the
outputs specified by the truth table of Figure 1-5, then your circuit is working correctly. If they do not
agree, you have a problem with your circuit and you need to check that the connections have been made
correctly. A useful trick is to click on a wire. The entire wire should be highlighted. If parts of it are not,
you do not have the wire properly connected. The debugging procedures discussed in Hardware Lab 1 may
also be of use here if the results of your circuit tests indicate a problem. If you cannot detect the source of
an error in your circuit after using the debugging techniques of Hardware Lab 1, see a laboratory teaching
assistant (laboratory assistant) for help. Once you are convinced that your circuit is working properly, save

5
There are other circuits that will realize the half adder. For now, build the assigned circuits using the designs contained in the
schematics provided. In many cases, we will be building upon and modifying these circuits. If you create designs of your own, you
may find it difficult to incorporate later modifications. As you progress in these simulation exercises, you will have many
opportunities to create your own designs.

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your file. Give the file a meaningful name such as ha_1.cct. This will help you keep track of your files.
Remember: always keep backup copies of all your circuits and any libraries you create6.

Having created the half-adder circuit, the next step is to document your work. Do this by removing the
switches and probes from the circuit. Then carefully label the inputs and outputs. (Refer to Simulator
Tutorial: Using LogicWorks™ 4 for Windows® or Macintosh® for instructions on labeling wires and pins.)
You can test your label by selecting the wire, i.e., clicking on it. Selecting the wire will highlight the wire
and everything connected to it. If the label is properly attached to the wire, the label will also be
highlighted. You can name inputs and outputs anything you want except "0" and "1". LogicWorks™
interprets "0" and "1" as denoting logic levels. Re-save your circuit after you have labeled the inputs and
outputs.

Task 2: Imbed the 1-Bit Half Adder in a Subcircuit

After you have built and tested the circuit, the next task is to imbed it in a module known as a subcircuit.
Imbed your half-adder circuit in a subcircuit using the subcircuit symbol shown in Figure 1-5. (To do this,
you will have to remove the binary switches and probes you used in testing your circuit (if you have not
done so already) and place properly configured input/output ports symbols on the input/output lines
respectively. Then follow the directions for creating a subcircuit described in Simulator Tutorial: Using
LogicWorks™ 4 for Windows® or Macintosh®.) Label your subcircuit ‘HA_1’. ‘HA’ stands for ‘half
adder’ and the ‘1’ indicates that the circuit operates on 1-bit operands. (In subsequent laboratory exercises
you will build circuits that operate on binary numbers with multiple bits; hence, it is important to specify
the bit length in labeling each subcircuit so that the length of the operands accepted by each subcircuit can
be determined simply by observing the label.) After you have created the subcircuit, test the circuit using
the same procedure describe above. (I.e., place binary switches on the inputs of the subcircuit, binary
probes at the outputs, and compare the output values obtained from your circuit with those contained in the
truth table of Figure 1-5 for every combination of A, B inputs.) If the subcircuit does not work correctly,
retrace your steps and try to debug your circuit. Ask a laboratory assistant for help if you need it. Once
you are convinced that your circuit is working correctly, add the subcircuit to your library7.

Creating subcircuits is an important technique universally used in the creation of digital circuits. A
subcircuit allows us to suppress the details of how a circuit operates and instead understand the subcircuit at
the function level. By suppressing the internal details, subcircuits also greatly simplify schematic
diagrams. We will see that as our circuits grow in complexity, using subcircuits is not only important but
also necessary. For complex circuits, getting an overview of how the circuit functions without the use of

6
Remember hard drives and networks crash often. If for some reason, you lose your files on your hard disk, you may have to recreate
them in a short time to meet the laboratory report deadline; hence you should keep updated back-up copies of all of the LogicWorks™
circuits and libraries you create in these laboratory exercises.
7
Recall you created your own library when you completed the Simulator Tutorial: Using LogicWorks 4 for Windows® or
Macintosh®.)

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subcircuits is next to impossible. The subcircuit symbols we create in this exercise will be used in
schematics in subsequent laboratory exercises. If you keep your notation the same as we use here, you will
have no problem using and combining your subcircuits using the schematic diagrams in subsequent
laboratory exercises. So, for your own sake, follow the notation used in this lab manual. Appendix A:
LogicWorks™ Subcircuit Symbols gives a summary of the notation used with the different subcircuits that
you will be creating in these laboratory exercises.

The Increment Circuit

An arithmetic operation that our microprocessor will use in its program-counter circuitry is the increment
operation. The increment circuit we will need must add 1 to a 4-bit number8. Let’s first design the simpler
2-bit increment function. Represent a 2-bit binary number A, with the most and least significant bits being
A1 and A0 respectively. To add 1 to A, we need to add 1 to A0, getting the result Y0, plus a carry, C0, as
shown in Figure 1-6. (This carry bit, C0, may be a 1 or a 0.) The carry is added to A1 to yield the result
Y1 and another carry CRY. Since we are incrementing a 2-bit number, the carry, CRY, represents the most
significant bit of the 3-bit result.

C0 _1
A1 A0
CRY Y 1 Y0

Figure 1-6. Incrementing a two-bit number.

In practice when we use this increment operation, sometimes we will be incrementing A by 0. Since
A+0=A (here the “+” signs means plus), any circuitry we design to perform the increment operation must
give the correct result whether we are incrementing by 1 or 0.

To implement the 2-bit increment function, we will divide the operation conceptually into two functions:
we will use one subcircuit to implement the addition of the increment value and the least significant bit, and
another subcircuit to add C0 and A1. The subcircuit that implements each of these functions is the half
adder created in Task 2. Justify to yourself that connecting the half-adder subcircuits as shown in Figure
1-7 will perform the 2-bit increment function, where the INC input is the increment value.

In a similar fashion we can use four half adders to implement a 4-bit increment circuit. A 4-bit increment
circuit will accept a 4-bit binary number as its operand and be controlled by the increment control. (Label

8
Remember that we’re building the simulation of a microprocessor that will operate on 4-bit operands and use 4-bit address values.

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the increment control as INC in your design). Your circuit will produce a 4-bit binary number and a carry
as output. If the input control, INC, is low, the output number will be the same as the input number. If the
input control is high, the output will be one more than the input.

Task 3: Build a 4-Bit Increment Circuit

Using your understanding of the increment function and the 1-bit half adder, build a 4-bit increment circuit
using four 1-bit half adders. Once you finish constructing the increment circuit using half-adder
subcircuits, imagine what your circuit would look like if you did not construct it from subcircuit blocks.
Your design is a good example of how we will use simple subcircuits to create more complicated circuits.

A0 A SUM Y0
HA_1
INC B CRY

A1 A SUM Y1
HA_1
B CRY CRY

Figure 1-7. 2-bit increment circuit.

Task 4: Test the 4-Bit Increment Using Hex Numbers

By now you may have noticed the pattern of tasks used in creating circuits: first build the circuit, next test
the circuit and (in many cases) imbed the circuit in a subcircuit. Let’s test the 4-bit increment circuit you
constructed in Task 3. Determining the minimum number of tests needed to guarantee that a circuit is
working properly is a difficult problem – and beyond the scope of an introductory course. An alternative
testing technique is to observe the output for every input combination. Successful completion of such an
exhaustive test applied to any circuit will guarantee that it is operating correctly.

The increment circuit you built in Task 3 operates on a 4-bit operand. In LogicWorks™, a convenient way
to simulate a 4-bit operand and observe a 4-bit output is to use the hex keyboard and the hex display. Test
your 4-bit increment circuit by connecting the four output lines of the hex keyboard to the four inputs of
your 4-bit increment circuit. Similarly, connect the hex display to the four output bits of the 4-bit
increment circuit and verify that the 4-bit increment circuit works in the desired fashion using hex
arithmetic to check your results9. Note that this requires 32 tests. (Why?) Record your test results and

9
If you are not familiar with the hexadecimal number system, review the Hexadecimal Numbers section in Simulator Tutorial: Using
LogicWorks 4 for Windows® or Macintosh®.)

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include them in your report. (If you’re not sure how to use the hex keyboard or hex display, review
Simulator Tutorial: Using LogicWorks™ 4 for Windows® or Macintosh®.)

If you are not getting the results you expect, there may be one of two problems: either your circuit is
constructed incorrectly, or you are using the hex keyboard or display incorrectly. The latter is usually the
case. Remember that the side of the hex keyboard with the single output line10 is adjacent to the LSB.
Also remember that the hex display is designed such that the signal supplied to the pin nearest the “dot” is
interpreted as the LSB.

Task 5: Imbed 4-Bit Increment Circuit in a Subcircuit

Once your circuit works correctly, delete the hex keyboard and hex display. Then put the 4-bit increment
circuit in a subcircuit using the symbol shown in Figure 1-8, label it “INC_4” and include it in your library.

INC_4
A3 Y3
A2 Y2
A1 Y1
A0 Y0
INC CRY

Increment

Figure 1-8. 4-bit Increment subcircuit symbol.

Task 6: Use INC_4 to Perform Two’s-Complement Operation

In the course associated with this laboratory, you will learn about the use of the two’s-complement number
system as a way of representing both positive and negative binary numbers in such a way that the sign of
the number becomes an integral part of the representation of the number. Most computer arithmetic is
performed using numbers in two’s-complement form – our microprocessor will be no different. In our
microprocessor, we will want the capability of negating two’s-complement numbers; negation of two’s-
complement numbers is handled by complementing each bit of the number and adding 1 to it. The circuit
shown in Figure 1-9 uses the increment subcircuit you created in Task 5 along with four inverters to
perform the two's-complement operation.

Note that by connecting the ‘INC’ input in Figure 1-9 to +5 Volts, the circuit will always perform the
two’s-complement operation. Build the circuit in LogicWorks™ and verify that it performs the two's-
complement operation. In our earlier test of the increment circuit, we exhaustively tested every input
combination. As you gain experience building and testing circuits you will realize that once a circuit works

10
Also remember that we will not be connecting this output line to any devices in the simulations described in this manual

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correctly for certain input combinations, it is likely to work correctly for all input combinations. It is left to
you to decide what constitutes a sufficient set of tests to make it likely that the two’s-complement circuit is
operating correctly. The test should be thorough enough to prove that the circuit works beyond reasonable
doubt. One set of test inputs is not enough to test the circuit. Justify in your report why successful
completion of your tests makes it likely that your circuit is operating correctly. (Hint: Be sure to test the
carry). Remember to record the details of your tests in your report.

INC_4
A3
A2 A3 Y3 Y3
A2 Y2 Y2
A1 A1 Y1 Y1
A0 Y0 Y0
A0 INC CRY CRY

+5V

Figure 1-9. A circuit that performs the two’s-complement operation.

Once you have tested this circuit and have shown that it works correctly, save it. In Simulation Lab 3 you
will be modifying this circuit and using it as one part of the arithmetic and logic unit for our
microprocessor.

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2SIMULATION LAB 2: 4-BIT FULL ADDER,

MULTIPLEXER & DECODER

Prerequisites: Before beginning this laboratory experiment you must be able to:
• Use LogicWorks™.
• Use Karnaugh maps.
• Have completed Simulation Lab 1: Half Adder, Increment & Two's Complement Circuit.

Equipment: Personal computer and LogicWorks™.

Objectives: In this experiment you will build and debug combinational logic subcircuits that perform
arithmetic operations and data routing using LogicWorks™.

Outcomes: When you have completed the tasks in this experiment you will be able to:
• Design, build, test, debug, and imbed in a subcircuit, a POS or SOP form of a full adder.
• Design, build, test, debug, and imbed in a subcircuit, a 4-bit full adder.
• Design, build, test, debug, and imbed in a subcircuit, a 2-to-1 multiplexer.
• Design, build, test, debug, and imbed in a subcircuit, a 4-bit, 2-to-1 multiplexer.
• Design, build, test, debug, and imbed in a subcircuit, a 1-to-2 decoder.
• Design, build, test, debug, and imbed in a subcircuit, a 2-to-4 decoder.
• Design, build, test, debug, and imbed in a subcircuit, a 4-to-16 decoder.

Lab Report Guidelines

Before you begin this laboratory exercise, make sure you understand the reporting requirements your
instructor has specified. If you understand the reporting requirements then you will know the observations
that are important to record in your lab notebook and the tests that need to be performed on the circuits you
construct. For this lab, it is recommended that you use a task-oriented format when organizing your lab
report. (If your instructor is using the report writing guidelines contained in this manual, you can review
them by clicking on the blue text: Task-Oriented Report Writing Guidelines.)

© 1999 Daniel J. Tylavsky

DIGITAL DESIGN
FOR THE LABORATORY SIMULATION LAB 2: 4-BIT FULL ADDER, MULTIPLEXER & DECODER

Introduction
In Simulation Lab 1, you developed the increment circuit (which you will use in the program-counter
portion of the microprocessor design) and the two's-complement circuit (which you will use as part of the
arithmetic and logic unit (ALU) of the microprocessor design.) In this laboratory exercise you will
continue constructing modules that will eventually be used in assembling the microprocessor. Our concern
in this laboratory exercise is with circuits that can perform binary addition and with circuits that control the
flow of data through our system: the multiplexer and decoder. You will eventually use the data flow
control circuits you create in this lab exercise (a 2-to-1 multiplexer, a 4-to-2 multiplexer, and a 1-to-2
decoder) to make the microprocessor self-capable of routing data to appropriate locations. The binary-
addition circuitry you will create (which is a 4-bit full adder) will contribute another piece to the ALU.
Each circuit you build will be modularized by imbedding it in a subcircuit and these modules will be used
in subsequent labs to create more complex circuits. Using modules to create more complex modules is a
powerful paradigm that we will use throughout these simulation laboratory exercises.

As we progress through these laboratory exercises, you will notice that the burden of circuit design will be
shifted from this manual to you. Instead of giving you a circuit schematic and asking you to build, debug
and modularize it, we will slowly begin to ask you to do more of the design work yourself. Any design
work you are asked to do will be well within your capabilities and will be supported by material in this
laboratory manual, your textbook, and your innate ability to recognize patterns.

In the next section we will look at a systematic method for designing a half adder. Using the methodology
described in that section you will be asked to design, build, and debug a full adder. If you are familiar with
canonical methods for designing circuits, skip the next section. (Skip the next section if you have
completed Hardware Lab 1: Debugging a Half and Full Adder.)

Design of a Half-Adder Using Canonical Product of Sums

In Simulation Lab 1, we used the canonical Sum-of-Products (SOP) technique for creating Boolean
algebraic expressions and circuit schematics for a half adder. In this lab exercise, we will review the
canonical Product-of-Sums (POS) method for creating the Boolean algebraic expressions for a half adder.

A B CRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

Figure 2-1. Half-adder truth table.

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In Simulation Lab 1, we created the truth table for a half adder as shown in Figure 2-1, where SUM and
CRY represented the sum and carry outputs, respectively. In Simulation Lab 1, we used this truth table to
create the SOP realization of the half adder. To design the half adder using a POS form, let’s define two
auxiliary functions, M and N, whose values are 0 for one and only one of the input combinations that cause
the SUM function to be 0. These auxiliary functions are shown in Figure 2-2. If we AND M and N
together we get the result M•N shown in the table of Figure 2-2. By inspection we can see that SUM =
M•N. This means that if we can realize the M and N functions, we can realize the SUM function as the
AND combination of M and N. By inspection, we can see that we want M to be 0 when and only when
A=0 and B=0. Clearly, this will be the case if we set M = A + B . The function M can then be realized
using the circuit shown in Figure 2-2. Similarly, the function N must equal 0 when and only when A=1,

and B=1. By inspection, the function N = A + B meets this requirement and can be realized using the
circuit of Figure 2-2. If we connect the functions M and N to the inputs of a 2-input AND gate of Figure
2-2, we get the SUM function that we want. This circuit is the hardware equivalent to the Boolean algebra
(
expression SUM = (A + B) • A + B . )
A
M = A+B
A B M N B
0 0 0 1
0 1 1 1
1 0 1 1
1 1 1 0 A
N = A+B
B

A
A B M N SUM = MN M = A+B
0 0 0 1 0
0 1 1 1 1 SUM
1 0 1 1 1
1 1 1 0 0 N = A+B
B

Figure 2-2. POS implementation of SUM for 1-bit half adder.

Using this same technique, the POS implementation of the CRY function can be created as shown in Figure
2-3. (Verify for yourself that the circuit of Figure 2-3 also will realize the CRY function.) Clearly the POS
form requires many more logic gates and connections than the SOP form shown in Figure 2-4. (See
Simulation Lab 1: Half Adder, Increment & Two's Complement if you have forgotten how the circuit of
Figure 2-4 was created.) Which would you rather build in the lab, the SOP or POS form for the CRY?
Most of us would rather build the form that takes less time to construct and less time to debug. Industry

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likewise prefers the form with the fewest gates1 and circuits with fewer gate connections because it can be
made smaller. Circuits with fewer connections and gates have fewer pieces that can become defective.
Consequently, these circuits will perform more reliably.

A
A+B
B
A B CRY
0 0 0
A
0 1 0 A+B
B
1 0 0
1 1 1
A
A+B
B

A A+B

A+B
CRY
B

A+B

Figure 2-3. POS implementation of CRY for 1-bit half adder.

A B CRY
0 0 0
0 1 0 A
CRY = AB
1 0 0 B
1 1 1

Figure 2-4. SOP implementation of CRY for 1-bit half adder.

If we wish to design a circuit using a minimal number of gates, is there a way of knowing a priori whether
the SOP or POS canonical forms will yield the more minimal design? The answer is yes. If the function
column of the truth table has fewer 1’s than zeros, a canonical SOP form will be more minimal. If the
function column of the truth table has the same number of 1’s and 0’s, both canonical SOP and POS forms
require the same number of gates; otherwise the POS form is more minimal.

1
Circuits are not always built using the realization that requires the fewest gates for a variety of reasons. Sometimes circuits are
constructed using one gate type, and such circuits will often require more gates. Sometimes circuits are designed so that all of their
capabilities are testable; this may require more gates. Also, circuit designs that avoid glitches, (see your textbook for the technical
definition of glitch) require extra gates.

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Your textbook describes ways of obtaining a minimal two-level2 (non-canonical) realization for logic
functions. There is no simple way of knowing a priori whether the minimal (non-canonical) SOP or POS
forms will require less logic.

DeMorgan’s Laws
DeMorgan’s law and it’s dual are two of the most useful laws in Boolean algebra. The two laws are shown
in Figure 2-5. Also shown in Figure 2-5 are the gate equivalency rules, which are identical to the laws in
gate form.

Laws Gate Equivalency

A+B = A·B = =

A·B = A+B = =

Figure 2-5. DeMorgan’s laws and gate equivalency.

What the gate equivalency rules mean are:

• The performance of a NOR gate is equivalent to the performance of an AND gate with inverted
inputs. In fact, the AND gate with inverted inputs is just another way to draw a NOR gate. The
AND gate with inverted inputs is shown in Figure 2-5 as an AND gate with bubbles at the input.
This is equivalent to having inverters at the input of the AND gate. Anywhere you see a NOR
gate, you can replace it with an AND gate with inverted inputs and vice versa.
• Similarly, the performance of a NAND gate is equivalent to the performance of an OR gate with
inverted inputs. You can replace a NAND gate with an OR gate with inverted inputs, and vice
versa.
Why are DeMorgan’s laws so important? Well, using gate equivalency you can build a binary digital
circuit with only one type of gate. For example, you can build all your circuits using only NOR or NAND
gates. Sometimes this reduces the number of IC chips required to physically build a circuit with hardware.
Also, at the transistor level, it is easier to build NAND and NOR gates. At the transistor level, AND gates
and OR gates are built by adding inverters to the NAND and NOR gates respectively3.

2
All canonical POS and SOP realizations are two-level realizations; that is, the input signal must travel through two AND/OR gates
before its effect on the output can be detected. (The presents or absence of inverters is ignored in this definition.)
3
This is true for both CMOS (Complementary Metal Oxide Semiconductor) and TTL (Transistor-Transistor Logic) digital logic
families.

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Gate Equivalency Rules

You will learn formal methods of how to design circuits using only AND gates in your lectures. The
material presented here is not comprehensive. It is intended as a refresher and a memory aid.
----Delete This Section----

Figure 2-6. Gate equivalency rules.

Now, we want to build different circuits using only AND gates. To do that, we need a set of rules for
converting different gates to AND gates and inverters. After the conversion, the functioning of the circuit
with AND gates and inverters should be identical to the functioning of the original gate. Using
DeMorgan’s laws, we have already defined a set of rules for you. Figure 2-6 defines four rules for
converting different gates to circuits using only AND gates and inverters. Using DeMorgan’s laws and
Boolean algebra, you can convince yourself of the validity of these rules4.

Once you are satisfied that the rules presented in Figure 2-6 are valid, we can now build any circuit using
only AND gates and inverters given the SOP or POS forms. To do this we use a top-down approach.
When using a top down approach, the inputs to the gates may not always be variables. Sometimes they will
be functions. We can think of the “X” and “Y” in Figure 2-6 as functions and apply the rules accordingly.
Let us now build the 1-bit full-adder using only AND gates and inverters.

Designing Binary Digital Circuits Using Only AND-OR-NOT Gates

Let us build the circuit for SUM of the 1-bit half adder that we designed earlier. To build the circuit we
need to first design the SOP or POS implementation of the circuit. Then we design an AND-OR-NOT
implementation using a top-down approach. The ----Delete This Section---- form is given by ----Delete
This Section----. If we consider ----Delete This Section---- to be X and ----Delete This Section---- to be Y,
then we can use Rule B from Figure 2-6, to convert OUT to a AND circuit. This is shown in Figure 2-7(a).
Now we look at ----Delete This Section---- and ----Delete This Section---- individually and convert them to
a AND circuit using Rule A from Figure 2-6. The AND circuits are shown in Figure 2-7(b). We can now
combine the circuits shown in Figure 2-7(a) and Figure 2-7(b), to form the AND-OR-NOT implementation
as shown in Figure 2-7(c). This circuit is built using only AND gates and inverters. It performs the
function of OUT for the 1-bit full adder. Let us look at this design process again.

• First we form the POS or SOP form for the function we want to build.

• Using the rules in Figure 2-6, we can convert any gate (or function) to its AND equivalent.
(Remember that the “X” and “Y” in Figure 2-6 could be functions derived from other binary
inputs.)

4
You can also use LogicWorks™ to verify that the truth tables of the gate and the respective NOR equivalent are the same.

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• Working “backwards” (top-down approach) we can draw the AND-OR-NOT implementation

of the circuit.
----Delete This Section----

Figure 2-7. AND-OR-NOT implementation of ----Delete This Section---- form for OUT.

Let us now look at the ----Delete This Section---- form for OUT. The ----Delete This Section---- form is
given by ----Delete This Section----. Assigning ----Delete This Section---- and ----Delete This Section----
to X and Y respectively, we can use Rule A to form the AND form for OUT. This is shown in Figure
2-8(a). Then using Rule B, we can draw the AND forms for ----Delete This Section---- and ----Delete This
Section---- individually as shown in Figure 2-8(b). The combined AND-OR-NOT implementation is
shown in Figure 2-8(c). We can combine the two series inverter to get the final circuit shown in Figure
2-8(d).
----Delete This Section----

Figure 2-8. AND-OR-NOT implementation for ----Delete This Section---- form for OUT.

Task 1: Design a Full Adder Using AND-OR-NOT Gates

Using the full-adder function definition table, Table 2-1, write down the canonical POS and SOP
expressions for the Cout and SUM functions of a full adder. Choose either SOP or POS expression for the
Cout and SUM functions then build, test and debug the circuit with only AND-OR-NOT gates using
LogicWorks™. (Remember: you will need to design two circuits: one for the SUM function and one for the
Cout function. Both functions should share the same A, B and Cin inputs.) Record the results of your
validation tests in the form of a truth table in your report. In your report also be sure to explain why you
picked the POS or SOP expressions for realizing the Cout and SUM functions.

Table 2-1. Full Adder Function Definition Table.

Cin A B SUM Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Design of a Full Adder Using a Minimal SOP Form

If you have studied Karnaugh maps in the lecture portion of your course, you will be able to derive a
minimum SOP form for the full adder. Refer to your textbook or prove, using the Karnaugh map in Figure
2-9 that the Cout function is given by:

Cout = AB + BCin + CinA.

COUT SUM

AB 00 01 11 10 AB 00 01 11 10
Cin Cin

0 0 0 1 0 0 0 1 0 1
1 0 1 1 1 1 1 0 1 0

Figure 2-9. Karnaugh map for Cout function. Figure 2-10. Karnaugh map for SUM function.

If you look in Figure 2-10 at the Karnaugh map attempt to obtain a minimum SOP expression for the SUM
function, you see that we obtain no reduction beyond the canonical SOP form:
SUM = A BCin + AB Cin + ABCin + AB Cin .

A
A
B

Cin

B
B
Cin

SUM
Cin
Cin
A

Cin

Figure 2-11. Minimal and canonical SOP implementation of SUM function.

Such a realization for the SUM function requires four 3-input AND gates and one 4-input OR gate, and a
few inverters as shown Figure 2-11. Fortunately, there is a more economical method for implementing the
SUM function. Refer again to Table 2-1 and make the following observation: the SUM function equals 1
for input combinations that contain an odd number of 1’s. This is precisely the function performed by an
exclusive OR (XOR) gate shown in Figure 2-12; hence an economical way to implement the SUM function
is to use the XOR operator, i.e.,

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SUM = A ⊕ B ⊕ Cin.

The SUM function could be build using either one 3-input XOR gate (see Figure 2-12) or two 2-input XOR
gates. (To see this latter implementation, see Hardware Lab 1: Debugging a Half and Full Adder.)

A B C Y
0 0 0 0
A 0 0 1 1
B Y=A⊕ B⊕ C 0 1 0 1
C 0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Figure 2-12. 3-Input XOR schematic symbol and truth table.

SUM

B
CRY

Cin

Figure 2-13. SOP implementation of 1-bit full adder.

Task 2: Build, Debug and Test a 1-Bit Full Adder

Write the minimal POS expression for the Cout function of a 1-bit full adder. Build, debug and test a 1-bit
full-adder circuit constructed using a 3-input XOR gate to realize the SUM function and using AND-OR-
NOT gates to implement your minimal POS form for the Cout function. Imbed your 1-bit full adder in a
subcircuit (see Figure 2-14), label the subcircuit FA_1, and add it to your library. Test your subcircuit.
Record the results of these tests (in the form of a truth table) in your laboratory notebook and include the
table in your report.

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FA_1

A SUM
B Cout
Cin
1-Bit Full Adder

Figure 2-14. Subcircuit symbol for a 1-bit full adder.

A 2-Bit Full Adder

The 1-bit full-adder subcircuit you constructed in the previous task is the kernel around which we will build
the adder portion of the ALU for the microprocessor we are designing. The ALU we will design will
operate on 4-bit numbers, so we need to extend our adder from a 1-bit design to a 4-bit design. A 2-bit
design will be described here; it will be left to you to extend this to a 4-bit design.

Consider the addition of two numbers A, and B, each of which has two bits of precision. Let the postscripts
0 and 1 refer to the least and most significant bits of numbers, respectively. The addition of A0 and B0
yields a sum Y0 and carry C0, as shown in Figure 2-15. The carry C0 is added to the sum of the most
significant bits, A1 and B1 to yield a sum bit, Y1 and a carry, Cout.

Using the 1-bit full-adder subcircuit you designed in the previous task, a 2-bit full adder can be constructed
as shown in Figure 2-16. Verify for yourself that the 2-bit adder schematic will perform correctly. Note
that the 2-bit adder circuit was designed for the possibility of a carry input. (If the carry input to the adder
processing the least significant bit is not used, it may be permanently connected to ground.)

C0
A1 A0
B1 B0
Cout Y1 Y0

Figure 2-15. Two-bit number addition.

Task 3: Design, Build and Test a 4-Bit Full Adder

Using Figure 2-16 as a guide, design a 4-bit full adder. The 4-bit full adder should accept two 4-bit
numbers and a carry as input, and give one 4-bit sum and a 1-bit carry as output. Build, test and debug the
4-bit full adder. Test the circuit using hex keyboards and a hex display. Include the test results in the form
of a truth table in your report. DO NOT test all input combinations. It is left to you to decide what
constitutes a sufficient set of tests to make it likely that the 4-bit full-adder circuit is operating

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correctly.(One set of test inputs is not enough.) Justify in your report why successful completion of your
tests proves beyond a reasonable doubt that your circuit is operating correctly. Once you are satisfied that
the circuit is working correctly, imbed the 4-bit adder in a subcircuit, label it “FA_4”, and test the
subcircuit. (The subcircuit symbol we’ll use for a 4-bit full adder is shown in Figure 2-17.) Once you are
satisfied that it is working correctly, add it to your library. (Remember to record the results of all of your
tests for inclusion in your lab report.)

FA_1
A0 A SUM Y0
B0 B Cout
Cin Cin

FA_1

A1 A SUM Y1
B1 B Cout Cout
Cin

Figure 2-16. 2-bit full adder.

FA_4
A3
A2
A1
A0 Y3
Y2
B3 Y1
B2 Y0
B1
B0 Cout
Cin
4-Bit Full Adder

Figure 2-17. Symbol for 4-bit full adder.

A Multiplexer
When we discuss the architecture of the microprocessor in later laboratory experiments, we will find that
hardware is needed that allows the executing program to select the route along which data flows. One
component that we will need to perform this data routing function is the multiplexer, or MUX. A MUX is
a device that can be controlled to route one of its (possibly) many input signals and to its sole output. If a
MUX has 2n data inputs, then it must have n control (or select) inputs (which have 2n different possible
settings) to be capable of routing each input to the output. By changing the control-input values we can
select which input data stream is connected to the output. For a MUX with two data inputs, one
control/select input is necessary. A truth table and symbol for the 1-bit MUX you will build is shown in

Figure 2-18. The control/select input, “ A/ B ”, indicates that the output is identical to the A input when the

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select signal is high (1) and identical to the B input when the select signal is low (0). This MUX is called a
2-to-1 MUX because it routes one of 2 inputs to the output under select line control.

A/B A B Y
0 0 0 0
MUX_1 0 0 1 1
A
0 1 0 0
B Y
0 1 1 1
A/B
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Figure 2-18. Truth table and symbol for 1-bit MUX.

Task 4: Design, Build and Test a MUX Using AND-OR-NOT Gates

Using the Karnaugh Map methods you learned in class, design, build and test an AND-OR-NOT
implementation of the 1-bit MUX. You can design either the POS or SOP implementation. Test the circuit
and record the results as a truth table in your report. Once you are convinced that the circuit is working
correctly, imbed it in a subcircuit, test the subcircuit, label it “MUX_1”, and add it to your library.

MUX_1
A0 A
B0 B Y Y0
A/B

A/B
MUX_1
A1 A
B1 B Y Y1
A/B

Figure 2-19. 2-bit, 2-to-1 MUX.

Task 5: Build a 2-Input 4-Bit Multiplexer

Because our microprocessor operates on 4-bit numbers, it will be necessary to construct a 4-bit, 2-to-1
MUX. The 4-bit MUX should select one of two 4-bit numbers with a single control line and the selected
number should appear on the output. A 2-bit 2-to-1 MUX is shown in Figure 2-19. Expand on this figure
to design a 4-bit MUX. Build and test the 4-bit MUX. Once you are satisfied that it is working correctly,

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imbed it in a subcircuit, label the subcircuit “MUX_4” (Figure 2-20), test the subcircuit, and add it to your
library.

MUX_4
A3
A2
A1
A0 Y3
Y2
B3 Y1
B2 Y0
B1
B0
A/B
4-Bit MUX

Figure 2-20. 4-bit, 2-to-1 MUX.

Demultiplexer/Decoder
The other piece of hardware our microprocessor will need to perform data routing is a demultiplexer, or a
demux. A demux, in some sense, performs the inverse operation of the MUX; it routes one input to one of
many outputs. A demux has one input line, 2n output lines and n control inputs. Each of the 2n different
settings of the control lines causes the input data to be routed to a different output line. The truth table and
subcircuit symbol for the 1-bit demux you will build is shown in Figure 2-21. This demux is called a 1-to-2
demux because it uses one control line to route the input to one of two outputs. (Using this notation, a
demux with 16 output lines would be called a 4-to-16 demux, because we need four control/select lines
with 24=16 unique settings to allow us to route the input to each of 16 output lines5.)

We could design each of the Y and Z output functions of the demux of Figure 2-21 using a 2-variable
Karnaugh map (using input variables D, Y/Z ). For large demultiplexers, the Karnaugh map approach
would work as well, but it becomes a bit unwieldy, for a 4-to-16 MUX, we would need to specify 16
outputs for each of the 32 input combinations – a total of 512 values. (There are 32 input combinations
because the device has a total of 5 input lines; four of these are control input lines, and one is a data input
line.)

D Y/Z Y Z
DEMUX_1 0 0 0 0
Y/Z Z 0 1 0 0
D Y 1 0 0 1
1 1 1 0

Figure 2-21. Truth table and symbol for 1-bit DEMUX.

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Let’s look at a simpler approach for designing the demultiplexer that relies on our understanding of
canonical forms. For a 1-to-2 demux, we want the Z output to be 1 ONLY when the input D is 1 and the
select line (call it A0 for the moment instead of Y/Z 6) is 0; hence the Z function is given by:

Z = D • A0 .

Similarly, we want the output Y to be 1 ONLY when both the input D and select input, A0, are 1; hence Y
is given by:

Y = D • A0 .

Task 6: Build and Test a 1-to-2 Demultiplexer Using AND-OR-NOT Gates

Build, and test the 1-bit, 1-to-2 demux using only AND-OR-NOT gates. (Save the circuit before you
imbed it in a subcircuit.) Imbed your circuit in a subcircuit labeled “DEMUX_1”, test the subcircuit, and
add it to your library.

Decoder Versus Demultiplexer

The device you built above we refer to as a demux. This device may also be called a decoder. What is the
difference? There is no difference in the construction of the device. What we call it, either a decoder or a
demultiplexer, depends on how we use it. When we use the device to route data, we call it a demultiplexer.
When the input bit (D) is thought of as a control signal (active high in our design), and when the output line
is being used as a control input to another device, we call the device a decoder. Because we think of the
decoder input data bit as an enabling signal (rather than a data bit), the notation we will use for a decoder is
different from that we use for a demux. Let’s repackage our demux as a decoder using a notation that is
traditional for a decoder.

Task 7: Repackage the 1-to-2 Demux as a 1-to-2 Decoder

Open the 1-to-2 demux circuit (not subcircuit) you created in Task 6. Imbed this circuit in a subcircuit
using the notation shown in Figure 2-22. Test the subcircuit and add it to your library. Note that when the
enable input to the decoder is inactive (i.e., 0), all outputs are inactive (i.e., 0), or disabled.

5
The notation we are using here is not unique. It is also common in the literature to find a demultiplexer with 16 output lines called a
1-of-16 demultiplexer.
6
We have changed the notation from Y/ Z to A0 to facilitate writing the output equations. The notation Y/ Z will be used in the
subcircuit symbol, as it is more meaningful when used in a schematic diagram.

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EN A0 Y1 Y0
DECODER 0 0 0 0
A0 Y0 0 1 0 0
EN Y1 1 0 0 1
1 1 1 0

Figure 2-22. Symbol and truth table for 1-bit decoder.

Building a 2-to-4 Decoder

The microprocessor you will build will need a larger decoder than that constructed above. Let’s start by
building a 2-to-4 decoder. A 2-to-4 decoder has the function definition table shown in Figure 2-23. The
postscript notation used in the decoder symbol and truth table is almost universal: the output line that
becomes active is labeled with the decimal equivalent of the applied binary address (with A1 being the
most significant bit). This means that if we apply the address (A1, A0) = 10B = 2D, the Y2 output line
should become active. To design this decoder, we will use the same approach as used for the 1-to-2
decoder (demux). We want the output line Y0 to be equal to the enable signal (EN) only when the applied
address is (A1, A0) = 00B; hence Y0 is given by,

Y0 = EN • A1 • A0 .

Similarly, we want Y1, Y2, and Y3 to be equal to EN only when the decimal equivalent of the applied
address is equal to the respective subscript, i.e.,

Y1 = EN • A1 • A0
Y2 = EN • A1 • A0
Y3 = EN • A1 • A0

A1 A0 Y0 Y1 Y2 Y3
DECODER
0 0 EN 0 0 0
A1 Y0
A0 Y1 0 1 0 EN 0 0
Y2
EN Y3 1 0 0 0 EN 0
1 1 0 0 0 EN

Figure 2-23. Function definition table and symbol for 1-bit 2-to-4 decoder.

Task 8: Build and Test a 2-to-4 Decoder Using AND-OR-NOT Gates

Build, and test the 1-bit, 2-to-4 demux using only AND-OR-NOT gates. Imbed your circuit in a subcircuit
labeled “DECODER_2”, test the subcircuit, and add it to your library.

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Building Larger Decoders

An alternate scheme for building the 2-to-4 decoder using primitive logic gates is to build the decoder using
the 1-to-2 decoders built in Task 7. Justify to yourself that the circuit of Figure 2-24 will function as a
2-to-4 decoder and that the notation used is consistent with the convention of having the subscript of the
activated output line be the decimal equivalent of the applied binary address. Also prove to yourself that
when the EN input line is inactive (i.e., 0), all output lines will be inactive.

DECODER

A0 Y0 Y0
EN Y1 Y1
DECODER
A1 A0 Y0
DECODER
EN EN Y1
A0 Y0 Y2
A0 EN Y1 Y3

Figure 2-24. Schematic for a 2-to-4 decoder constructed from 1-to-2 decoders / demultiplexers.

Task 9: Design, Build & Test a 4-to-16 Decoder Using 2-to-4 Decoders
Using the technique illustrated in Figure 2-24, design, build, and test a 4-to-16 decoder using only the 2-to-
4 decoder subcircuits you constructed in Task 8. Imbed your circuit in a subcircuit labeled “DECODER_4”
(see Figure 2-25 for the subcircuit symbol to use), test the subcircuit, and add it to your library.

DECODER_4
Y00
Y01
Y02
Y03
A3 Y04
A2 Y05
A1 Y06
A0 Y07
Y08
EN Y09
Y10
Y11
Y12
Y13
Y14
Y15
4 to 16 Decoder

Figure 2-25. Subcircuit symbol for a 4-to-16 decoder.

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3 SIMULATION LAB 3: ARITHMETIC AND LOGIC UNIT

Prerequisites: Before beginning this laboratory experiment you must be able to:
• Use LogicWorks™.
• Perform a 1’s complement operation on a multi-bit operand.
• Have completed Simulation Lab 1: Half Adder, Increment & Two's Complement Circuit.
• Have completed Simulation Lab 2: 4-Bit Full Adder, Multiplexer & Decoder.

Equipment: Personal computer and LogicWorks™.

Objectives: In this laboratory exercise you will learn how to construct an arithmetic and logic unit
(ALU) using subcircuits you built with LogicWorks™ in simulation labs 1 and 2.

Outcomes: When you have completed the tasks in this experiment you will be able to:
• Build, test, debug, and imbed in a subcircuit, an elementary arithmetic and logic unit (ALU).
• Describe the arithmetic and logical operations of which the ALU is capable.
• Describe the input control line values that correspond to each arithmetic and logical operation of
the ALU.
• Write a top-down description of a complex logic circuit.
• Calculate the approximate propagation delay time of a combinational-logic circuit.

Lab Report Guidelines

Before you begin this laboratory exercise, make sure you understand the reporting requirements your
instructor has specified. If you understand the reporting requirements then you will know the observations
that are important to record in your lab notebook and the tests that need to be performed on the circuits you
construct. For this lab, it is recommended that you use a top-down format when organizing your lab report.
(If your instructor is using the report writing guidelines contained in this manual, you can review them by
clicking on the blue text: Top Down Report Writing Guidelines.)

Introduction
In simulation labs 1 and 2 you built combinational logic circuits of increasing complexity. In this
laboratory exercise we will build upon these modules and combine them to form a more complex
combinational logic subcircuit: the arithmetic and logic unit (ALU). The ALU in a microprocessor is the

© 1999 Daniel J. Tylavsky

DIGITAL DESIGN
FOR THE LABORATORY SIMULATION LAB 3: ARITHMETIC AND LOGIC UNIT

unit that performs all of the arithmetic operations (such as add, subtract, negate, etc.) and all of the logical
operations (such as 1’s complement, AND, OR, etc.) Because this is an introductory class, we will limit
the number of operations our ALU will perform so that we can limit the complexity of the design.
Conceptually, however, the ALU we will design will be no different from the ALU in the personal
computer you use for performing these digital-logic simulations.

Our ALU, like all ALU’s, will be a combinational logic circuit that will have two data input ports, each of
which will accept a 4-bit binary number1 (plus a carry input). These strings are known as operands. Our
ALU will be capable of operating on either one operand (e.g., to perform a 1’s complement operation), or
two operands (e.g., to perform the sum, A+B) and will produce a 4-bit result (plus a possible carry). The
ALU will be controlled by a set of input control signals. These input control signals will determine which
operation the ALU will perform.

In this laboratory exercise you will construct the ALU. It will be left as an exercise at the end of this lab to
create a table that lists the operations the ALU performs for each set of input control signals. As you work
through this laboratory assignment, if you focus on how each subcircuit works, and how they interact, then
you will find constructing the table at the end much easier. You will find that many of the modules we
create will be capable of performing either logical or arithmetic operations. It may help you in organizing
your understanding if you divide the ALU operations into two types: logical and arithmetic.

Design of a NEG/NOT Circuit

The first module we build will be capable of performing two different operations on one operand. Which
operation we perform will be determined by the control signals we apply to the module. If we use one set
of control signals and apply an operand, say A, we'll get a 4-bit negative A out. If we use a different set of
control signals, our module will perform a bit-wise complement of A, giving the 1's complement of A; that
is, if A = 1001, our output will be 0110.

In Simulation Lab 1, you designed the two's complementing circuit shown in Figure 3-1. This circuit is
capable of only performing the 2's-complement operation; it has no control inputs that allow us change the
function that it performs. Starting with this circuit, you will modify it as shown in Figure 3-2.

1
We choose 4-bit (rather than 32-bit) operands because the 4-bit circuitry is much less tedious to construct and debug. This simplicity
will allow you to spend your time understanding the concepts we introduce rather than tediously building 32-bit versions of the
subcircuits we will need.

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INC_4
A3
A2 A3 Y3 Y3
A2 Y2 Y2
A1 A1 Y1 Y1
A0 Y0 Y0
A0 INC CRY CRY

+5V

Figure 3-1. Two's complement circuit.

A3

INC_4
A2 A3 Y3 Y3
A2 Y2 Y2
A1 Y1 Y1
A0 Y0 Y0
A1 INC CRY CRY

A0

Pass
NEG/NOT

Figure 3-2. NEG/NOT circuit.

The modifications shown in Figure 3-2 allow this circuit to do three things: it can perform the 2's-
complement operation (i.e., negate arithmetically), perform the 1's complement (i.e., logically complement
each bit, also known as performing the NOT of each bit) or allow the input argument to pass-through

unscathed. In Figure 3-2, two control signals have been added to effect these controls: the Pass and the

NEG/NOT . The notation chosen for these signals communicates two things: which operation the signal
controls, and whether the signal is high or low when active. The over-bar notation means that the signal is
low (0) when active. If the over-bar is not present, the signal is high when active. (If you understand the
notation we are using, in many cases you will be able to determine the functions being performed by each

circuit simply by inspecting the notation.) The Pass and NEG/NOT signals act in the following way:

• The Pass control when active (low) allows the input signal to pass through unscathed. When

the Pass signal is inactive, the device is controlled by the NEG/NOT signal.

• When the NEG/NOT signal is low the A operand (we'll use A to represent the 4-bits A3-A0) is

negated (arithmetically). When the NEG/NOT signal is high, the circuit of Figure 3-2 performs
the one's complement (logical operation) on the A operand.

Let's look at how each of these control signals controls the circuit of Figure 3-2.

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• Pass = 0. Pass-Through Operation

With Pass = 0, the output of the AND gate in Figure 3-2 must be 0, preventing the INC_4

subcircuit from incrementing the incoming signal. The Pass = 0 is also fed into each XOR
gate. Recall from the definition of the XOR gate that 0⊕A=A; hence the A input is passed

through the XOR gates unscathed and then through the incrementer unscathed. Thus with Pass

= 0, the A operand is passed through the NEG/NOT circuit as indicated in Figure 3-3.

• Pass = 1, NEG/NOT = 0. Arithmetic Negate Operation

With Pass = 1 and NEG/NOT = 0, both inputs to the AND gate are 1's; hence the output of

the AND gate is high, causing the INC_4 circuit to increment the incoming signal. The Pass =
1 signal is supplied as one input to each of the XOR gates. Recall from the definition of the

XOR gate that 1 ⊕ A = A ; that is, when one input to an XOR gate is a 1, the XOR acts on the
other input as an inverter would; hence the input to the INC_4 circuit is the bit-wise

complement of A, (or A ). Incrementing A by 1 is the definition of the two's-complement

operation. Thus this control scheme arithmetically negates the A operand as indicated in Figure
3-3.

• Pass = 1, NEG/NOT = 1. One's Complement Operation

Under this control scheme the lower input to the AND gate is zero. This causes the output of
the AND gate to be low. This in turn causes the INC_4 circuit to pass through the incoming 4-

bit operand signal unscathed. The incoming 4-bit operand is A (see argument above); hence
the output of the INC_4 circuit is the bit-wise complement, or one's complement of A as
indicated in Figure 3-3.

Task 1: Build the NEG/NOT Circuit

Build the circuit shown in Figure 3-2, imbed it in a subcircuit using the notation of Figure 3-3, test it, and
add it to your library.

NEG/NOT Pass NEG/NOT FUNCTION

A3 Y3
A2 Y2 0 0 PASS-THROUGH
A1 Y1
A0 Y0 0 1 PASS-THROUGH
Pass CRY 1 0 TWO'S COMPLEMENT
NEG/NOT 1 1 ONE'S COMPLEMENT

Figure 3-3. NEG/NOT function definition table and subcircuit symbol.

Each of the circuits we design in this lab will play a key role in your microprocessor so it is important that
you select your tests so that you are sure each of these circuits work correctly. Briefly mention in your lab

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report how you chose to test this circuit. It is not necessary to describe in your report all of the input and
output values you tested; instead include a function table similar to the table shown in Figure 3-3.

Design of an ADD/OR Circuit

The NEG/NOT circuit is an extremely simple version of an ALU, so simple that no one would call it an
ALU. Yet, it will do either an arithmetic operation, the NEGATE, or a logical operation, the NOT of 4
bits. It will also pass-through data without operating on it. Typically, an ALU is a circuit that performs
many different functions on its inputs, more functions than just the three given above. In particular, we
would like to be able to do an ADD and an OR of two 4-bit numbers – and we would like to retain the pass-
through capability. In your previous laboratory exercises, you have constructed all of the subcircuits we
will need to build this circuit. Let's build this circuit in two stages, first let's build the ADD/OR circuit,
then let's modify the circuit to gain the pass-through capability.

B3

A3

B2
OR3
A2
OR2
OR1
B1
OR0
A1 MUX_4
OR3
OR2 A3
B0
OR1 A2
OR0 A1
A0 A0 Y3 Y3
AD3 Y2 Y2
AD2 B3 Y1 Y1
FA_4 B2 Y0 Y0
A3 A3 AD1
A3 A2 A2 A3 AD0 B1
A2 A1 A1 A2 B0
A1 A0 A0 A1 AD3
A0 A0 Y3 AD2 A/B
B3 B3 Y2 AD1
B3 B2 B2 B3 Y1 AD0
B2 B1 B1 B2 Y0
B1 B0 B0 B1
B0 B0 Cout Cout
Cin Cin
ADD/OR

Figure 3-4. ADD/OR circuit.

Figure 3-4 shows the schematic of the ADD/OR circuit. (This figure uses the LogicWorks™ bus concept
and notation2. If you are not familiar with this notation look over the section titled Breakouts and Bus
Lines in Simulator Tutorial: Using LogicWorks™ 4 for Windows® or Macintosh®.) This circuit accepts
two 4-bit operands, A and B, as input. These operands are fed to the 4-bit full-adder subcircuit (FA_4
found in your library) and to four 2-input OR gates. The 4-bit output of the OR gates and adder is fed into
a 2-to-1 4-bit mux (MUX_4 found in your library). This mux is used to select which result (ADD or OR) is
routed to the output. (This is a typical example of how multiplexers are used in digital systems.) To
control which result is routed to the output, the mux selector input is controlled by the ADD /OR control.

2
Use of a bus simplifies the construction and presentation of the circuit schematic by eliminating the need to provide a unique route
for each signal line.

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The selector signal notation is consistent with the notation described earlier: when the ADD /OR signal is
low, the (arithmetic) addition result is routed to the output. When the ADD /OR signal is high, the
(logical) OR result is routed to the output.

To add the data pass though capability to the circuit of Figure 3-4, we add a 4-bit 2-to-1 mux as the output
stage as shown in Figure 3-5. One input to the output-stage mux is the ADD/OR-circuit-output signal, the

other is the A operand. The selector input of the output stage mux is controlled by the Pass signal. When

Pass = 0, the A operand appears at the output unscathed. When Pass = 1, the output function, either

ADD or OR, depends on the value of the ADD /OR signal as shown in the table of Figure 3-6.

B3

A3

B2
OR3
A2
OR2
OR1
B1
OR0
A1 MUX_4
OR3
OR2 A3
B0
OR1
A2
A1 MUX_4
OR0
A0 A0 Y3 A3
AD3 Y2 A2
AD2
B3 Y1 A1
FA_4 B2 Y0 A0 Y3 Y3
A3 A3 AD1
A3 A2 A2
A3 AD0
B1 A3
Y2 Y2
A2 A1 A1 A2 B0 A2 B3 Y1 Y1
A1 A0 A0
A1 AD3 A1
B2 Y0 Y0
A0 A0 Y3 AD2 A/B A0 B1
B3 B3 Y2 AD1 B0
B3 B2 B2 B3 Y1 AD0
B2 B1 B1 B2 Y0 A/B
B1 B0 B0
B1
B0 B0 Cout Cout
Cin Cin
ADD/OR
Pass

Figure 3-5. ADD/OR circuit with pass-through.

ADD/OR
A3
A2
A1
A0 Y3 Pass ADD/OR FUNCTION
Y2
B3 Y1 0 0 Pass Through
B2 Y0
B1 0 1 Pass Through
B0
1 0 ADD
ADD/OR
1 1 OR
Pass
Cin Cout

Figure 3-6. ADD/OR function table and symbol.

Task 2: Build and Test the ADD/OR Circuit

Using the subcircuits contained in your library, build the ADD/OR circuit with pass-through shown in
Figure 3-5. Create a subcircuit for this circuit using the symbol in Figure 3-6. Test the subcircuit and add
it to your library. Briefly mention the procedure you used to test it. Justify why the results of the tests you
chose make it likely that your circuit functions correctly.

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Design of an ALU
The last stage in building the ALU is to combine the NEG/NOT and the ADD/OR subcircuits as shown in
Figure 3-7 to create the complete ALU. This ALU contains three input control signals:

• The Invert signal, when active indicates that some type of inversion, either a one's or two's
complement is taking place.

• The A Only signal, when active, indicates that only the A operand is being acted upon by the
ALU.

• The Arith/Logic signal operates so that when it is low, an arithmetic operation is performed.

When Arith/Logic = 1, a logical operation is performed by the ALU.

Once this notation is understood, you may be able to fill out the function definition table for this circuit
even without reference to Figure 3-7. Consider the example filled-in in Table 1:

• A Only = 1 implies that the A and B operands are combined in some fashion.

• Invert = 1 implies neither A nor B are inverted (neither a one's nor a two's complement is
performed.)

• Arith/Logic = 0 implies the operation is arithmetic.

The only two-operand, noninverting arithmetic operation of which our ALU is capable is the sum, A + B.

NEG/NOT ADD/OR
A3 A3 Y3 A3
A2 A2 Y2 A2
A1 A1 Y1 A1
A0 A0 Y0 A0 Y3 Y3
Y2 Y2
Invert Pass CRY B3 B3 Y1 Y1
B2 B2 Y0 Y0
NEG/NOT B1 B1
B0 B0
Arith/Logic ADD/OR
A Only Pass
Cin Cin Cout Cout

ALU
A3
A2
A1 Y3
A0 Y2
Y1
B3 Y0
B2
B1
B0
Cin Cout
Arith/Logic
Invert
A Only

Figure 3-7. The complete ALU.

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Task 3: Build and Test the ALU Circuit

Build the complete ALU circuit shown in Figure 3-7. Complete the ALU function definition table, Table 1
and include it in your report. Test the ALU and then imbed the ALU in a subcircuit using the notation
shown in Figure 3-7. Test the subcircuit then save the subcircuit in your library. Describe in your report
briefly how you tested the circuit. The ALU you have saved in your library is the one around which we
will construct a microprocessor.

Table 1. ALU Function Definition Table.

A Only = 0
Arith / Logic Invert Function
0 0
0 1
1 0
1 1

A Only = 1
Arith / Logic Invert Function
0 0
0 1 Arithmetic Sum, A+B
1 0
1 1

The ALU Design Methodology

The design methodology we have used to construct the ALU has followed the same pattern we established
early on in these laboratory exercises: create subcircuits of complex circuits, then use these subcircuits to
create more complex subcircuits, and so on to ever greater levels of complexity. This made designing the
ALU easy. Imagine how difficult it would be to design an ALU using only the symbols for AND gates and
OR gates and to manage the resulting schematic diagram!

In spite of the complexity of laying out large complex circuits at the gate level, many ALU's (or at least
parts thereof) are designed just that way today. Rather than use a hierarchical design approach, a truth table
is constructed of the complex function to be implemented and sophisticated software programs, using
techniques like Karnaugh methods, find the optimum design. (Optimization must balance many competing
criteria. Speed, as measured by propagation delay time, is one of these.) Whether or not hierarchical
techniques are used in designing a component depends on a number of factors including the type of
component to be designed, the need for optimization, and the availability of the necessary software to
manage the optimization. In this laboratory manual, we will continue to use hierarchical design techniques
because they are easier to use. Also, the resultant designs are easier maintain and easier to understand by

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ourselves and by others who may work with them. When we come to a component that may benefit from
using more sophisticated design techniques, we'll point that out.

Task 4: Propagation Delay Time of the ALU

Let's take a short break from microprocessor design and look at a practical problem: propagation delay
times. Though we will not consider propagation delay times in our design, they are very important in a real
world design. For our ALU, identify the longest path between any input and any output. By longest path,
we mean the largest number of gates that a signal would traverse when traveling from any input to any
output. Assuming a propagation delay of 3 nanoseconds for each AND, OR, NAND, NOR, and XOR find
the maximum propagation delay time between any input signal and any output response of the ALU.
Neglect the delays of all inverter gates. You may assume that all signals are applied to all input signals
simultaneously. Be sure to include the longest propagation delay time, and a description of the longest path
in your report.

Report Writing
Check with your instructor about the reporting requirements for this lab. If you are using the reporting
guidelines in this manual, use the Top-Down Report Writing Guidelines for writing your report.

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