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Sheet 2

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18 views3 pages

Sheet 2

Uploaded by

mohamedhesham.sky
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Sheet 2

1) Demonstrate by means of truth tables the validity of the following:


a) (XYZ)' = X'+Y'+Z' b) X+YZ = (X+Y)(X+Z) c)XY+X'Z+YZ = XY+X'Z

2) Simplify the following Boolean expressions to minimum number of


literals:
a)X'Y'+XY+X'Y' b)X'Y+XY'+X'Y'

c)WXZ'+WX'YZ+XZ d)ABC'D'+A'BC'+ABD+A'BCD+BCD'

e)(BC'+A'D)(AB'+CD') f)(X'Y'+Z)'+Z+XY+WZ

g)A'B(D'+C'D)+B(A+A'CD)

3) Find the complement of the following expressions:


a)XY'+X'Y b)(AB'+C)D'+E

c) AB(C'D+CD')+A'B'(C'+D)(C+D')

4) Implement the following functions using:


a) OR gates and complements only. b) AND gates and complements only.

i) F=X'Y'+X'Z+Y'Z ii)F=(Y+Z')(X+Y)(Y'+Z)

5) Obtain the truth table of the following functions and express each
function in sum of min terms and product of max terms:
a)F=AB+B'C'+C'D+D'A b)F=(A'+B)(B'+C)

6) For the Boolean functions E and F, as given in the following T.T:


a) List the minterms and maxterms of each function.

b) List the minterms and maxterms of E' and F'.

c) List the minterms and maxterms (E+F) and (E.F).

d) Express E and F in SOP and POS.

e) Simplify E and F to min. number of literals.


X Y Z E F
0 0 0 1 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 1 1
1 1 1 0 0

7) Convert the following functions to SOP and POS:


a)F(A,B,C,D) = (AB+C)(B+C'D) b)G(X,Y,Z) = X'+X(X+Y')(Y+Z')

8) Given the following Boolean function:


a) Obtain the T.T of the function.

b) Implement the function using the basic logic gates.

c) Simplify the function and implement it after simplification.

9) Draw the logic circuit that realize the statement "Electrical


engineering students" shall take as an elective course either Boolean
Algebra or "Computer Programming".

10) An integrated circuit logic family has AND gates with fan-out of 5 and
buffer gates with fan-out of 10.show how the output signal of a single
AND gate can be applied to 50 other AND gate inputs without over
loading the output gate.

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