Digital Logic Design

Combinational Logic
Part 4
Objectives
•Other Gate Types
• NAND
• NOR
•More Gates Types
• XOR
• XNOR
 More Gates: NAND - NOR
X Y Z=(XY)’
0 0 1
X
NAND Z F = (XY)’ 0 1 1
Y 1 0 1
1 1 0

X Y Z=(X+Y)’
X 0 0 1
NOR Z F = (X+Y)’
Y 0 1 0
1 0 0
1 1 0

Sometimes it is desirable to build circuits using NAND gates only or NOR gates
only
 NAND Gate is Universal
NOT X X’ X
X’
X

X X XY
AND XY
Y Y

X X (X’.Y’)’ = X+Y
OR X+Y
Y Y

•Therefore, we can build all functions we learned so far using NAND gates
ONLY (Exercise: Prove that NOT can be built with NAND)
•NAND is a UNIVERSAL gate
 Graphic Symbols for NAND Gate
Two equivalent graphic X
symbols or shapes for the AND-NOT Y (XYZ)’
SAME function Z

X
NOT-OR X’+Y’+Z’ = (XYZ)’
Y
Z

AND-NOT = NOT-OR
 Implementation using NANDs
Example: Consider F = AB + CD
NAND
A A
B B
F F
C C
D D

Proof:
NAND
F = ((AB)’.(CD)’)’
= ((AB)’)’ + ((CD)’)’
= AB + CD A
B F

C
D
 Implementation using NANDs
Consider F =Σm(1,2,3,4,5,7) – Implement using NAND
gates X
Y’
Y=1 F
YZ X’
X 00 01 11 10 Y

0 1 1 1 Z
X=1 1 1 1 1
X
Z=1 Y’
F
X’
F(X,Y) = Z+XY’+X’Y Y

Z’
 Rules for 2-Level NAND
Implementations
1. Simplify the function and express it in sum-of-products
form(SOP)
2. Draw a NAND gate for each product term (with 2 literals or
more)
3. Draw a single NAND gate at the 2nd level (in place of the OR
gate)
4. A term with single literal requires a NOT

What about multi-level circuits?

 Multilevel NAND Circuits
Boolean function implementation
◦ AND-OR logic → NAND-NAND logic
◦ AND → AND + inverter=NAND
◦ OR → inverter + OR = NAND
◦ For every circle that is not compensated by another small circle along the same line, insert an inverter.

Figure 3.22 Implementing F = A(CD + B) + BC

NAND Implementation

Figure 3.23 Implementing F = (AB +AB)(C+ D)

NOR Gate is Universal
X X’ X X’
NOT
X

X X (X’+Y’)’ = XY
AND XY
Y Y

X X (X+Y)’’ = X+Y
OR X+Y
Y Y

•Therefore, we can build all functions we learned so far using NOR gates ONLY
(Exercise: Prove that NOT can be built with NOR)
•NOR is a UNIVERSAL gate
 Graphic Symbols for NOR Gate
Two equivalent graphic
symbols or shapes for the
X (X+Y+Z)’
SAME function
Y
OR-NOT
Z

X (X’Y’Z’)=(X+Y+Z)’
NOT-AND Y
Z

OR-NOT = NOT-AND
Implementation using NOR gates
Consider F = (A+B)(C+D)E
NOR

NOR
A A
B B
F F
C C
D D

E E’
 Rules for 2-Level NOR
Implementations
1. Simplify the function and express it in product of sums
form (POS)
2. Draw a NOR gate (using OR-NOT symbol) for each sum term
(with 2 literals or more)
3. Draw a single NOR gate (using NOT-AND symbol) the 2nd
level (in place of the AND gate)
4. A term with single literal requires a NOT

What about multi-level circuits?

 Implementation using NOR gates
Consider F =Σm(1,2,3,5,7) – Implement using NOR gates
X’
Y=1 Z F
YZ
Y
X 00 01 11 10
Z
0 1 1 1
X=1 1 1 1
X’
Z=1 Z F
Y
F’(X,Y) = Y’Z’+XZ’, or
Z
F(X,Y) = (Y+Z)(X’+Z)
3-8 Other Two-level Implementations
Wired logic
◦ A wire connection between the outputs of two gates
◦ Open-collector TTL NAND gates: wired-AND logic
◦ The NOR output of ECL gates: wired-OR logic

F = ( AB )  (CD ) = ( AB + CD ) = ( A + B)(C  + D) AND-OR-INVERT function

F = ( A + B ) + (C + D ) = [( A + B)(C + D)] OR-AND-INVERT function

Figure 3.28 Wired Logic

 Non-degenerate Forms
16 possible combinations of two-level forms
◦ Eight of them: degenerate forms = a single operation
◦ AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-NOR, NOR-AND, NOR-NAND.
◦ The eight non-degenerate forms
◦ AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-NAND, AND-NOR.
◦ AND-OR and NAND-NAND = sum of products.
◦ OR-AND and NOR-NOR = product of sums.
◦ NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?
 AND-OR-Invert Implementation
AND-OR-INVERT (AOI) Implementation
◦ NAND-AND = AND-NOR = AOI
◦ F = (AB+CD+E)'
◦ F' = AB+CD+E (sum of products)

Figure 3.29 AND-OR-INVERT circuits, F = (AB +CD +E)

 OR-AND-Invert Implementation
OR-AND-INVERT (OAI) Implementation
◦ OR-NAND = NOR-OR = OAI
◦ F = ((A+B)(C+D)E)'
◦ F' = (A+B)(C+D)E (product of sums)

Figure 3.30 OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'

 Tabular Summary and Examples
Example 3-11: F = x'y'z'+xyz'
◦ F' = x'y+xy'+z (F': sum of products)
◦ F = (x'y+xy'+z)' (F: AOI implementation)
◦ F = x'y'z' + xyz' (F: sum of products)
◦ F' = (x+y+z)(x'+y'+z) (F': product of sums)
◦ F = ((x+y+z)(x'+y'+z))' (F: OAI)
Tabular Summary and Examples
Figure 3.31 Other Two-level Implementations
 More Gates: XOR - XNOR
X Y Z=XY
Exclusive OR X F = X’Y + XY’ 0 0 0
Z
(XOR) Y =XY
0 1 1
1 0 1
1 1 0

Exclusive NOR X F = XY + X’Y’ X Y Z=(XY)’

Z
(XNOR) Y = (X  Y)’ 0 0 1
=XY 0 1 0
=X Y
1 0 0
1 1 1

Different symbols for XNOR

 3-9 Exclusive-OR Function
Exclusive-OR (XOR)
◦ xy = xy'+x'y

Exclusive-NOR (XNOR)
◦ (xy)' = xy + x'y'

Some identities
◦ x0 = x
◦ x1 = x'
◦ xx = 0
◦ xx' = 1
◦ xy' = (xy)'
◦ x'y = (xy)'

Commutative and associative

◦ AB = BA
◦ (AB) C = A (BC) = ABC
 Exclusive-OR Implementations
Implementations
◦ (x'+y')x + (x'+y')y = xy'+x'y = xy

Figure 3.32 Exclusive-OR Implementations

Odd Function
◦ ABC = (AB'+A'B)C' +(AB+A'B')C = AB'C'+A'BC'+ABC+A'B'C = S(1, 2, 4, 7)
◦ XOR is a odd function → an odd number of 1's, then F = 1.
◦ XNOR is a even function → an even number of 1's, then F = 1.

Figure 3.33 Map for a Three-variable Exclusive-OR Function

 XOR and XNOR
Logic diagram of odd and even functions

Figure 3.34 Logic Diagram of Odd and Even Functions

 Four-variable Exclusive-OR function
Four-variable Exclusive-OR function
◦ ABCD = (AB'+A'B)(CD'+C'D) = (AB'+A'B)(CD+C'D')+(AB+A'B')(CD'+C'D)

Figure 3.35 Map for a Four-variable Exclusive-OR Function

 Parity Generation and Checking
Parity Generation and Checking
◦ A parity bit: P = xyz
◦ Parity check: C = xyzP
◦ C=1: one bit error or an odd number of data bit error
◦ C=0: correct or an even # of data bit error

Figure 3.36 Logic Diagram of a Parity Generator and Checker

Parity Generation and Checking
Parity Generation and Checking
 3.10 Hardware Description Language (HDL)
A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form.
It resembles an ordinary computer programming language, such as C, but is
specifically oriented to describing hardware structures and the behavior of
logic circuits.
It can be used to represent logic diagrams, truth tables, Boolean
expressions, and complex abstractions of the behavior of a digital system.
In the public domain, there are two standard HDLs that are supported by
the IEEE: VHDL and Verilog.
A Top-Down Design Flow
Specification

RTL design and

Simulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

Design entry creates an HDL-based description of the functionality that is to be implemented in
hardware. Depending on the HDL, the description can be in a variety of forms: Boolean logic
equations, truth tables, a netlist of interconnected gates, or an abstract behavioral model
Logic simulation displays the behavior of a digital system through the use of a computer. A
simulator interprets the HDL description and either produces readable output, such as a time-
ordered sequence of input and output signal values, or displays waveforms of the signals. The
simulation of a circuit predicts how the hardware will behave before it is actually fabricated.
Simulation detects functional errors in a design without having to physically create and operate
the circuit. Errors that are detected during a simulation can be corrected by modifying the
appropriate HDL statements
Logic synthesis is the process of deriving a list of physical components and their
interconnections (called a netlist ) from the model of a digital system described in an
HDL. The netlist can be used to fabricate an integrated circuit or to lay out a printed
circuit board with the hardware counterparts of the gates in the list

Timing verification confirms that the fabricated, integrated circuit will operate at a
specified speed. Because each logic gate in a circuit has a propagation delay, a
signal transition at the input of a circuit cannot immediately cause a change in the
logic value of the output of a circuit. Propagation delays ultimately limit the speed at
which a circuit can operate. Timing verification checks each signal path to verify that
it is not compromised by propagation delay
 Module Declaration
Examples of keywords:
module, end-module, input, output, wire, and, or, and not

Figure 3.37 Circuit to demonstrate an HDL

The term module refers to the text enclosed by the keyword pair module . . .
endmodule. A module is the fundamental descriptive unit in the Verilog language. It
is declared by the keyword module and must always be terminated by the keyword
endmodule
The keyword module is followed by a name and a list of ports. The name (
Simple_Circuit in this example) is an identifier. Identifiers are names given to
modules, variables (e.g., a signal), and other elements of the language so that they
can be referenced in the design
The port list of a module is the interface between the module and its environment.
In this example, the ports are the inputs and outputs of the circuit.
Next, the keywords input and output specify which of the ports are inputs and
which are outputs. Internal connections are declared as wires
The circuit in this example has one internal connection, at terminal w1 , and is
declared with the keyword wire.
Each gate instantiation consists of an optional name (such as G1, G2 , etc.)
followed by the gate output and inputs separated by commas and enclosed within
parentheses. The output of a primitive gate is always listed first, followed by the
inputs.
 HDL Example 3.1
HDL description for circuit shown in Fig. 3.37
 Gate Delays
All physical circuits exhibit a propagation delay between the transition of an input and a resulting
transition of an output. When an HDL model of a circuit is simulated, it is sometimes necessary to
specify the amount of delay from the input to the output of its gates. In Verilog, the propagation
delay of a gate is specified in terms of time units and by the symbol #.

Example: timescale directive The first number specifies the unit of measurement for
◦ ‘timescale 1 ns/100ps time delays. The second number specifies the precision
for which the delays are rounded off, in this case to 0.1
ns. If no timescale is specified, a simulator may display
dimensionless values or default to a certain time unit,
usually 1 ns (=10-9 s) 1ps=10-12
HDL Example 3.2Gate-level description with propagation delays for
circuit shown in Fig. 3.37
 HDL Example 3.3
In order to simulate a circuit with an HDL, it is necessary to apply inputs to the circuit
so that the simulator will generate an output response. An HDL description that
provides the stimulus to a design is called a test bench
In its simplest form, a test bench is a module containing a signal generator
Test bench for simulating the circuit with delay
Within the test
bench, the inputs
to the circuit are
declared with
keyword reg and
the outputs are
declared with the
keyword wire .
The module
Simple_Circuit_
prop_delay is
instantiated with
the instance
name M1.
Simulation output for HDL
Example 3.3
 Boolean Expression
Boolean expression for the circuit of Fig. 3.37
Boolean equations describing combinational logic are specified in Verilog with a continuous
assignment statement consisting of the keyword assign followed by a Boolean expression.

Verilog uses the symbols (&), (|), and (~) for AND, OR, and NOT
(complement),respectively.
Boolean expression:

HDL Example 3.4

HDL Example 3.4
 User-Defined Primitives
General rules:

Declaration:

Implementing the hardware in Fig. 3.39

HDL Example 3.5
HDL Example 3.5 Continued)