Examples Blocking Assignments

module BlockingAssignmentExample2;
reg [7:0] a, b, c, d, e; Output
initial begin
a = 8'hDA;
$display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); [0] a=0xda b=0xx c=0xx
#10 b = 8'hF1;
$display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); [5] d=0xaa e=0xx
c = 8'h30;
$display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c); [10] a=0xda b=0xf1 c=0xx
end
[10] a=0xda b=0xf1 c=0x30
initial begin
#5 d = 8'hAA; [10] d=0xaa e=0x55
$display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
#5 e = 8'h55;
$display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
end
endmodule

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 Procedural Assignments

Procedural assignments take place in the initial and always

constructs. These are regarded as procedural bodies.
Primarily, assignments to reg data types takes place in procedural
bodies.
Several procedural flow control statements are available
Delay control
Event control
Within a module there can be several procedural bodies
Execution of these bodies begins concurrently at the start of
simulation

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 Procedural Flow
An event or delay control statement causes program flow to be put on hold
temporarily.
Flow of the simulation continues after the event occurs or delay expires.

always always always

… … …
… … …
@(reset) if (clear) #10
… … …
… … …
end end end
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 Procedural Constructs
 The primary mechanism for modeling the behavior of a design are the
following two statements:
 Initial statement
 Always statement
 A module can contain any number of initial or always statements.
 All of them execute concurrently w.r.t. each other
 Initial Statement
 An initial statement executes only once, which is at start of simulation or
t=0
 Syntax is initial [timing_control] procedural_statement(s)
 Procedural statements can be assignment, conditional, case, loop, wait,
disable, …
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 Initial Statement
 Example of an initial statement:
parameter SIZE = 1024;
reg [7:0] vld_ram[0:SIZE‐1];
reg speed_reg;

initial
begin: seq_blk_a # procedural blocks can be assigned labels
integer index;
speed_reg = 0;

for (index = 0; index < SIZE; index = index+1)

vld_ram[index] = 0;
end

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 Always Statement
 Unlike initial statement, the always statement executes repeatedly
 Similar to the initial statement, the always statement also begins
execution at time t=0
 Syntax of the always statement is:
always [timing_control] procedural_statements
 Example
always
#5 myclk = ~myclk; # clk waveform with a period of 10

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 Example of Always Statement
module d_flipflop(clk, d, set, q, qbar)
input clk, d, set;
output reg q, qbar;

always
wait (set == 1)
begin
#3 q <= 1; # will discuss <= when we get to
#2 qbar <= 0; # non‐blocking assignment
wait (set == 0);
end
…
…

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 Initial and Always Statement
 A module can contain multiple initial and multiple always blocks
 Each block starts a separate control flow
 Each block starts execution at time t=0

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 Non Blocking Assignments
Non‐blocking assignment statements are allowed to be scheduled
without blocking the execution of the succeeding statements.
Non‐blocking assignments are specified by a <= symbol
Overloading: Same symbol is used as a relational operator in
expressions
In the next few slides, we will look at the same example as previous
but with non‐blocking assignment

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 Examples Non‐Blocking Assignments
module NonBlockingAssignmentExample3; Delays
reg x, y, z; • Statements x = 0 through
reg [15:0] reg_a, reg_b; reg_b = reg_a are executed
integer count; sequentially at time 0
• reg_a[2] = 0 is scheduled to
initial begin execute at t=15
x = 0; y = 1; z = 1; // scalar assignments • reg_b[15:13] = {x, y,, z} is
count = 0 scheduled to execute at t = 10
reg_a = 16`b0; reg_b = reg_a; //Initialize vectors • Increment of count is
reg_a[2] <= #15 1`b1 //Assignment with delay scheduled at t = 0 .
reg_b[15:13] <= 10 {x, y, z}; //Concatenate and assign
count <= count + 1;
end
endmodule

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 Explanation for Non‐Blocking Assignment
All the statements start at t = 0, because the first statement does not
block the execution of the second statement and so on.
 Delays associated with each statement are honored for that
statement only.
The RHS of every non‐blocking statement of a particular time‐step is
captured and moves onto the next statement
The captured RHS value is assigned to the LHS variable only at the
end of the time‐step.
 If $display executes before the LHS is assigned the value, it will
display the previous value.

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 Another Example of Non Blocking
always @(posedge clock) begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; // What value will this get?
end

Explanation
• A read operation is performed on each RHS variable in1, in2, in3, and reg1 at the posedge of clock
• All the RHS expressions are evaluated, and stored internally.
• Write operations to the LHS are scheduled to be executed at the time specified by the intra‐assign
statement, ie. write to reg1 after 1 time unit, to reg2 at the next negative edge of clock, and to reg3
after 1 time unit
• The order in which the write operations are performed is irrelevant as the values are already stored

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 Blocking and Non‐Blocking Example
always @(posedge clock) begin always @(posedge clock) begin
r_test_1 <= 1`b1; r_test_1 = 1`b1;
r_test_2 <= r_test_1; r_test_2 = r_test_1;
r_test_3 <= r_test_2; r_test_3 = r_test_2;
end end

Explanation
• In the first case, it will take 3 clock cycles for the value of 1 to propagate to r_test_3.
• In the second case the value of 1 will propagate to r_test_3 in the first clock cycle itself

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking
assignments. If you want to create combinational logic use an always block with Blocking
assignments. Try not to mix the two in the same always block.

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 Application of NonBlocking Assignments
Non blocking assignment statements are used as a method to model several concurrent data
transfers that may take place after a common event.
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3
reg3 <= #1 reg1;
end
Three concurrent data transfers take place at the positive edge of clock
1. A read operation is performed on each RHS variable in1, in2, in3, and reg1 at the posedge
of clock. RHS expressions are evaluated and results stored in memory
2. The write operations to the LHS variables are scheduled to be executed at the time
specified by the delay in each assignment.
3. The write operations are executed at the scheduled time steps.
Swap two variables using blocking and non‐blocking assignments
Show problems on Palanitkar page 170‐171 for another example

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 Conditional Statements
Conditional statements are used for making decisions based on certain conditions
The conditions decide whether a particular statement should be executed or not
There are three types of conditional statements:
 First type checks for condition before executing a statement (if)
 Second type checks for condition and also what to execute if condition is not met. (if‐else)
 Third is multiple conditions. (if‐else‐if)

if (expression) if (expression) if (expression1)

true_statement; true_statement; true_statement1;
else else if (expression2)
false_statement; true_statement2;
else
default_statemen;

The expression is evaluated to be true or false (1 or 0)

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 Multiway Branching
In type3 conditional statement, there were many alternatives out of which one is chosen
When there are too many alternatives, the nested if‐else‐if can become tedious
Better way to handle such situations is through the case statement. The keywords case, endcase,
and default are used.
case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
….
….
default: default_statement;
endcase
A block of multiple statements must be grouped by the keywords begin and end.
casex: Treats all x & z values as don’t cares
casez: Treats all z values as don’t cares

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 4‐to‐1 Multiplexer with case statement
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0})
2`d0: out = i0;
2`d1: out = i1;
2`d2: out = i2;
2`d3: out = i3;
default: $display(“Invalid”);
endcase
endmodule

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 Loops
There are four different types of looping statements in Verilog: while, for, repeat,
and forever
The syntax for these in Verilog is very similar to C programming language
All looping statements can appear only inside an initial or always block.
Loops can also contain delay expressions

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 Sequential Blocks
Block statements are used to group multiple statements together to work
together as one.
Sequential blocks use begin and end as the keywords to define a block
A statement in a sequential block executed only after its preceding statement
completes execution (except for non‐blocking assignments with intra‐assignment
timing control)
If delay or event control is specified, it is relative to the simulation time when the
previous statement in the block completes execution.
Almost all the examples we have seen in class so far fall into this category
Explain the example from Palnitkar’s book on page 189

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 Parallel Blocks
Parallel blocks are specified by the keywords fork and join
Statements in a parallel block are executed concurrently
Ordering of the statements is controlled by the delay or event control assigned to
each statement
If delay or event control is specified, it is relative to the time the block was
entered
Since all statements in the block are executed concurrently, the order in which
the statements are written is not important
One must be cautious of creating implicit race conditions in a parallel block
Explain the two examples on pages 190‐191 from Palnitkar’s book

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 Nested Blocks
Blocks can be nested
Sequential and parallel blocks can be mixed in the same module
initial
begin
x = 1`b0;
fork
#5 y = 1`b1;
#10 z = {x, y};
join
#20 w = {y, x};
end
Parallel block of code inside the sequential block of code

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 Named Blocks
Blocks can be given names
Local variables can be declared for the named blocks
Named blocks are part of the design hierarchy. Variables inside a named block
can be accessed by using hierarchical name referencing
Named blocks can be disabled meaning their execution can be stopped
Example on page 192 Palnitkar’s book

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 Disabling Named Blocks
 The keyword disable terminates the execution of a named block
 The keyword disable can be used to get out of loops, handle error conditions, or control execution ‐ very
similar to break statement in C
 Key difference is that disable can stop execution of any named block in the design
 Disabling a named block passes execution to the immediate next statement after the block

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October 10

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 Generate Blocks
 Generate statements allow Verilog code to be generated dynamically at
elaboration time before the simulation begins.
 Elaboration time is the phase before simulation starts, when all design modules are linked
and hierarchical references are resolved
 Facilitates creation of parameterized models.
 Generate statements are particularly convenient for repeated operations or
module instances for multiple bits of a vector.
 Also useful when some Verilog code is conditionally included based on
parameter definitions.
 Generate statements allow control over the declaration of variables, functions,
and tasks as well as control over instantiations
 All generate instantiations are coded with a module scope and require the
keywords generate and endgenerate

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 Generate Blocks
 Generated instantiations‐ can be of the following types:
 Modules
 User defined primitives
 Verilog gate primitives
 Continuous assignments
 initial and always blocks
 Generated instances have unique identifier names and can be referenced
hierarchically
 For interconnection between structural elements and procedural blocks,
generate statements permit following Verilog data types to be declared within its
scope:
 net, reg
 integer, real, time, realtime
 event

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 Generate Block Example
module bitwise_xor(out, i0, i1);
parameter N = 32; // Declaring a 32‐bit bus by default
output [N‐1:0] out;
input [N‐1:0] i0, i1;
genvar j;
generate for (j=0; j<N; j=j+1)
begin xor_loop
xor uxor(out[j], i0[j], i1[j]);
end
endgenerate

endmodule
 Before the simulation, the simulator elaborates (expands) the code to create a flat representation
 genvar is a keyword used to declare variables that are used only in the evaluation of the generate block
 The value of genvar can be defined only by a generate loop
 Generate loops can be nested but only if the nested loops do not use the same genvar as an index
 Generate can be used for conditional statements including case.

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 Generate Block Example
 During elaboration time, the generate loop is expanded.
 The body of the for‐loop is replicated for each value of the iteration
xor xor_loop[0].uxor(out[0], i0[0], i1[0]);
xor xor_loop[1].uxor(out[1], i0[1], i1[1]);
…
…
xor xor_loop[N‐1].uxor(out[N‐1], i0[N‐1], i1[N‐1]);

 In the for‐loop, a variable is needed that is initialized and modified

on every iteration
 The generate block must have a label which is used for reference
bitwise_xor.xor_loop[0].uxor;
bitwise_xor.xor_loop[1].uxor;
…
…
bitwise_xor.xor_loop[N‐1].uxor;

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 Generate Block (contd.)
 During elaboration, all statements within the for‐loop are replicated.
 Our example had only one gate instantiation, but in general a
generate statement can contain procedural statements
 Generate‐conditional allows for conditional selection of statements
at elaboration time
 Condition must be a static condition, computable at elaboration
time
 Generate‐case is similar to generate‐conditional, except that a case
statement is used to model the conditional selection
 Read and understand these from Palanitkar’s book pp. 198‐200

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 Tasks
 A task is like a procedure, it provides the ability to execute common
pieces of code from several different places in a description.
 A task can contain timing controls, and it can call other tasks and
functions as well
 The inputs and outputs of a task are declared at the beginning of the
task, and specify the order to be used in a task call
 In addition to the task arguments, a task can reference any variable
defined in the module in which the task is declared
 A task can be declared automatic – all local variables that are
declared with the task are allocated dynamically for each task call
 A task is invoked by a task enable statement that specifies the
argument values and the variables that receive the results

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 Task Declaration and Invocation
Tasks are declared with the keywords task and endtask
Tasks must be used if any of the following conditions is true for the procedure
 There are delay, timing, or event control constructs in the procedure
 The procedure has zero or more than one output arguments
 Procedure has zero or more input arguments
Ports (input, output, inout) in a task are not used to connect external signals to
the module but to pass values to and from the task
Tasks can directly operate on reg variables defined in the module

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 Examples of Tasks
module operation; task bitwise_oper;
… output [15:0] ab_and, ab_or, ab_xor;
… input [15:0] a, b;
parameter delay = 10; begin
reg [15:0] A, B; #delay ab_and = a & b;
reg [15:0] AB_AND, AB_OR, AB_XOR; ab_or = a | b;
ab_xor = a ^ b;
always @(A or B) end
begin endtask
bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); …
end …
… endmodule
…

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 Examples of Tasks operation on variable defined in module
module sequence; task init_sequence;
… begin
… clock = 1`b0;
reg clock; end
… endtask
initial task assymetric_sequence;
init_sequence; //Invoking task begin
… #1 clock = 1`b0;
always #5 clock = 1`b1;
begin #7 clock = 1`b0;
assymetric_sequence; //Invoke another task end
end endtask
… …
… endmodule
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 Automatic or Re‐entrant Tasks
Tasks are normally static in nature
All declared items are statically allocated and they are shared across all
invocations of the task executing concurrently
This creates a problem of one invocation overwriting the items of a second
invocation. This will lead to wrong results
To avoid this conflict, a keyword automatic is added in front of the task keyword
All items declared inside such tasks are allocated dynamically for each invocation
For automatic tasks, each task operates in an independent space.
Use automatic tasks if there is a chance that a task might be called concurrently
from two locations in the code

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 Examples of Automatic Task
module top;
reg [15:0] cd_xor, ef_xor, c, d, e, f;
…
task automatic bitwise_xor;
output [15:0] ab_xor;
input [15:0] a, b;
begin
#10 ab_xor = a ^ b;
end
endtask
…
always @(posedge clk)
bitwise_xor(ef_xor, e, f);
…
always @(posedge clk2)
bitwise_xor(cd_xor, c, d)

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 Functions
 Functions also provide the capability to execute common code from
different places in the module.
 A function can return only one value
 A function cannot contain delays, timing, or event control
statements in the procedure
 A function cannot call any other task, and must have at least one
input
 No output or inout declarations are allowed in a function
 A function may call other functions
 Declared with keywords function and endfunction

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 Examples of Function for Parity Calculation
module parity;
reg [31:0] addr;
• Function definition will implicitly create an internal
variable of the same name as the function
reg parity;
• Illegal to declare another variable of the same name
always @(addr) inside the scope of the function
begin • Return value is initialized by assigning the function
parity = calc_parity(addr); result to the internal variable
$display(“Parity = %b”, calc_parity(addr));
• A function cannot contain any time‐controlled
end statements like #, @, wait, posedge, negedge
…
function calc_parity;
• A function cannot start a task because it may
consume simulation time, but can call other
input [31:0] address;
functions
begin
calc_parity = ^address; //xor of all address bits
end
endfunction
…
endmodule

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 Recursive Functions
A function that calls itself is called a recursive function
Recursive function is also called an automatic function
The keyword automatic can be used to declare a recursive function
Example of computing factorial is given on next slide
Homework: Fibonacci series?

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 Examples of Recursive Function
module top;
function automatic integer factorial;
input [31:0] oper;
begin
if (oper >= 2)
factorial = factorial(oper‐1) * oper;
else
factorial = 1;
end
endfunction

integer result;
initial
begin
result = factorial(4)
$display(“Factorial of 4 is %0d”, result)
end
endmodule

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 Tasks and Functions
Tasks and functions serve different purposes in Verilog
 Must be defined in a module and remain local to the module
 Functions are used when Verilog code is purely combinational.
Tasks Functions
A task can enable other tasks and functions Can enable another function but not another
task
May take non‐zero simulation time Always execute in 0 simulation time

Can contain delay, event, or timing control Cannot contain any delay, event, or timing
statements control statements
May have zero or more arguments of type Must have one or more input arguments
input, output, or inout
Do not return any value, but can pass multiple Always return a single value. Cannot have
values through output, and inout arguments output or inout arguments

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