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Pipeline Architecture

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Ngo Hoang Minh Nhat
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54 views33 pages

Pipeline Architecture

Uploaded by

Ngo Hoang Minh Nhat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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RISC-V

Pipeline Core
● Overview
● Implementation of Fetch Cycle
● Implementation of Decode Cycle
● Implementation of Execute Cycle
● Implementation of Memory Cycle
● Implementation of Write Back Cycle
● Implementation of Pipeline Top
● Pipeline Hazards
● Implementation of Hazard Unit
● Implementation of Pipeline Top II
Overview of RISC-V
Pipeline
Architecture
Pipelining
We design a pipelined processor by subdividing the
single-cycle processor into five pipeline stages.
Thus, five instructions can execute simultaneously,
one in each stage. Because each stage has only
one-fifth of the entire logic, the clock frequency is
approximately five times faster.
Pipelining
Pipeline Datapath
Implementation of
Fetch Cycle
Abstract View of Pipelining
Fetch Cycle Datapath PCSrcE

Modules to be Integrated:
1) PC Mux
2) Program Counter
3) Adder
4) Instruction Memory
InstrD
5) Fetch Stage Registers

PCD

PCPlus4D
PCTargetE
Implementation of
Decode Cycle
RegWriteW

Decode Cycle Datapath X

Modules to be Integrated:
1) Control Unit
2) Register File
3) Extender
4) Decode Stage Registers InstrD

PCD

PCPlus4D
X
RDW
ResultW
Implementation of
Execute Cycle
X

Execute Cycle Datapath

Modules to be Integrated:
1) AND Gate
2) Mux
3) Adder
4) ALU
5) Execute Stage Registers

X
Implementation of
Memory Cycle
Pipeline Datapath
X

Memory Cycle Datapath

Modules to be Integrated:
1) Data Memory
2) Memory Stage Registers

X
Implementation of
Write Back Cycle
Write Back Cycle Datapath

Modules to be Integrated:
1) Mux
Implementation of
Pipeline Top
Pipeline Datapath
Pipeline Hazards
Pipeline Hazard

● Structural Hazard
1. Hardware does not support the execution of instruction in same clock cycle.
2. Without having Two memories RISC-V pipelining architecture will have structural hazard.

● Data Hazard
1. Data to be executed is not available.
2. May occur when pipeline is stalled.
3. Solve by using forwarding or bypassing technique.
Data Hazard In Pipelining
Solution of Data Hazards

● Solving Data Hazards with nops


● Solving Data Hazard with Forwarding / Bypassing
Using Nops
Using Forwarding / Bypassing
Updated Pipeline Top Architecture
Implementation of
Hazard Unit
Condition Table
Condition for Data Hazard

Memory Stage WriteBack Stage


if (RegWriteM and (RdM != 0) and (RdM == Rs1E)) if (RegWriteW and (RdW != 0) and (RdW == Rs1E))
ForwardAE = 10 ForwardAE = 01

if (RegWriteM and (RdM != 0) and (RdM == Rs2E)) if (RegWriteW and (RdW != 0) and (RdW == Rs2E))
ForwardBE = 10 ForwardBE = 01

RegWriteW
ForwardAE
ForwardBE

RegWriteM
Rs2E
Rs1E

RdW
RdM
Implementation of
Pipeline Top II
Updated Pipeline Top Architecture
Thank You

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