ANALOG AND DIGITAL ELECTRONICS

UNIT – 3
1. Latch

• What it is: A latch is a basic memory device that stores one bit of data. It is level-triggered,
meaning it responds to input as long as a control signal (like Enable) is at a certain level (high
or low).

• How it works: The output can change whenever the control signal (Enable) is active.

• Types:

o SR Latch: Has two inputs, Set (S) and Reset (R).

Set Reset Output (Q)

(S) (R)
0 0 No Change (Holds
State)
0 1 Reset (Q = 0)
1 0 Set (Q = 1)
1 1 Invalid Condition

Explanation:

• Set (S): When 1, tries to set output to 1.

• Reset (R): When 1, tries to reset output to 0.
• Invalid: Both can't be 1 at the same time.

o D Latch: Has one input, Data (D). The output follows the input (D) when the enable
signal (EN) is active.

Enable (EN) Data (D) Output (Q)

0 0 No Change (Holds State)

0 1 No Change (Holds State)

1 0 Q=0
1 1 Q=1

Explanation:

• Enable (EN): Controls whether the latch responds to the data input.
• Data (D): The input data that sets the output when EN is active.
• Output (Q): Follows the input (D) only when EN = 1.
2. Flip-Flop

• What it is: A flip-flop is similar to a latch but it is edge-triggered, meaning it only responds to
changes at the edge of a clock signal (either rising or falling edge).

• How it works: The output only changes at the specific moment when the clock signal
transitions from 0 to 1 (rising edge) or from 1 to 0 (falling edge).

• Types:

o SR Flip-Flop: Similar to the SR latch, but it only responds on the clock edge.

▪ Set (S) = 1 and Reset (R) = 0 sets the output to 1 on the clock edge.

▪ Set (S) = 0 and Reset (R) = 1 resets the output to 0 on the clock edge.

▪ Invalid if S = 1 and R = 1 at the same time.

o D Flip-Flop: Like the D latch but only stores data at the clock edge.

o
▪ If D = 1 at the clock edge, the output becomes 1.

▪ If D = 0 at the clock edge, the output becomes 0.

 o JK Flip-Flop: Like the SR flip-flop, but when both inputs (J and K) are 1, it toggles the
output (switches between 0 and 1).

o
o T Flip-Flop: Toggles (switches) its state on every clock edge when T = 1.

o
Key Difference (Simplified):

• Latch: Changes when the control signal (Enable) is on. It keeps changing as long as the signal
stays on.

• Flip-Flop: Changes only at the moment the clock signal switches (like a button press). It doesn't
change again until the next clock switch.

Conversion of S-R Flip-Flop into D Flip-Flop

1. S-R Flip-Flop :
S-R flip-flop is similar to S-R latch expect clock signal and two AND gates. The circuit responds to
the positive edge of clock pulse to the inputs S and R.

2. D Flip-Flop :
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.
Conversion of S-R Flip-Flop into D Flip-Flop :

• Step-1:
We construct the characteristic table of D flip-flop and excitation table of S-R flip-flop.

• Step-2:
Using the K-map we find the boolean expression of S and R in terms of D.

S=D

R = D'

• Step-3:
We construct the circuit diagram of the conversion of S-R flip-flop into D flip-flop.

Conversion of S-R Flip-Flop into D Flip-Flop

1. S-R Flip-Flop :
S-R flip-flop is similar to S-R latch expect clock signal and two AND gates. The circuit responds to
the positive edge of clock pulse to the inputs S and R.

2. D Flip-Flop :
D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.

Conversion of S-R Flip-Flop into D Flip-Flop :

• Step-1:
We construct the characteristic table of D flip-flop and excitation table of S-R flip-flop.
• Step-2:
Using the K-map we find the boolean expression of S and R in terms of D.

S=D

R = D'

• Step-3:
We construct the circuit diagram of the conversion of S-R flip-flop into D flip-flop.

Conversion of J-K Flip-Flop into T Flip-Flop

1. J-K Flip-Flop: JK flip-flop shares the initials of Jack Kilby, who won a Nobel prize for his
fabrication of the world’s first integrated circuit, some people speculate that this type of flip flop
was named after him because a flip-flop was the first device that Kilby build when he was
developing integrated circuits. J-K flip-flop is the gated version of SR flip-flop with an addition of
extra input i.e. clock input. It prevents invalid output conditions when both the inputs are at the
same value.

2. T Flip-Flop: T flip-flop means Toggle flip-flop. It changes the output on each clock edge and
gives an output that is half the frequency of the signal to the input.

Conversion of J-K Flip-Flop into T Flip-Flop:

• Step-1: Construct the characteristic table of T flip-flop and excitation table of the J-K flip-flop.
• Step-2: Using the K map, find the boolean expression for J and K in terms of T.

J=T

K=T

• Step-3: Construct the circuit diagram for the conversion of the J-K flip-flop into a T flip-flop.

Conversion of J-K Flip-Flop into D Flip-Flop

JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is clock input. It
prevents the invalid output that may be obtained when both the inputs are 1. Whereas D Flip-
Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from
becoming the same value.

What is Flip-Flop?

A flip-flop is a basic component of digital electronics. This kind of circuit has two stable states and
is frequently used in storing one bit of information. Various flip-flops such as SR (Set-Reset), D
(Data or Delay), JK and T belong to this category. Each category has distinct features and
functions within digital circuits. Simply put, a flip-flop can preserve some binary value (0 or 1)
changing its output according to input signals received. Hence, it resembles computer memory
cell that retains certain data until it gets altered by new ones.

Conversion of J-K Flip-Flop into D Flip-Flop

Step-1: We construct the characteristic table of D flip-flop and excitation table of JK flip-flop.
Step-2: Using the K-map we find the boolean expression of J and K in terms of D.

J=D
K = D'

Step-3: We construct the circuit diagram of the conversion of JK flip-flop into D flip-flop.

Difference between JK Flip Flop & D Flip Flop

JK Flip-Flop D Flip-Flop
The JK flip flop has two inputs, J (set) and K Also called DFF, data or delay flip flop,
(reset), which determine what it does. has only one data input (D) and a clock
input.
It has two inputs, J and K, as well as a clock At the rising or falling edge of the clock
input. signal the output of a DFF switches to
the value of D input.
Based on the inputs J and K, JK flip flop can Because it acts according to clock
toggle its output between stable states (0 and signal during storage and transfer, it is
1). suitable for synchronization and
storage purposes.
Because of its ability to function as either DFF truth table is simpler than JKFF
toggle FFs or SR_FFs or data FFs depending on because it merely duplicates its input to
input state, it has a more complicated truth output.
table than any other type of flip flop.
Advantages of Flip Flop

Memory storage : Flip-flops can retain binary information (0 or 1) until something new is sent to
them. This function of keeping data is essential for sequential logic circuits like registers and
memories.

Synchronization : Data input and output timing can be controlled by using clock signals in flip-
flops. This synchronization guarantees that there will be no errors with processing data during
specific periods which is one of most important things for digital systems.

Controlled output : The output of a flip-flop can only change when it has been triggered by either
a clock signal or particular input conditions. With such behavior, it helps with making sure digital
circuits are stable and reliable.

versatility : Various types of flip-flops including D, JK, SR and T type flip-flops provide different
functionalities for different types of circuits requirements. Thus, this flexibility enables designers
implement a wide range of logical operations within short periods.

Sequential logic : In sequential logic circuits, where output depends not only on current input but
also previous state(s), flip-flop is an important element allowing us to perform complex
operations and algorithms in digital systems.
Disadvantages of Flip Flop

Complexity : As an example, the JK flip-flops have complex truth tables and multiple input
configurations making the design of their circuits more intricate and necessitating additional
logic for effective operation control.

Propagation Delay : Flip-flops introduce some delays in the circuit because it takes time for the
output to respond after changes in inputs. Such delays may affect speed and performance of a
digital system as a whole.

Power Consumption : Even when they are not changing state, flip-flops use power perpetually. In
large digital systems with many of them, their constant power drain leads to higher energy
consumption levels and heat generation rates.

Size and Cost : The implementation of more flip-flops within any given circuit leads to increased
size as well as manufacturing costs associated with that system which can be problematic
especially where there are space constraints or budget limitations as is often seen in most
applications.

How do shift registers move data?

We can feed and extract data to and from a shift register in two ways:

1. Serially: Data enters the cascade of flip-flops in a stream. Each bit passes through the
cascade in a line. We get the data output at the last flip-flop. The output is in the same order
as the input.

2. Parallel: Each flip-flop can have its own input. This particular setting of giving input is known
as parallel input. Similarly, each flip-flop can have its own output too. This is parallel output.

What are the uses of shift registers?

Since a shift register comprises of flip-flops, we can use them for the following general purposes

1. To shift data – Shift registers can shift data either to the right, to the left or in both directions.
In this post, we will look at shift registers where the data moves in the right direction.

2. To store data – The flip-flops shift data on the application of a clock pulse. In the absence of a
clock pulse, the shift register holds that data.

3. To produce a delay – The data can stay inside the shift register or pass through it. Either way,
the processes consume some clock cycles. So we can use them to introduce some delay if we
need it.

4. To convert between serial-parallel – Since we have both serial and parallel types of inputs
and outputs, we can use shift registers to convert serial data to parallel or vice versa.

Serial-In Serial-Out Shift Register (SISO)

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as a Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus
the name Serial-In Serial-Out Shift Register. The logic circuit given below shows a serial-in
serial-out shift register. The circuit consists of four D flip-flops which are connected in a serial
 manner. All these flip-flops are synchronous with each other since the same clock signal is
applied to each flip-flop.

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip flop. The main use of a SISO is to act as a delay element.

• Advantages: Simple design, minimal hardware required.

• Disadvantages: Slow data transfer rate due to serial processing.

Serial-In Parallel-Out Shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D
flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them. The output of the first flip-flop is connected to
the input of the next flip flop and so on. All these flip-flops are synchronous with each other
since the same clock signal is applied to each flip-flop.

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip-flop and producing a parallel output. They are used in communication
lines where demultiplexing of a data line into several parallel lines is required because the
main use of the SIPO register is to convert serial data into parallel data.

SIPO (Serial In, Parallel Out)

• Advantages: Converts serial data to parallel format, which can be used in systems that
require parallel processing.
• Disadvantages: Requires multiple output lines, which can increase complexity and hardware
costs.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and produces a serial output is known as a Parallel-In Serial-Out
shift register. The logic circuit given below shows a parallel-in-serial-out shift register. The
circuit consists of four D flip-flops which are connected. The clock input is directly connected
to all the flip-flops but the input data is connected individually to each flip-flop through a
multiplexer at the input of every flip-flop. The output of the previous flip-flop and parallel
data input are connected to the input of the MUX and the output of MUX is connected to the
next flip-flop. All these flip-flops are synchronous with each other since the same clock signal
is applied to each flip-flop.

A Parallel in Serial Out (PISO) shift register is used to convert parallel data to serial data.

PISO (Parallel In, Serial Out)

• Advantages: Converts parallel data to serial, which is useful for data transmission over serial
lines.
• Disadvantages: Slower to load data into the register compared to parallel processing, and
requires a shift register to convert data to serial form.

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-
Out shift register. The logic circuit given below shows a parallel-in-parallel-out shift register.
The circuit consists of four D flip-flops which are connected. The clear (CLR) signal and clock
signals are connected to all 4 flip-flops. In this type of register, there are no interconnections
between the individual flip-flops since no serial shifting of the data is required. Data is given
 as input separately for each flip flop and in the same way, output is also collected individually
from each flip flop.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.

PIPO (Parallel In, Parallel Out)

• Advantages: Fast data transfer, all bits processed simultaneously.

• Disadvantages: Requires many data lines and more complex hardware for parallel
connections.

Shift Register Counter

Shift Register Counters are the shift registers in which the outputs are connected back to the
inputs in order to produce particular sequences. There are basically two types:

• Ring Counter
• Johnson Counter

Ring Counter

A ring counter is basically a shift register counter in which the output of the first flip-flop is
connected to the next flip-flop and so on and the output of the last flip-flop is again fed back
to the input of the first flip-flop, thus the name ring counter. The data pattern within the shift
register will circulate as long as clock pulses are applied. The logic circuit given below shows
a Ring Counter.
Ring Counter Truth Table

The circuit consists of four D flip-flops which are connected. Since the circuit consists of four
flip-flops the data pattern will repeat after every four clock pulses as shown in the truth
table. A Ring counter is generally used because it is self-decoding. No extra decoding circuit is
needed to determine what state the counter is in.

Johnson Counter- A Johnson counter is basically a shift register counter in which the output
of the first flip flop is connected to the next flip flop and so on and the inverted output of the
last flip flop is again fed back to the input of the first flip flop. They are also known as twisted
ring counters. The logic circuit given below shows a Johnson Counter. The circuit consists of
four D flip-flops which are connected.

Johnson Counter Truth Table

An n-stage Johnson counter yields a count sequence of 2n different states, thus also known
as a mod-2n counter. Since the circuit consists of four flip-flops the data pattern will repeat
every eight clock pulses as shown in the truth table. The main advantage of the Johnson
counter is that it only needs n number of flip-flops compared to the ring counter to circulate a
given data to generate a sequence of 2n states.
 Johnson Counter

Applications of Shift Registers

• The shift registers are used for temporary data storage.

• The shift registers are also used for data transfer and data manipulation.
• The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time
delay to digital circuits.
• The serial-in parallel-out shift register is used to convert serial data into parallel data thus
they are used in communication lines where demultiplexing of a data line into several parallel
lines is required.
• A Parallel in Serial out shift register is used to convert parallel data to serial data.

Differences between Synchronous and Asynchronous Counter

There are two types of counters in digital logic circuit that are used to count the
numbers of bits and these types depends upon the clock pulse applied to the flip flops.

1. Asynchronous Counter:

These are the counters in which we do not use universal clock, main clock is only
applied to the first flip flop and then for rest of flip flops the output of previous flip
flop is taken as a clock.
ASYNCHRONOUS COUNTER

2. Synchronous Counter:

These are the counters in which we use a universal clock that is common to all flip
flops. The Circuit diagram of Synchronous Counter is given Below:
SYNCHRONOUS COUNTER

Difference Table:

Let’s see the difference between these two counters:

S.NO Synchronous Counter Asynchronous Counter

1. In synchronous counter In asynchronous
we use a universal clock counter main clock is only
that is common to all flip applied to the first flip flop
flops through out the and then for rest of flip flops
circuit. the output of previous flip flop
is taken as a clock.
2. Synchronous Counter is Asynchronous Counter is
faster in operation as slower as compared to
compared to synchronous counter in
Asynchronous Counter. operation.
3. Synchronous Counter Asynchronous Counter
does not produce any produces decoding error.
decoding errors.
4. Synchronous Counter is Asynchronous Counter is also
also called Parallel called Serial Counter.
Counter.
5. Synchronous Counter Asynchronous Counter
designing as well designing as well as
implementation are implementation is very easy.
complex due to increasing
the number of states.
6. Synchronous Counter will Asynchronous Counter will
operate in any desired operate only in fixed count
count sequence. sequence (UP/DOWN).
7. Synchronous Counter Asynchronous Counter
examples are: Ring examples are: Ripple UP
counter, Johnson counter. counter, Ripple DOWN
counter.
8. In synchronous counter, In asynchronous counter,
propagation delay is less. there is high propagation
delay.

Design Mod – N synchronous Counter

The value of N can be different from power of 2. Also, the counting sequence may be
random for example some cyclic code (8421, 2423 etc). The following method is
applied for designing for mod N and any counting sequence.

Design for Mod-N counter :

The steps for the design are –
Step 1 : Decision for number of flip-flops –
Example : If we are designing mod N counter and n number of flip-flops are required
then n can be found out by this equation.

N <= 2n

Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops(n)
required is
For n =3, 10<=8, which is false.
For n= 4,10<=16, which is true.

Therefore number of FF required is 4 for Mod-10 counter.

Step 2 : Write excitation table of Flip flops –

Here T FF is used

Excitation table of T FF.

Step 3 : Draw state diagram and circuit excitation table –

Counting Sequence of Decade counter

A decade counter is called as mod -10 or divide by 10 counter. It counts from 0 to 9

and again reset to 0. It counts in natural binary sequence. Here 4 T Flip flops are
used. It resets after Q3 Q2 Q1 Q0 = 1001.

Circuit excitation table –

Here Q3 Q2 Q1 Q0 are present states of four flip-flops and Q*3 Q*2 Q*1 Q*0 are next
counting state of 4 Flip flops. If there is a transition in current state i.e if Q3 value
changes from 0 to 1 or 1 to 0 then there’s corresponding T(toggle) bit is written as 1
otherwise 0.
 Circuit excitation table

Step 4 : Create Karnaugh map for each FF input in terms of flip-flop outputs as the
input variable –
Simplify the K map –

K map for finding minimal expressions.

Step 5 : Create circuit diagram –

Here negative edge triggered clock is used for toggling purpose.

• The clock is provided to every Flip flop at same instant of time.

• The toggle(T) input is provided to every Flip flop according to the simplified equation
of K map.
Circuit diagram

Timing diagram : Here toggling is used.

Characteristic table of T FF.

The state of a FF will change only when toggle input(T) of a FF is 1.

 Timing diagram of synchronous Decade counter

Explanation :

• Initially Q3 Q2 Q1 Q0 are 0 0 0 0.
• The sequence of counter can be verified from the timing diagram. At every falling
edge of the clock output Q0 toggles because T0 is connected to logic 1.
• T1 becomes 1 only when expression T1 = Q’3Q0 becomes 1 also if clock falling edge
occurs(because there is negative edge triggering) then the output state of T1 i.e Q1 will
change.
• T2 becomes 1 only when expression T2 = Q1Q0 becomes 1 also if clock falling edge
occurs then the output state Q2 will change.
• T3 becomes 1 only when expression T1 = Q3Q0 + Q2Q1Q0 resultant becomes 1 also if
clock falling edge occurs(because there is negative edge triggering) then the state of
Q3 will change.
• We get Output as Q3(MSB) Q2 Q1 Q0(LSB).
• After 10th falling edge the output state of all the FFs again becomes 0 0 0 0.