Electronic Devices and Circuits

(EL-1004)
LABORATORY MANUAL
FALL 2023

(LAB # 07)
Analysis and Implementation of Limiter (Clipper) and
Clamper Circuits
Engr. Kashif Ullah

Student Name: ___________________________

Roll No: _____________ Section: ___________

______________________________________________________________________________________________________________________________________________________

Date performed: _____________________, 2023

NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES,ISLAMABAD
Prepared
Manualby: Engr. Muhammad
Submission Sajjad
Date: ______________, 2023 Version: 2.14
Last Edited Engr. Kashif Ullah Updated: Fall 2023
by:
Verified by: Dr. Awais Ayub
_______________________________
LAB ENGINEER SIGNATURE & DATE
 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

MARKS AWARDED: /10

LAB 0 Analysis and Implementation of Limiter (Clipper)
: 7 and Clamper Circuits
Objectives of the Exercise:
 To analyze the function and operation of limiters (clipper) and clampers.
 Implementation of different clipper and clamper circuits to understand the procedure of getting
desired waveform.
Equipment Required:
 Rectifier diode (1N4007 (2))
 Zener diode: (6.8 V)
 Resistor (100 Ω, 1 kΩ , 2.2kΩ, 100 kΩ)
 Capacitor (1uF)
 Multi-meter.
 Bread board
 Oscilloscope.
Function generator
Theory:
Diode Clippers/ Limiters:
The primary function of a limiter is to limit a portion of an applied alternating (AC) signal. The
process is typically performed by a resistor-diode combination. A DC source can also be incorporated
to provide additional shifts of the applied voltage.
A double limiter limits both the positive and negative peaks of an input waveform. Single limiters
limit either the positive or negative peak. Clipping circuits are also called slicers, amplitude selectors
or limiters.
Types of Clippers:
1) Clippers may be classified into two types based on the positioning of the diode.
1) Series Clippers, where the diode is in series with the load resistance.
2) Shunt Clippers, where the diode is shunted across the load resistance.
2) According to biasing, the clippers may be classified as
1) Unbiased Clippers, which have no DC source for limiting input waveform
2) Biased Clippers, which have DC source for limiting input waveform.
3) According to level of clipping the clippers may be
1) Positive Clippers, which clip only positive half (either complete or partial) of waveform.
2) Negative Clippers, which clip only negative half (either complete or partial) of the waveform.
3) Combination Clippers, which clip both positive and negative part of waveform.
Basic Guideline:
1) In forward Bias state a diode could be modelled as a short circuit and in the reverse bias state it
could be modelled as an open circuit. In practice the forward bias situation is modelled with
Vd as 0.7V, while the reverse bias situation is modelled by a resistance of the order of several
Mega Ohms. This feature is used in the design of limiter/ clipper circuits.

EDC LAB NUCES, ISLAMABAD Page 2 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

2) When DC source is involved in the circuit, visualize the waveform while keeping the
channel on DC mode because AC mode excludes the offset added by the DC source.
3) Keep ‘R1’ very small as compared to ‘RL’ to avoid extra attenuation of signal.
Clampers:
Clampers are designed to clamp an alternating signal to a specific level without altering the peak-to-
peak characteristics of the waveform. The best approach to the analysis of clampers is to use a step-by-
step approach. The first step should be an examination of the network for that part of the input signal
that forward biases the diode. With the diode forward biased the voltage across the capacitor and
across the output terminals can be determined. For the rest of the analysis it is then assumed that the
capacitor will hold on to the charge and voltage level established during this interval of the input
signal. The next part of the input signal can then be analyzed to determine the effect of the stored
voltage across the capacitor and the open-circuit state of the diode.
The analysis of a clamper can be quickly checked by simply noting whether the peak-to-peak voltage
of the output signal is same as the peak-to-peak voltage of the applied signal. This check is not
sufficient to be sure the entire analysis was correct but it is a characteristic of clampers that must be
satisfied.
A voltage doubler is composed of two sections in cascade, a clamp and a peak rectifier. When excited
by a sinusoid the clamping section provides a clamped signal with one peak clamped to zero volts, and
other peak at twice the maximum amplitude. In response the peak detector section provides a voltage
of double the magnitude of input sinusoid. Because the output voltage is double the input peak the
circuit is called a voltage doubler.
A clamping circuit introduces (or restores) a D.C level to an A.C signal. Thus a clamping circuit is
also known as D.C restorer, or D.C reinserted or a baseline stabilizer. The following are two general
types of clamping:
1) Positive clamping occurs when negative peaks raised or clamped to ground or on the zero
level. In other words, it pushes the signal upwards so that negative peaks fall on the zero level.
2) Negative clamping occurs when positive peaks raised or clamped to ground or on the zero
level. In other words, it pushes the signal downwards so that the positive peaks fall on the zero
level.
Key Guidelines:
 A clamper adds a dc level to an AC voltage.
 Capacitor charges to near peak of input (Vp (in) – 0.7).
 Capacitor can only discharge through the RL.
 Since RL has high resistance, the capacitor discharges very little each period.
 Note that time constant should be large (at least 10 times the period of the input voltage).
 Since capacitor retains charge, it acts like a battery in series with the input voltage.

LAB TASKS
Task 1: Limiter Circuits:
1) Cut-in-voltage:
Determine the cut-in-voltage for the diode using the diode-checking capability of the DMM.
Vd =
EDC LAB NUCES, ISLAMABAD Page 3 of 11
 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

2) Single limiter:
Construct the limiting circuit of Figure-1. Give a sinusoidal input voltage with 8 Vp-p value at a
frequency of 1000 Hz. Observe the output on CRO.

Figure-7.1
Vin (amplitude) = ____________
Vin (frequency) = ____________
Sketch the input and output waveforms on the graph below. Label the peak voltages and time period of
input and output carefully.

3) Reverse the direction of diode in Figure-6.1 as shown in figure-6.2.

EDC LAB NUCES, ISLAMABAD Page 4 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

Figure-7.2
Sketch the (expected) input and output waveforms on the graph below. Label the peak voltages and
time period of input and output carefully.

4) Replace the diode in Figure-7.2 with a 6.8 V zener diode and provide a sinusoidal input voltage
with 16 Vp-p value at a frequency of 1000 Hz input and sketch the waveforms below:

Observations:

5) Biased single limiter:

EDC LAB NUCES, ISLAMABAD Page 5 of 11
 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

Construct the biased single limiter circuit of Figure-7.3. Give an input voltage of any amplitude at
least greater than VO (or give 8 Vp-p at a frequency of 1000 Hz).

Figure-7.3
Sketch the input and output waveforms on the graph below. Label the peak voltages and time period of
input and output carefully.

6) Double limiter:
Construct the double limiter circuit of Figure-7.4 (a). Give a sinusoidal input voltage of amplitude
at least greater than VO (or give the sinusoidal input of 8 Vp-p at a frequency of 1000 Hz).

Figure-7.4 (a)

Sketch the input and output waveforms on the graph below. Label the peak voltages and time period of
input and output carefully.

EDC LAB NUCES, ISLAMABAD Page 6 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

7) Double Limiter with Zener Diodes:

Construct the double limiter circuit using zener diodes using R = 2.2 kΩ, of Figure-7.4 (b). Give a
sinusoidal input voltage of amplitude at least greater than VO (or give the sinusoidal input of 16 Vp-
p at a frequency of 1000 Hz).

Figure-7.4 (b)

Sketch the input and output waveforms on the graph below. Label the peak voltages and time period of
input and output carefully.

EDC LAB NUCES, ISLAMABAD Page 7 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

Task 2: Clamper Circuits:

1) Construct the network of Figure-7.5.

Figure-7.5
i. Set the input voltage equal to square wave of arbitrary levels i.e. –3 V and +2 V and 1 kHz
from the signal generator.
ii. Using the value of Vout from part i., calculate VC and Vout for the interval of Vin that causes the
diode to be in the ON state.
(Calculated) VC = _________________
(Calculated) Vout = _________________
iii. Using the results of part ii, calculate the level of Vout after Vin switches to the other level and
turns diode OFF.
(Calculated) Vout = _________________
iv. Using the results of parts ii and iii sketch the expected waveform for Vout in figure below for
one full cycle of Vin.

Vout in
voltage- time
mode(Expected)

v. Sketch the actual input and output waveforms separately on the graph below. Label the peak
voltages and time period of input and output carefully.

EDC LAB NUCES, ISLAMABAD Page 8 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

vi. (Post Lab: v-vii) Reverse the diode of Figure-7.5. Determine the levels of VC and Vout for the
interval of Vin that causes the diode to be in the ON state.
(Calculated) VC = _________________
(Calculated) Vout = _________________

vii. Using the results of Part v. calculate the level of Vout after Vin switches to the other level and
turns diode OFF.
(Calculated) Vout = _________________
viii. Using the results of Parts v and vi sketch the expected waveform for Vout on Figure-4.

Vout in voltage-time mode(Expected)

EDC LAB NUCES, ISLAMABAD Page 9 of 11

 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

2) Effect of R:
a) Determine the time constant (τ=RC) for the network of Figure-7.5 for the interval of the input
signal that causes the diode to assume the OFF state and be approximated by an open circuit.
(Calculated) τ = _____________
b) Calculate the period of the applied signal and then determine half the period to correspond with
the time interval that the diode is in the OFF state during the first cycle of the applied signal.
(Calculated) T = ___________
(Calculated) T/2 = ___________
c) The discharge period of an RC network is about 5τ. Calculate the time interval established by 5τ
using the result of Part 2(a) and compare to T/2 calculated in Part 2(b).
(Calculated) 5τ = _____________

d) Change R to 1 kΩ and calculate the new value of 5τ.

(Calculated) 5τ = _____________
e) How does the 5τ calculated in Part 2(d) compare to T/2 of the applied signal? How would you
expect the new value of R to affect the output waveform Vout?

f) For R=1 kΩ in figure 7.5, provide the same square wave signal and observe the output. Record it
in graph below:

Vout for R=1 kΩ

g) Change R to 100 Ω and calculate the new value of 5τ.
(Calculated) 5τ = ____________
h) How does the 5τ calculated in the previous part compare to T/2 of the applied signal? What
effect will the lower value of R have on the waveform?

i) For R=100 Ω in Figure-1, provide the same square wave signal and record the observation in
graph below:
EDC LAB NUCES, ISLAMABAD Page 10 of 11
 Electronic Devices National University Roll No: __________
& Circuits of Computer and Emerging Sciences
07

Lab
(EL-1004) Islamabad

#
_________________________________________________________________________________

Vout for R=100 Ω

3) Voltage Doubler:
a) Construct the circuit of Figure-7.6.

Figure-7.6
b) Give a sinusoidal input of 8 Vp-p at f =1 kHz.
c) View vout on oscilloscope and trace the result on graph below:

Observations:

EDC LAB NUCES, ISLAMABAD Page 11 of 11