STION ONE [30 MARI 2) Define the term “adress decowling’ as used an merry ystems and use a sketch 10 explain the full address decoding technique. [9 Marks} beewcer SAM and DRAM memories {8 matks} [4 Marks} four features/parameters to distinguish (hy Use at {¢) Hyplain the function of the following software (i) Linker (iy Emulator (d) Explain the ports of the 82554 PPL and their contrat [9 Marks} QUESTION TWO [20 MARKS] (a) Peripheral devices required for a system depe ms of the chips Intel $255, 8259, and 8251 when system x liv aual applications. Explain the use cetezid 1 the 8086 microprocessor-based [6 Marchi} ( Faplaany hice advantages ofthe assem as a ofi~a esevelopment ool, [6 Maks] fe) A control word is given as CW. ALL Using this pafor etic, explain the n and modes of 8255A ports [8 Marks} (QUESTION THREE [20 MARKS] (a), Write contro! word to reset PC2, In your response ex; lin sach resultant bit ofthe Control Word. [6 Macks} () An 8085 microprocessor-based system requires 4K <8 of RAM memory and IK x 8 of ROM tnemory, Available are 2K x 8 RAM chips an 1K «4 +GM chips. Design the required mry system and interface ito the 8O8S rmstuproet te Im your answer, show the following {Memory map segment if RAM memory stas 2: cary Toeation OOOOH followed by the ROM memory. [8 Marks} Gi) Block diagram showing how the memory syster i: interfaced to the $085 ticroprocessor. [6 Marks} QUESTION FOUR [20 MARKS} (a) Explain key factors tobe considered when choos.ny be! w+ en a microprocessor and a microcontroller, [6 Marks} (b) Use an example and a sketch to explain the word avdresse nl [6 Marks} {@) Usea sketch to explain the double handshake Jats ane used with 8255A PPL, (8 Marks) xe TION FIVE [20 MARKS] ae (a). Determine the contol word required to configure Port + ostpat in Mode-1, Port B as input in ‘Mode @ and Port C as inp. [10 Marks] (b) A word addressable memory system is specified ss 4K + $ aral isto be implemented using 2K x. 4 RAM chips. Determine: : [10 Marks} (i). The number of chips required forthe menory stam (i) The number of address bits needed pet chip(iii) ‘The number of memory banks (is) The number of address bits needed for the whole memory system using the word- addressable technique. (¥) Sketch the memory system when using low-order interleaving technique.FACULTY OF ENGINEERING AND THE HU IL T ENVIRONMENT SCHOOL OF ELECTRICAL AND ELI C1 RONIC ENGINEERING BACHELOR OF TECHNOLOGY IN ELECTRIC AL & ELECTRONIC ENGINEERING YEAR IV SEMESTER IC EEET 471; MICROPROCESSOR SYSTEMS \ND APPLICATIONS. f: 2.0 HOURS. INSTRUCTIONS TO CANDIDAT 1) Attempt Question One (Compulsory) and any her TWO Questions 2) All questions carry marks as indicated against them 3) All working MUST be elearly shown on the answer sce 4) Do NOT answer more than THREE, questions §5) Star each question ona fiesh page 6) Mobile phones ate prohibited in examination rooms OWING: YOU SHOULD HAVE THE FOL © Answer booklet # Scientific ealeulatorTECHNICAL UNIVERSITY OF KENYA ENGINEERING, YEAR 4.2 AfDB PROGRAM APRIL 2024 EEEL 471 Microprocessors Systems caT2 Duration: 1 hour Question One we (2) Explain the function of the assembler as a low-level language system development too! mention three files associated with it. [6 Marks] (b) Explain the function of the following software development tools. @ Linker [4 Marks] Gi) Emulator Question Two (@) Use atiming diagram to explain the Simple Strobe VO parallel data transfer method. [5 Marks) given as CW = 82H. Using this information, explain the direction and modes (b) Acontrol word is [7 Marks] of 8255A porss. (©) Determine the control word ‘Mode 1 and Port C as input. required to configure Port A as output in Mode 0, Port B as input in [8 Marks} _ be c Bec ‘ bi a a o pip he: = Dems ¢ De A Dye pa a 7H t re & oe ls r Dredg MC ry * >) SF BACHELOR OF TECHNOLOGY IN ELECTRICAL & i ee i,