LOGIC GATES AND FLIP FLOPS

Unit – 02 : LOGIC GATES AND FLIP FLOPS :

 Definitions, symbols and truth table of
 Basic gates NOT, OR, AND.
 Universal gates NAND, NOR.
 Special gates XOR, XNOR.
 De Morgan’s Theorems.
 Sum of Product, Product of Sum, Min term , Max term,
 Karnaugh-Map ,
 Logical diagram, truth table, Flip -Flops-
 RS, T, D, JK, Master/ Slave JK and timing diagram.
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Standard form of Boolean Expressions

 All Boolean expressions can be converted into either of two standard forms :
1. Sum-of Product(SOP)
2. Product-of-Sum(POS)

What is SOP ?
 SOP stands for Sum of Products( ∑ ).
 The product terms are also known as min-terms(m).
 When two or more product term are ORed, then the resulting expression is called SOP.
Example :
AB + BCD
ABC + CDE + BCD
 A product term is equal to 1 if and only if each of the literals in the term is 1.
 A product term is equal to 0 when one or more literals are 0.
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Conversion of a general expression to SOP :

a) (A + B)(C + B )
b) (A + BC)C
c) (A + C)(B + AC )
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The standard SOP :

Q1. Convert it into standard SOP function F = AB + A C + B C
Q2. Convert the Boolean expression F = ABC + BCD + ACD
Q3. Convert the Boolean expression F = ABC + AB + ABCD
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What is POS ?
 POS stands for Product of Sums( ∏ ).
 The sum terms are also known as max-terms(M).
 When two or more sum terms are multiplied, then the resulting expression is called POS.
Example :
(A + B) + (B + C + D)
(A + B + C)(C + D + E)(B + C + D)
 A sum term is equal to 0 if and only if each of the literals is 0.
 A sum term is equal to 1 when one or more of the literals in the term are 1.
LOGIC GATES AND FLIP FLOPS
 LOGIC GATES AND FLIP FLOPS

Canonical Form (Standard SOP and POS Form)

 Any Boolean function that is expressed as a sum of minterms or as a product
of max terms is said to be in its “canonical form”.
 It mainly involves in two Boolean terms, “minterms” and “maxterms”.

Conversions of Canonical Forms

There are 2 steps to follow to convert the canonical form of the equations.

Step 1: Interchanging the operational symbols, Σ and Π in the equation.

Step 2: Writing the indexes of the terms that are not presented in the given form

of equation.
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Conversion of SOP to POS form

Example:
The SOP function
F = ∑ A, B, C (0, 2, 3, 5, 7)
= A’ B’C’ + A’BC’ + A’BC + AB’C + ABC
Step 1: changing the operational sign to Π
Step 2: writing the missing indexes of the terms 1, 4 and 6.
1 = 001 = (A + B + C’)
4 = 100 = (A’ + B + C)
6 = 110 = (A’ + B’ + C)
Writing down the new equation in the form of POS form,
F = Π A, B, C (1, 4, 6)
= (A+ B+ C’)(A’+B+C)(A’+B’+ C)
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Conversion of POS to SOP form

Example :
The POS function
F = Π x, y, z (2, 3, 5)
= (x+y’+z)(x+y’+z’)(x’+y+z’)
 For getting the SOP form the POS form, we have to change the symbol ∏ to ∑.
 After that, we write the numeric indexes of missing variables of the given Boolean function.

So the SOP form is:

F = Σ x, y, z (0, 1, 4, 6, 7) = (x'y'z') + (x'y'z) + (xy'z') + (xyz') + (xyz)
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Introduction of K-Map (Karnaugh Map)

 In digital circuits and practical problems we need to find expression with minimum variables.
 We can minimize Boolean expressions of 3, 4 variables very easily using K-map without using
any Boolean algebra theorems.
 So it is known as minimization technique.
 It can take two forms SOP and POS according to the need of problem.
 K-Map is aa array of squares(cell) in which each squares represents a binary value of the
input variable.
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Steps to solve expression using K-map

1. Select K-map according to the number of variables.
2. Identify minterms or maxterms as given in problem.
3. For SOP put 1’s and for POS put 0’s in blocks of K-map.
4. Make rectangular groups containing total terms in power of two like 2,4,8 and try to
cover as many elements in one group.
5. From the groups made in step 5 find the product terms and sum them up for SOP form.
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1. K-map of 3 variables Z= ∑A,B,C(1,3,6,7)

Final expression (A’C+AB)

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K-map for 4 variables F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)

Final expression (QS+Q’S’)

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K-map of 3 variables – F(A,B,C)=π(0,3,6,7)

Final expression – (A' + B’) (B’ + C’) (A + B + C)

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K-map of 4 variables – F(A,B,C,D)=π(3,5,7,8,10,11,12,13 )

Finally we express these as product – (C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)

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What is Flip Flop ?
 A circuit that has two stable states is known as a flip flop. A flip-flop is a memory element which is
capable of storing one bit of information.
 It has two outputs, one for normal value and other for complement value.
 A flip flop is also known as bistable multivibrator.
 It is a sequential circuit which generally samples its inputs and changes its outputs only at particular
instants of time and not continuously.
 There are 4 types of Flip-Flop :
1) S-R FF
2) J-K FF
3) D - FF
4) T - FF
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S-R Flip Flop
 It is basically S-R latch using NAND gates with an additional enable input.
 It is also called as level triggered SR-FF.
 In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.
Block Diagram

Truth Table

Circuit Diagram
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J-K Flip-Flop
 The basic S-R NAND flip-flop circuit suffers from two basic switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
2. if Set or Reset change state while the enable input is high the correct latching action may not occur.
 Then to overcome these two fundamental problems, JK flip Flop was developed.
 The inputs are labeled J and K in honor of the inventor of the device, Jack Kilby.
Circuit Diagram
Truth Table
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D Flip Flop
 D Flip Flop is known as Delay Flip Flop.
 D-FF is simple S-R latch with a NAND inverter connected between S and R inputs.
 It has only one input.
 The input data is appearing at the output after some time, due to this data delay between i/p and o/p,
it is called delay flip flop.

Circuit Diagram

Truth Table
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T Flip Flop
 Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together.
 It has only input denoted by T as shown in the Symbol Diagram.

Circuit Diagram

Truth Table
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Race Around Condition In JK Flip-flop

 For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle
as long as CLK is high, which makes the output of the flip-flop unstable or uncertain.
 This problem is called race around condition in J-K flip-flop.
 This problem (Race Around Condition) can be avoided by ensuring that the clock input is at
logic “1” only for a very short time.
 This introduced the concept of Master Slave JK flip flop.
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Master-Slave JK Flip Flop

Circuit Diagram
 The Master-Slave Flip-Flop is basically a
combination of two JK flip-flops
connected together in a series
configuration.
 Out of these, one acts as
the “master” and the other as a “slave”.
 The output from the master flip flop is
connected to the two inputs of the slave
flip flop whose output is fed back to inputs
of the master flip flop.
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Timing Diagram of a Master flip flop

1. When the Clock pulse is high the output of master is high and
remains high till the clock is low because the state is stored.
2. Now the output of master becomes low when the clock pulse
becomes high again and remains low until the clock becomes
high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but
not the slave thus the output of the slave remains low till the
clock remains high.
5. When the clock is low, the slave becomes operational and
remains high until the clock again becomes low.
6. Toggling takes place during the whole process since the
output is changing once in a cycle.
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