VLSI SYSTEM DESIGN

logic synthesis using VHDL

Lecture #19
CMOS Inverter Delay Estimation
CMOS Inverter Capacitances
❖The parasitic capacitance associated with MOSFET
--Cgd, Cgs, gate overlap with diffusion
--Cdb, Csb, voltage dependent junction capacitance
--Cg, the thin-oxide capacitance over the gate area
--Cint, the lumped interconnect capacitance
❖Load capacitance
Fig.1. Cascaded CMOS inverter
Cload= Cgd,n + Cgd,p + Cdb,n + Cdb,p + Cint + Cg
• Csb,n and Csb,p have no effect on the transient behavior
of the circuit, since VSB=0
•The delay times calculated using Cload may slightly
overestimate the actual inverter delay
-- Charging, discharging
Fig.2. First stage CMOS inverter with lumped
output load capacitance
Delay-time definitions
❖The propagation delay is determined by the input-output signal delay during high
to low and low to high transition of the output.

Fig. Input and output voltage of typical CMOS inverter

Delay-time definitions
❖The rise time is defined as the time required for the output voltage to rise from
V10% to V90% level.
❖Similarly, the fall time is defined as the time required for the output voltage to
drop from V90% to V10% .

Fig. Output voltage rise and fall time

Calculation of the Delay-time
❖The simplest approach for calculating the propagation delay times τPHL and τPLH
❖Estimating the average capacitance current during charge down and charge up
How to Improve Delay?
• Minimize load capacitances
--Small interconnect capacitance
--Small Cg of next stage
• Raise supply voltage
--Increases current faster
• Increase transistor gain factor
--Increase transistor drive current for charging/discharging output capacitance
• Use low threshold voltage devices
--More sub-threshold leakage power dissipation
 MODULE#3

Lecture#20
Clocked Circuits
Circuit design style
❖Circuit performance and power dissipation largely depend on circuit design
style:
-Non-clocked style
-Clocked style
❖CMOS logic family, Pseudo nmos logic, pass transistor are examples of non –
clocked family.
Non-clocked Style (CMOS logic family)
❖ Standard CMOS is a Non-Ratioed logic family,
-The logic function will be correctly implemented regardless of device sizing.
-Device sizing will only affect the performance of the gate.

Fig. NOT Gate using CMOS

Ratioed logic
❖In CMOS, it is important to note that sizing considerations improved the
performance (speed) of the logic gates, but not their functionality.
❖Ratioed Logic is an attempt to reduce the number of transistors required to
implement a given logic function.
❖The concept of Ratioed Logic uses the same Pull-down network as CMOS but
uses a simple load as its Pull-up network.
❖ This Load constantly leaks current from the supply to the output capacitance.
In this way, the output is charged when the PDN is closed, providing a ‘1’.
Pseudo nmos logic family
❖The topology of a Pseudo nMOS gate is shown in the following figure:

❖The clear advantage of this gate over Standard CMOS is the reduced number
of transistors.
❖Reduce complexity, low capacitance, higher speed
❖N+1 transistors to implement an N-input gate.
❖But more power dissipation.
Pass-transistors
❖Transistors can be used as switches.
❖VDD and GND rails are the strongest 1 and 0.
❖NMOS passes strong 0
– But degraded or weak 1
❖PMOS passes strong 1
– But degraded or weak 0
❖Thus, NMOS are best for pull-down network
Pass- transistor logic
❖Pass transistor logic uses pass transistor to implement any logic function.
❖Generally, AND/OR logic are utilized to implement any function.

Fig. Pass-transistor implementation of an AND gate.

Pass- transistor logic
❖Advantages:
- few transistors
- high density
- low power consumption.
❖Disadvantages:
- resistance of the transistor alter depending upon the input voltages.
Pass- transistor logic
• Pass-transistor gates cannot be cascaded by connecting the output of a pass gate to
the gate input of another pass transistor.
 Lecture#21
Clocked/ Non-clocked Circuits
Differential Pass Transistor Logic
• For high performance design, a differential pass-transistor logic family, called CPL or DPL, is
commonly used. The basic idea is to accept true and complementary inputs and produce true and
complementary outputs.
 Differential Pass Transistor Logic
• Since the circuits are differential, complementary data inputs and outputs are always available.
Generating differential signals requires extra circuitry.
• Furthermore, the availability of both polarities of every signal eliminates the need for extra
inverters, as is often the case in static CMOS or pseudo-NMOS.
• CPL belongs to the class of static gates, because the output-defining nodes are always
connected to either VDD or GND through a low resistance path.
• The design is very modular. In effect, all gates use exactly the same topology. Only the inputs
are permutated. This makes the design of a library of gates very simple.
Transmission gate
❖The most widely-used solution to deal with the voltage-drop problem is the use of
transmission gates. NMOS devices pass a strong 0 but a weak 1, while PMOS
transistors pass a strong 1 but a weak 0.
Transmission gate
❖Advantages:
-more ideal switch compared to pass transistor.
- resistance of the transistor is not going to be dependent on the input/output voltages.
- more compatible with CMOS logic family.
Dynamic Logic: Basic Principles
• With the addition of a clock input
-it uses a sequence of pre-charge and
conditional evaluation phase
• The PDN (pull-down network) is
constructed exactly as in complementary
CMOS.
• Operation of this circuit is divided into two
major phases: pre-charge and evaluation
with the mode of operation determined by
the clock signal CLK.
Pre-charge
• When CLK = 0, the output node Out is pre-charged to VDD by the PMOS
transistor Mp .
• During that time, the evaluate NMOS transistor Me is off, so that the pull-
down path is disabled.
Evaluation
• For CLK = 1, the pre-charge transistor Mp is off, and the evaluation transistor Me is
turned on. The output is conditionally discharged based on the input values and the
pull-down topology.
• If the inputs are such that the PDN conducts, then a low resistance path exists
between Out and GND and the output is discharged to GND.
Important properties for the dynamic logic gate
• The logic function is implemented by the NMOS pull-down network.
• The number of transistors is lower than in the static case: N + 2 versus 2N.
• It is non-ratioed.
• It only consumes dynamic power.
• The logic gates have faster switching speeds.
-due to the reduced load capacitance
-dynamic gate does not have short circuit current
 Lecture#23
Dynamic logic circuits
Speed and Power Dissipation of Dynamic Logic
• The main advantages of dynamic logic are increased speed and reduced
implementation area.
-After the pre-charge phase, the output is high. For a low input signal, no
additional switching occurs. Tplh=0
-The high-to-low transition, requires the discharging of the output
capacitance through the pull-down network.
-Tphl is proportional to CL and the current-sinking .
-The presence of the evaluation transistor slows the gate as it presents an
extra series resistance.
-Omitting this transistor, may result in static power dissipation and
potentially a performance loss.
Speed and Power Dissipation of Dynamic Logic
• When evaluating the power dissipation of a dynamic gate,
- Physical capacitance is lower since dynamic logic uses fewer transistors
-Dynamic gates do not exhibit short circuit power since the pull-up path is
not turned on when the gate is evaluating.
-Dynamic logic gates by construction can at most have one transition per
clock cycle. Glitching (or dynamic hazards) does not occur in dynamic logic.
Issues in Dynamic Design
• Dynamic logic clearly can result in high performance solutions compared to static
circuits, but has some limitations:
-Charge leakage
-Charge sharing
- Clock skew
Charge Leakage
• The operation of a dynamic gate relies on the dynamic storage of the output value on
a capacitor.
• If the pull-down network is off, the output should ideally remain at the pre-charged
state of VDD during the evaluation phase.
• However, this charge gradually leaks away due to leakage currents.
Charge Leakage
• The operation of a dynamic gate relies on the dynamic storage of the output value on a
capacitor.
• If the pull-down network is off, the output should ideally remain at the pre-charged
state of VDD during the evaluation phase.
• However, this charge gradually leaks away due to leakage currents.
Charge Leakage
• The leakage problem van be counteracted by reducing the output
impedance on the output node during evaluation.
 Lecture#24
Dynamic and Domino logic circuits
Charge Sharing
• Another important concern in dynamic logic is the impact of charge sharing.
• This causes a drop in the output voltage, which cannot be recovered due to the
dynamic nature of the circuit.
Cascading Dynamic Gates
• The cascading problem arises because the outputs of each gate and
hence the inputs to the next stages are pre-charged to 1. This may
cause inadvertent discharge in the beginning of the evaluation cycle.
Cascading Dynamic Gates
• On the rising edge of the clock, output Out1 starts to discharge. The second
output should remain in the pre-charged state of VDD as its expected value is 1
(Out1 transitions to 0 during evaluation).
• However, there is a finite propagation delay for the input to discharge Out1 to
GND. Therefore, the second output also starts to discharge.
Domino Logic
• A Domino logic consists of an n-type dynamic logic block followed by a static
inverter.
 Domino Logic
• Consider a chain of Domino gates. During pre-charge, all inputs are set to 0.
• During evaluation, the output of the first Domino block either stays at 0 or makes a 0🡪 1
transition, affecting the second gate. This effect might ripple through the whole chain, one
after the other.
Advantages
• Low power consumption
• Reduced chip area
• Higher speed of operation (only rising delay)
• No short circuit power dissipation
Limitations
• Inverting buffer is needed for each gate.
• All the gates are non-inverting in nature.
• Higher switching activity.

⮚ How to deal with non-inverting property of Domino logic?

- Reorganize logic using De-morgan’s theorem
- Dual- rail Domino logic
Dealing with the Non-inverting Property of Domino
Logic
• A major limitation in Domino logic is that only non-inverting logic can be implemented.
• Since the inputs to a Domino gate are low during pre-charge, it is tempting to eliminate the
evaluation transistor as this would reduce clock load and increase pull-down drive.
• However, eliminating the evaluation device extends the pre-charge cycle: the pre-charge now
has to ripple through the logic network as well.
Lecture#25

DESIGNING SEQUENTIAL LOGIC

CIRCUITS
Introduction
• Sequential circuits: the output not only depends upon the current values of
the inputs, but also upon preceding input values.

• This topic discusses the CMOS implementation of the most important

sequential building block.
Timing Metrics for Sequential Circuits
• There are three important timing parameters associated with a
register: set-up time, hold time and propagation delay of the
register.
Timing Metrics for Sequential Circuits
❖Assume that the worst-case propagation delay of the logic equals
❖The minimum clock period T, required for proper operation of the sequential circuit is
given by:
Classification of memory elements
Static versus Dynamic Memory
• Memories can be static or dynamic. Static memories preserve the state as long as
the power is turned on. Static memories are built using positive feedback or
regeneration,
• Example: SRAM
• Dynamic memories store state for a short period of time—on the order of
milliseconds. They are based on the principle of temporary charge storage on
parasitic capacitors associated with MOS devices.
• Example: DRAM
Latches versus Registers
• Latch:
It is level-sensitive circuit that passes the D input to the Q output when the
clock signal is high. This latch is said to be in transparent mode.
When the clock is low, the input data sampled on the falling edge of the clock
is held stable at the output for the entire phase, and the latch is in hold mode.
• Register:
Contrary to level-sensitive latches, edge-triggered registers only sample the
input on a clock transition — 0-to-1 for a positive edge-triggered register, and 1-to-0
for a negative edge-triggered register.
Latches versus Register
• A latch is an essential component in the construction of an edge-triggered register.
• It is level-sensitive circuit that passes the D input to the Q output when the clock signal is
high. This latch is said to be in transparent mode.

Figure: Timing of positive and negative latches.

The Bi-stability Principle
❖Static memories use positive feedback to create a bistable circuit — a circuit having two
stable states that represent 0 and 1.

Figure: Two cascaded inverters (a) and their VTCs (b)

Conventional 6T SRAM cell.
❖A typical SRAM cell is made up of six MOSFETs.
❖Each bit in an SRAM is stored on four transistors (P1, P2, N1 and N3) that form two
cross-coupled inverters.
❖This storage cell has two stable states which are used to denote 0 and 1.

Figure: Conventional 6T SRAM cell.

Lecture#26

DESIGNING SEQUENTIAL LOGIC

CIRCUITS
Multiplexer-Based Latches
❖One very common technique involves the use of multiplexers to implement the latch.
-it has the important added advantage that the sizing of devices only affects performance
and is not critical to the functionality.
Positive latch using transmission gate
❖A transistor level implementation of a positive latch based on multiplexers is shown in
Figure.
- When CLK is high, the bottom transmission gate is on and the latch is transparent -
that is, the D input is copied to the Q output. During this phase, the feedback loop is open
since the top transmission gate is off.
Multiplexer-based NMOS latch using NMOS
only pass transistors
• The use of NMOS only pass transistors results in the passing of a degraded high voltage
of VDD-Vtn to the input of the first inverter.
• This impacts both noise margin and the switching performance.
Master-Slave Edge-Triggered Register
❖A multiplexer-based latch is used in this particular implementation, although any latch could be
used. On the low phase of the clock, the master stage is transparent, and the D input is passed to
the master stage output,0
❖During the high phase of the clock, the slave stage samples the output of the master stage (QM),
while the master stage remains in a hold mode.
Master-slave positive edge-triggered
register using multiplexers
❖A complete transistor-level implementation of a the master-slave positive edge-triggered register
is shown in Figure. The multiplexer is implemented using transmission gates as discussed in the
previous section.
Disadvantages
❖The drawback of the transmission gate register is the high capacitive load presented
to the clock signal.
❖ The clock load per register is important, since it directly impacts the power
dissipation of the clock network.
❖Ignore the overhead required to invert the clock signal, each register has a clock load
of 8 transistors.
--One approach to reduce the clock load at the cost of robustness is to make the
circuit ratioed.
Lecture#27

DESIGNING SEQUENTIAL LOGIC

CIRCUITS
Dynamic Latches and Registers
❖Storage in a static sequential circuit relies on the concept that a cross-coupled inverter
pair produces a bistable element and can thus be used to memorize binary values.
❖This approach has the useful property that a stored value remains valid as long as the
supply voltage is applied to the circuit, hence the name static.
❖The major disadvantage of the static gate, however, is its complexity.
❖The principle is exactly identical to the one used in dynamic logic — charge stored on a
capacitor can be used to represent a logic signal.
❖The absence of charge denotes a 0, while its presence stands for a stored 1. No
capacitor is ideal, unfortunately, and some charge leakage is always present.
Dynamic Transmission-Gate Edge-triggered
Registers
❖A fully dynamic positive edge-triggered register based on the master-slave concept is shown in
Figure.
❖When CLK = 0, the input data is sampled on storage node 1, which has an equivalent capacitance of
C1 consisting of the gate capacitance of I1 , the junction capacitance of T1 , and the overlap gate
capacitance of T1.
❖On the rising edge of clock, the transmission gate T2 turns on, and the value sampled on node 1 right
before the rising edge propagates to the output Q.
Clock overlap
❖Clock overlap is an important concern for this register.
❖ During the 0-0 overlap period, the NMOS of T1 and the PMOS of T2 are simultaneously on,
creating a direct path for data to flow from the D input of the register to the Q output. This is
known as a race condition.
❖The 1-1 overlap region where an input-output path exists through the PMOS of T1 and the NMOS
of T2.
 Lecture#28
Introduction to VHDL
 Course Content
❖To learn about the VHDL hardware description language.
❖Knowing the difference between various styles of modeling.
❖Design Procedure of Digital System.
❖Review of Combinational and Sequential Circuits.
❖Designing of PLA and PLDs.
❖Designing of combinational circuits.
❖Design of some complex digital circuits.
 Digital System Design Procedure
❖Limitations with digital system design
--Scaling down the process technology increasing the design complexity
--Limitations associated with the fabrication is increasing but technology is improving.
--To model the hardware computer aided design (CAD) tool is required.
--Conflicting results due to advancement in technology in various performance parameters.
❖Need of Todays electronic circuits:
--Low power consumption
--High integral density
--High performance
Moore’s Law
❖Gorden Moore predicted that there will be exponential growth in no. of transistors inside the chip.

Fig. Moore law graph (Image source:

https://raw.githubusercontent.com/SingularityKChen/PicUpload/master/img/20200712091524.png)
Introduction
❖Digital system design is a system that is used for the implementation of the hardware.
❖Such as any combinational circuit, controller and microprocessor.
❖Designing steps:
--Specification is necessary.
--Device technology such as PLDs and FPGA.
--To design Digital system: Top down approach is followed.
--To design PLDs and FPGA: Applications, architecture and the interconnection and timing
synchronization is necessary.
--VHDL for the application of synthesis.
Introduction
• As integrated circuit technology has improved to allow more and more components on a chip,
digital systems have continued to grow in complexity.
• The early integrated circuits belonged to SSI (small scale integration), MSI (medium scale
integration), or LSI (large scale integration) categories depending on the density of integration.
• SSI referred to ICs with 1 to 20 gates,
• MSI referred to ICs with 20 to 200 gates, and
• LSI referred to devices with 200 to a few thousand gates. Many popular building blocks, such
as adders, multiplexers, decoders, registers, and counters, are available as MSI standard parts.
• When the term VLSI was coined, devices with 10,000 gates were called VLSI chips.
Introduction to VHDL
❖VHDL is hardware description language used to describe behaviour and structure of
digital system.
❖VHDL stands for VHSIC Hardware Description Language, where VHSIC is very high-
speed integrated circuit.
Design flow in modern digital system design
 Lecture#29
Introduction to VHDL
Spectrum of Design Technologies
Hierarchy in design
❖Bottom up approach:
Transistor 🡪 Gates 🡪 Combinational Circuits 🡪 Sequential Circuits 🡪
Controller/ uP 🡪 System

❖Top Down Approach:

System 🡪 Controller/ uP 🡪 Sequential Circuits 🡪 Combinational Circuits 🡪 Gates
🡪 Transistor
❖Generally top down approach is followed in hardware system designing.
Design: Top down approach for Multiplier
VLSI/Digital system design flow
❖It is the standardized procedure
-- to enlighten the system from general idea to hardware implementation.
❖It incorporates several steps:
-- System specifications
-- Design formulation (in terms of VHDL/Verilog coding)
-- Simulation
-- Design synthesis
-- Layout
-- Testability
-- Placing and routing
-- Fabrication
Role of CAD tools
❖The computer aided design (CAD) tool is used especially with HDLs.
❖It gives the formats for writing HDL codes for the actual design.
❖CAD tools convert the HDL inputs given to it in more informative outputs about the hardware in
HDL form.
❖The role of CAD tools is:
-- To convert information from behavioral level to register transfer level (RTL)
-- Register transfer level to gate level
-- Gate level to transistor level
--Transistor level to the layout level
Design flow in modern digital system design
Design Idea

Behavioral Design
Flow Graph, HDL code
Data Path Design
Bus/Register Structure
Logic Design

Gate/F-F Netlist
Physical Design
Transistor Layout
Manufacturing

Chip/Board
System Design flow steps
❖Behavioral Design:
--This step specify the actual function of the design: i.e, behavior.
--Behavior can be specify in many ways:
-Truth table or Boolean expression.
-State transition diagram or table (FSM)
-High level algorithm
-- After this step synthesis is necessary for the hardware implementation.
System Design flow steps
❖Data path design:
--It has the components like registers, adders, multipliers, multiplexers, decoders etc, which are
the generated netlist of register transfer level.
-- The generated netlist will be in the form of graph.
-- In a graph vertices depicts components and edges indicates interconnections among various
components.
-- the components may be any functional blocks, gates or flip-flops.
--Here the generated netlist is also called as structural design.
Logic Design
❖It generate the netlist into the form of basic gates and flip-flops.
❖The netlist may be in the form of standard cells. The standard cells depicts the pre-designed circuit
blocks (Basic gates, Mux, decoder etc.) with their already implemented layout design.
❖This is the stage where various techniques can be employed to optimize the various performance
parameters:
--To minimize delay of the circuit.
--Minimize the number of gates.
--To reduce dynamic power dissipation switching activities can be reduced.
 Lecture#30
Introduction to VHDL
 Physical Design
❖The final layout is generated in this stage, then it can be send for the fabrication.
❖The layout has many layers of polysilicon, semiconductor, metal etc.
❖These layers are in the form of rectangular shapes.
--the thickness and width of each layers are fixed.
--the minimum spacing is also decided according to DRC rules.
❖The final design may be an IC, FPGA or ASIC type of design.
Other steps in design flow
❖Simulation for Verification
--at logic level, switch level and circuit level
❖Testability analysis and Test pattern generation
--it is utilized to test the manufactured devices
Design Representation
Design representation
❖Design can be directly represented by Y-chart.
❖Y-chart shows the design steps in three main domain:
--Behavioral
--Structural
--Physical
❖These design steps complete your actual hardware implementation form specifications to the
fabrication.
Y-Chart
❖Y-Chart represents the actual representation of the different steps needed for the fabrication .
Behavioral Description
❖ For a given set of specified inputs what will be the response: the function of the system.
--The functionality of the design may be in the form of Boolean functions, truth table.
--Algorithm may be written in VHDL.
❖Example Full Adder:
--Two inputs X and Y
--One input carry (Cin)
--Carry output (Cout)
--Sum output (Sum)
❖The Boolean expression for the sum and carry out:
🡪 SUM=X XOR Y XOR Cin
🡪 Cout=(X AND Y) OR (X AND Cin) OR (Y AND Cin)
Structural Description
❖It describes how the internal components are interconnected.
--The components may be registers, adders, multipliers, multiplexers, decoders etc, which are the
generated netlist of register transfer level.
❖At the structural description different level of representations are there:
--functional or module level
--gate level
--transistor level
--hybrid level of abstraction is also possible
❖As we go through successive level of abstraction, more detailed information is revealed.
Structural Description
❖It shows the internal structure of the full adder and its interconnection.
Design Methodology
❖Front-End Design
❖Back-End Design
System on a Chip
❖System on a Board
--Components were put in bread board
--Interconnected with the help of wires
❖ System on a Chip
--Embedded System on Chip
❖Advantages:
--Reduced Power dissipation
--Reduced Chip Interconnects
--Reduced Device Size
 Lecture#31
Introduction to VHDL
History
❖The requirements for the language were first generated in 1981 under the VHSIC
program. In this program, a number of U.S. companies were involved in designing
VHSIC chips for the Department of Defense (DoD).
❖ Re-procurement and reuse was also a big issue.
❖Thus, a need for a standardized hardware description language for design, documentation,
and verification of digital systems was generated.
❖A team of three companies, IBM, Texas Instruments, and Intermetrics, were first awarded
the contract by the DoD to develop a version of the language in 1983.
❖VHDL language was standardized by the IEEE in December 1987; this version of the
language is now known as the IEEE Std 1076-1987.
Capabilities of VHDL
❖The language can be used as an exchange medium between chip vendors and CAD tool
users.
❖The language supports hierarchy.
❖The language supports flexible design methodologies: top-down, bottom-up or mixed.
❖The language is not technology-specific, but is capable of supporting technology-specific
features.
❖It supports both synchronous and asynchronous timing models.
❖Various digital modeling techniques such as finite-state machine descriptions, algorithmic
descriptions, and Boolean equations can be modeled using the language.
❖The language is publicly available, human readable, machine readable.
Hardware Abstraction
❖VHDL is used to describe a model for a digital hardware device. This model specifies the external
view of the device and one or more internal views.
❖The internal view of the device specifies the functionality or structure, while the external view
specifies the interface of the device through which it communicates with the other models in its
environment.
Hardware Abstraction
❖In VHDL, each device model is treated as a distinct representation of a unique device, called
an entity.
Modeling Styles
❖VHDL can describe a digital system at several different levels
-Behavioral
-Data flow
-Structural
Sequential vs Concurrent Statements
❖VHDL provides two different types of execution: sequential and concurrent.
❖Different types of execution are useful for modeling of real hardware.
-Sequential statements view hardware from a “programmer” approach.
-Concurrent statements are order-independent and asynchronous.
VHDL Description of Combinational Circuits
❖ VHDL models combinational circuits by concurrent statements. Concurrent statements are
statements which are always ready to execute.
❖These are statements which get evaluated any time and every time a signal on the right side of
the statement changes.
❖Here A, B, C, D and E are the Signals.
❖The symbol <= is the signal assignment operator. which indicates that the value computed on
the right side is assigned to the signal on the left side.
VHDL Description of Combinational Circuits
❖When we initially describe a circuit, we may not be concerned about propagation delays. If we
write :
C <= A and B;
E <= C or D;
❖this implies that the propagation delays are 0 ns.
❖In this case, the simulator will assume an infinitesimal delay referred to as ∆ (delta).
❖Assume that initially A = 1 and B = C = D = E = 0. If B is changed to 1 at time 1 ns, then C
will change at time 1+ ∆ and E will change at time 1+2 ∆.
❖Unlike a sequential program, the order of the preceding concurrent statements is unimportant.
If we write
E <= C or D;
C <= A and B;
the simulation results would be exactly the same as before.
Important points to remember
❖VHDL is not case sensitive; uppercase and lowercase letters are treated the same by the compiler
and by the simulator. Thus, the statements would be treated as same.

❖Signal names and other VHDL identifiers may contain letters, numbers, and the underscore
character (_). An identifier must start with a letter, and it cannot end with an underscore. Thus
C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are not.
❖Every VHDL statement must be terminated with a semicolon (;).
❖In a line of VHDL code, anything following a double dash (--) is treated as a comment.
❖ Words such as and, or, and after are reserved words (or keywords) which have a special meaning
to the VHDL compiler.
Important points to remember
❖In digital design, we often need to perform the same operation on a group of
signals. A one-dimensional array of bit signals is referred to as a bit-vector.
VHDL Modules
❖The structure of VHDL module can be defined as: Entity description and an
architecture description.
❖To declare the entity, we use:

❖The interface-signal declaration normally has the following form:

❖For example:
VHDL Modules
❖The architecture description of module:
VHDL Modules
• The entity description can be considered as the black box picture of the module
being designed and its external interface.

Fig. Black Box View of the Two-Gate Module Fig. VHDL Module with Two Gates
VHDL Modules
❖The entity declaration gives the name two_gates to the module. The port
declaration specifies the inputs and outputs to the module.
❖ A, B, and D are input signals of type bit, and E is an output signal of type bit.
❖The signal C is declared within the architecture since it is an internal signal.
Description of Full Adder Module
Hierarchy of 4-bit parallel adder
4-Bit adder

Full adder Full adder Full adder Full adder

Inputs Outputs Inputs Outputs Inputs Outputs Inputs Outputs

VHDL Program Structure
❖The Full-Adder module defined in previous lecture
taken here as a component in a system, which consists
of four full adders connected to form a 4-bit binary
adder.
❖We first declare the 4-bit adder as an entity.
--Since the inputs and the sum output are 4 bits wide, we declare
them as bit-vectors which are dimensioned 3 down to 0.
❖The Full-Adder as a component within the architecture
of Adder4.
❖The component specification is very similar to the entity
declaration for the full adder.
❖ Anytime a module created in one part of the code has
to be used in another part, a component declaration
needs to be used.
❖Fig: 4-bit binary parallel adder.
Structural Description of a 4-Bit Adder
Structural Description of a 4-Bit Adder
❖In preparation for simulation, we can place the entity and architecture for the Full-Adder
and for Adder4 together in one file and compile.
❖Alternatively, we could compile the Full-Adder separately and place the resulting code in
a library which is linked in when we compile Adder.
The Next step to be followed
❖After specifying the system in VHDL, two steps can be followed:
❖ Simulate the system and verify the operation
--Just running a program written in some high-level language.
--It requires a test bench, that specifies the inputs that are to be applied and the way the
outputs are to be displayed.
❖Use a synthesis tool to map it to hardware.
-- Convert it to a netlist of low level primitives.
-- The hardware can be Application specific Integrated Circuit (ASIC).
-- It can be Field Programmable Gate Array (FPGA).
The Next step to be followed
❖When the design is mapped to hardware, we do not need test bench for simulation any
more.
❖Signal can be actually applied from some source (e.g. signal generator), and the response
evaluated by some equipment (e.g. oscilloscope or logic analyzer.)
Hardware Target
❖ASIC
--It may be choice when high performance and high packing density is required.
--All logic cells, circuits or layouts are designed specifically.
--It requires high NRE cost and high volume (expected to be used in large numbers such as:
processor chips).
❖FPGA
--The mapping can be done in the laboratory itself with a FPGA kit and associated software.
--Design in terms of standard blocks.
--Medium NRE cost, Medium volume.
--Design time and complexity is less.
--More cost, Low performance.
SPARTAN FPGA KIT
Difference between Simulation and synthesis

VHDL module Test bench VHDL

module

Simulation
Synthesis

Evaluate
results ASIC FPGA
Synthesis Tools
❖Software tools for FPGA
--Xilinx ISE or Vivado for Xilinx FPGA kits.
--Other FPGA vendors also provides similar types of softwares.
❖Commercial CAD tools for ASIC:
--Tool suite from cadence
--Tool suite from Synopsys
Sequential Statements and VHDL Processes
❖The behavioral style architecture contains concurrent statements with sections of sequential
statements that describes the output of the circuit at discrete moment in given particular
inputs.
❖The behavioral architecture includes the following:
-process statements and sensitivity lists.
-Sequential statements
-Variables
❖It is used to describe both combinational and sequential logic.
❖Process: VHDL processes helps to model sequential logic.
❖A VHDL process has the following basic form: