VLSI SYSTEM DESIGN

logic synthesis using VHDL

 Lecture#1
Introduction to VLSI Design
Introduction
❖ Very large scale integration (VLSI) is the process of creating an IC by combining
thousands of transistors into a single chip. VLSI began in 1970s when complex
semiconductor and communication technologies were being developed.
❖ The microprocessor is a VLSI device. before the introduction of VLSI technology most
ICs had a limited set of functions they could perform.
❖ An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI
enable makers to add all of these into a single chip.
Why VLSI?
❖ Electronics of today and tomorrow
❖ Integration reduces manufacturing cost, almost no manual assembly
❖ Higher performance (speed) circuits
❖ Low power circuits for portable applications
❖ More mixed signal emphasis
--wireless hardware
--high performance signal processing
--sensors, actuators, and microsystems
Complexity and design

❖ Creating a design team provides a realistic approach

to complete a VLSI project, as it allows each person
to study small sections of the system.
❖ Needing hundreds of engineers, scientists and
technicians.
❖ Needing hierarchy design and many different Level
views
❖ Everyone of each level depends upon the computer
aided design (CAD) tools.
General overview of the design hierarchy
VLSI DESIGN FLOW
• VLSI – very large scale
integration – lots of
transistors integrated
on a single chip
• • Top Down Design –
digital mainly – coded
design – ECE 411
• • Bottom Up Design –
cell performance –
Analog/mixed signal –
ECE 41
 Lecture#2
Ideal Switches and Boolean Operations
VLSI chip type
• It can be divided into three categories:
❖ Full custom design: every circuit is custom designed for the project. It
is tedious and time consuming task.
❖ Application specific integrated circuits (ASICs): it allows designer to
create ICs for a particular application. ASICs are very popular for
prototyping and low–volume production. CAD tools are utilized for
this purpose.
❖ Semi-custom design :The majority of the chip is designed using a
group of predefined cells as building blocks.
Moore’s law
• Moore’s law:
• In 1965, Gordon
Moore realized there
was a striking trend;
each new generation
of memory chip
contained roughly
twice as much
capacity as its
predecessor, and each
chip was released
within 18-24 months
of the previous chip.
Switch-Level Boolean Logic
❖ Logic gates are created by using sets of controlled switches
❖ Characteristics of an assert-high switch
❖ NMOS acts like an assert-high switch

y = x • A, i.e. y = x, if A = 1
Series and Parallel switches

❖ Series connected switch

will act as AND
function.

❖ Parallel connected
switches will act as OR
function.
Switch-Level Boolean Logic
❖ Characteristics of an assert-low switch
❖ PMOS acts like an assert-low switch

y = x • A, i.e. y = x, if A = 0
Combining assert-high and assert-low switches
❖ NOT Gate
❖ a=1=>SW1 closed, SW2 open=>y=0=

❖ a=0=>SW1 open, SW2 closed=>y=1=a

CMOS Circuit Basics
❖ CMOS Complementary metal oxide
semiconductor uses 2 types of
MOSFETs to create logic functions:
--NMOS
--PMOS
❖ CMOS Power Supply – typically
single power supply – VDD, with
Ground reference
--VDD ranges from (0.6V) 1V to 5V
• --Logic Levels (voltage-based)
• --all voltages between 0V and VDD
 Lecture#3
MOSFETs as Switches
Introduction
❖ MOSFETs (Metal oxide semiconductor field effect transistor) structure
is created by superimposing several layers of conducting and
insulating materials to forms a sandwich like structure.
❖ CMOS technology provides two types of transistors : an n-type
transistor (NMOS) and a p-type transistor (PMOS).
❖ Transistor operation are controlled by electric fields so the devices are
also called Field effect transistors.
MOSFET as switch
❖ The gate of the MOSFET controls the flow of current between the
source and the drain.
❖ When the gate of an NMOS transistor is 1, the transistor is ON and
there is a conducting path from source to drain.
❖ When gate is low the NMOS transistor is OFF and almost zero
current flows from source to drain.
❖ A PMOS transistor is just opposite , being ON when the gate is low
and OFF when the gate is high.
❖ When gate is high PMOS transistor, no current flows.
MOSFET as switch
❖ MOSFETS are intrinsically electronic devices.
❖ To use them as controlled switches, we must define how to translate
between Boolean values and electrical parameters.

Fig.1 power supply connection Fig.2 Logic

definitions
MOSFET as switch
❖ At the circuit level we represent the variable x using a voltage Vx such
that :
• 0<=Vx<=VDD
❖ In general
• --Low voltages correspond to logic 0 values.
• --High voltages correspond to logic 1 values.
Dual power supply voltage
❖ Early generations of MOS circuits utilized both positive and negative
supply.
❖ VDD is positive supply whereas VSS is negative voltage supply.
MOSFET Threshold voltages
❖ Threshold voltage is defined as a
minimum gate to source voltage
that is necessary to form the
channel.
❖ If VGS<=VTN, the transistor will
act as an open circuit.
❖ For the NMOS to be in conducting
state, the gate to source voltage
should be greater than threshold
voltage.
VGS>= VTN
MOSFET Threshold voltages
❖ PMOS behaves in a
complementary manner.
❖ The source terminal is connected to
the ground and drain is side closest
to the ground.
❖ The PMOS will be OFF when
VSG<=VTP
❖ It becomes in conducting state
when VSG>=VTP
MOSFET Pass Characteristics
❖ Each type of transistor is better at passing (to output) one digital voltage than the
other
❖ NMOS passes a good 0 but weak 1
❖ When input is 1 at the output we get VDD-Vtn.
❖ But when 0 is applied we get good 0 at the output.

Fig.1. Logic 0 transfer Fig.2. Logic 1 transfer

MOSFET Pass Characteristics
❖PMOS passes a good (strong)1 but weak 0.
❖When input is 1 at the output we get VDD.
❖But when 0 is applied we get weak 0 at the output.

Fig.1. Logic 1 transfer Fig.2. Logic 0 transfer

Conclusion
❖ PMOS passes strong logic 1 voltages, but weak logic 0 levels.
--Use PMOS to pass logic 1 voltages of VDD.
❖ NMOS passes strong logic 0 voltages, but weak logic 1 values.
--Use NMOS to pass logic 0 voltages of VSS.
❖ When gate is low the NMOS acts as an open switch, when logic 1
is applied at the gate terminal it behaves as a closed switch.
❖ When gate is low the PMOS acts as a closed switch, when logic 1
is applied at the gate terminal it behaves as an open switch.
 Lecture#4
MOS series and parallel connection
NMOS Transistors in Series/Parallel Connection
❖ Transistors can be thought
as a switch controlled by
its gate signal.
❖ NMOS switch is closed
when control input is high.
❖ For performing AND
operation NMOSs should
be in series.
❖ FOR OR operation
NMOSs must be
connected in parallel.
PMOS Transistors in Series/Parallel Connection
❖ PMOS switch is closed when
control input is low.
❖ PMOS Transistors pass a
“strong” 1 but a “weak” 0.
❖ For performing AND-NOT
operation PMOSs should be
in parallel.
❖ FOR OR-NOT operation
PMOSs must be connected
in series.
CMOS Circuits
❖ Complementary CMOS logic gates consists of two blocks.
-- NMOS pull-down network
-- PMOS pull-up network
❖ Digital logic circuits are non linear networks that
use transistors as electronic switches to divert one
of the supply voltage to either VDD or 0 to the
output node.
❖ At every point in time (except during the switching
transients) each gate output is connected to either
VDD or VSS in a low-resistive path.
❖ The network insures that one switch is ON other
will be open.
❖ At the output node we always get inverted output.
CMOS Circuits _ Advantages
❖ MOSFET devices are fabricated on same chip. This causes density to be reduced and complex
fabrication process.
❖ CMOS devices consume negligible power and hence are preferred over MOS devices in
battery operated applications.
 Lecture#5
Realization of basic gates using CMOS
NOT Gate using CMOS
❖ The NOT or INVERT function is often considered the simplest
Boolean operation. It has an input A and at the output we get the
inverted output.

Fig.1 Logic symbol Fig.2 NOT Gate using CMOS

CMOS Inverter
❖ CMOS inverter Consists of two complementary MOSFETS PMOS and NMOS .
❖ The source terminal of the PMOS is connected to the VDD.
❖ The source terminal of the NMOS is connected to the GND.
❖ The drain terminal of both the MOSFETs are connected together, that is output (Out).
NAND Gate using CMOS
❖ Use a complementary NMOS/PMOS pair for each input.
❖ Connect the output node to the power supply VDD through PMOS.
❖ Connect the output node to ground through NMOS.

Fig.1 Logic symbol Fig.2 NAND Gate using CMOS

NOR Gate using CMOS
❖ Implementation of NOR gate utilizes same topology. It requires two
sets of complementary pairs, each driven by separate input.

Fig.1 Logic symbol Fig.2 NAND Gate using CMOS

Complex Combinational Logic
❖ Implement the function
• F(A,B,C,D)=
Demorgan’s Theorem
❖ NAND-OR rule
-- bubble=inversion

❖ NOR-AND rule
 Lecture#6
Physical structure of CMOS integrated
circuits
Integrated Circuit Layers
❖ The primary task of the VLSI designer is to
translate circuit schematics into silicon form; this
process is called physical design.
❖ CMOS integrated circuits are electronic switching
networks that are created on small area of a silicon
wafer using a complex set of physical and chemical
processes.
❖ Integrated circuits are a stack of patterned layers:
--Metals, good conduction, used for
interconnects
--Insulators (silicon dioxide), block conduction
--Semiconductors(silicon), conducts under
certain conditions Fig. Two separate material layers

❖ Stacked layers form 3-dimensional structures

Three-dimensional Structure
❖ Combining the top and side views of an IC allows us to visualize the three-dimensional structure:
--The side view illustrates the order of the stacking.
--Insulating layers separate the two metal layers so that they are electrically distinct.
--The patterning of each layer is shown by a top view perspective

(a) Side view (b) Top view

Fig. Layers after the stacking process is completed
Three-dimensional Structure
❖ The stacking order is established in the manufacturing process, and can not be altered by
the VLSI designer.

(a) Side view (b) Top view

Fig. Layers after the stacking process is completed
Interconnect Resistance and Capacitance
❖ Logic gates communicate with each other by signal flow
paths from one point to another
--Using patterned metal lines (interconnects)
--Current flow is governed by the physical
characteristics of the material and the dimensions of the
line
Fig.1. Symbol for a linear resistor
--Ohm’s law, V=IR
❖ Line resistance Rline: a parasitic (unwanted) electrical
element that cannot be avoided:

Fig.2. Geometry of a conducting line

Sheet Resistance Model
❖ Sheet resistance Rs, rewriting
(a) Top-view geometry

(b) Sheet resistance contributions

Fig. Top-view geometry of a patterned line

❖ We can determine how many ‘squares’ of the layer

are present from the top view of layout, Example R
= 8*Rs
 Lecture#7
Resistive and capacitive effects
 Capacitor
❖ Interconnect lines also exhibit the property of capacitance.
--In electronics, the element that stores charge is called
capacitor

--Since electric current is defined by the time derivative I

= (dQ/dt), differentiating gives the I-V equation Fig.1. Circuit symbol for a capacitor

❖ Capacitance exists between any two conducting bodies that

are electrically separated .
--For the interconnect line, the conductor is isolated from
the substrate by an insulating layer of silicon dioxide glass
-- So, the capacitance depends on the geometry of the
line

Fig.2. Geometry for calculating the line

Where is the permittivity of the insulating oxide F / capacitance
cm
Effects of R and C on performance Parameters
❖ Wires are important as they determine:
--Speed
--Power
--Noise
❖ So conventionally alternative layers run orthogonally.
Delay: RC Time Constant
❖ The interconnect line exhibits both parasitic resistance Rline [Ω]
and capacitance Cline [F].
(a) Physical structure
❖ Forming the product of these two quantities gives

❖ In high speed digital circuits, signals on an interconnect line are

delayed by time constant, which places a limiting factor on the
speed of the network.
❖ In high speed digital circuits, signals on an interconnect line are
delayed by , which places a limiting factor on the speed of the
network.
--VLSI processing are directed toward minimizing both Rline
and Cline.
--Circuit designers are then faced with creating the fastest
switching network within the limits of delay. (b) Circuit model
Fig. Time delay due to the interconnect
time constant
 MOSFETs
❖ MOSFET is a small area set of two basic patterned
layers that together act like a controlled switch
--The voltage applied to the gate determines the
electrical current flow between the source and drain
terminals (a) nFET symbol (b) nFET layers
❖ Assuming that the drain and source are formed on
the same layer, then this behavior can be used to Fig.1. nFET circuit symbol and layer equivalents
deduce that
--The gate signal G is responsible for the absence
or presence of the conducting region between the
drain and source region

(a) Open switch (b) Closed switch

Fig.2. Simplified operational view of an nFET

MOSFET Device Dimension
❖ Physical dimensions of a MOSFET
• L = channel length
• W = channel width
• W/L = aspect ratio
❖ Side and Top views

Fig.1. Layers used to create a MOSFET

(a) Side view (b) Top view

Fig.2. Views of a MOSFET
nFET and pFET
❖ The polarity of a FET (n or p) is determined
by the polarity of the drain and source regions.
❖ nFET: the drain and source regions are
labeled as “n+” to indicate that they are
heavily doped as in Figure (a).
❖ pFET: the source and drain regions are p+
sections that are embedded in an n-type “well”
layer as in Figure (b). (b) pFET cross section
(a) nFET cross section
❖ Metal contacts have been added to connect the
drain and source regions to other parts of the
circuit. Fig. nFET and pFET layers
❖ pn junction are formed between n+ regions
and the p type substrate to prevent current
flow between adjacent layers.