Enhancing VLSI Design Efficiency: Tackling Conges on and Shorts with

Prac cal Approaches and PnR Tool (ICC2)

Abstract: Effec ve management of conges on is crucial for ensuring the efficient and reliable
opera on of modern integrated circuits, which are becoming increasingly complex and densely
packed with millions of transistors. The objec ve of this paper is to illustrate conges on, shorts,
and prac cal approaches to fix both issues at lower/higher technology nodes. This paper also
includes PnR tool (ICC2) related commands and their uses to overcome the men oned issues.

Conges on: Conges on in VLSI (Very large-scale Integra on) design refers to the circumstance
when the number of rou ng tracks is less than the required rou ng tracks. These rou ng
resources are used to connect all the required wires between the different components of the
design. PnR tool highlights congested areas as red hotspots, as depicted in figure 1. As the
complexity of the design increases, conges on has become a major issue in chip design that
requires careful considera on and op miza on to ensure that the design meets the required
ming, power, and area constraints.

Fig-1

Conges on report:

• GRC: The term GRC is an abbrevia on of Global Rou ng Cells. During the ini al placement,
the core area gets divided into equally sized small squares called GRC.
• Overflow total: The summa on of the total number of overflow routes for all GRCs. In the
above report, it is 1,384,599.Overflow Max: “Both Dirs” means combined results for both
horizontal and ver cal rou ng direc ons. Max indicates the maximum number of
 overflow routes for a single GRC among all GRCs. For example, if there are 100 rou ng
tracks available at a GRC while 172 tracks are going through it, that means the overflow is
72 for this GRC. Overflow (%): The GRCs value is the total number of global rou ng cells
with any overflow/lack of rou ng resources. A GRC value of 426,013 indicates that
426,013 GRCs has an overflow among all GRCs. The overflow percentage (%) shows that
out of the total number of GRCs, a certain percentage GRCs have overflow.

• Note: It has been observed that GRC overflow percentage should be less than 1%;
otherwise, it would be difficult to route. If we proceed with rou ng with GRCs overflow
(%) of 34.2291 as shown in the report, the PnR tool will s ll complete rou ng, but there
will be lots of viola ons such as complex shorts and DRC viola ons. Addi onally, the
men oned issues will cause ming degrada on because it leads to an increase in the
length of the interconnect wires, which increases the capacitance and resistance of the
wires, thereby slowing down the propaga on of the signal.

Cause of conges on:

• Bad floorplan/inappropriate placement of macros.
• High standard cell density in a par cular area.
• High number of standard cells in close vicinity of macros, as shown in Figure 4.
• Rou ng blockages over standard cells, as shown in Figure 2.
• High port density, as shown in Figure 3.
• Scan chain reordering and mixing/swapping are restricted.
• Improper op miza on of netlist during synthesis.

Fig-2 Fig-3 Fig-4

Conges on allevia on Techniques:

• Placement blockages
 • Cell padding
• Keep out margin/HALO.
• Modify PG grid.
• Conges on driven placement.
• Try different techniques during synthesis like logical synthesis, topographical synthesis.
• SPG and non-SPG placement.
• Refine placement/floorplan.

o Placement blockages: Spread the standard cells if they are highly dense by crea ng
par al placement blockages, as shown in Figure 5. Alterna vely, restrict the placement of
standard cells in a par cular area if there is an immense lack of rou ng resources by
crea ng hard placement blockages, as shown in Figure 6.create_placement_blockage -
type par al -blocked_percentage 50 -boundary {{llx lly} {urx ury}} -name Par al_PB
o create_placement_blockage -type hard -boundary { {lrx lry} {urx ury} } –name Hard_PB

Fig-5 Fig-6

Keep out margin/Halo: Keepout margin is a region around the boundary of a macro in which
no other cells are placed. Keeping the placement of cells out of such regions avoids conges on
and net detouring and produces beHer Quality of result. In Figure –7, a keepout margin is created
around the macro.
o create_keepout_margin -type hard -outer {5 5 5 5 } [get_cells *macro_name*]
 Fig-7

Cell padding: Applying a keepout margin around standard cells is known as cell padding. When
a cell has a high number of pins like a mul bit flop, the demand for rou ng resources increases.
Hence, we restrict the placement of cells near these cells to avoid conges on.

Implemen ng cell padding:

o create_keepout_margin -type hard -outer {3.9200 3.9200 3.9200 3.9200} [get_cells
cell_name]
o Refine_opt/incremental placement.

Fig-8

Modify PG grid: To have maximum rou ng resources, one can try to reduce the number of PG
stripes or the width of stripes. However, this has a trade-off with electromagne c (EM) and IR
drop.

Topographic synthesis: At the very first stage, we perform logical synthesis and proceed to
further stages like DFT, PnR. The synthesis tool tries to op mize in the best possible way to have
a minimum netlist area and meet the required ming and power constraints. ALer one itera on
of PnR we have floorplan informa on like block shape, size, blockages, and physical cells. We
write out the DEF of the floorplan and give it back to the synthesis tool and rerun synthesis. Now
it has physical constraints as well, so it will generate a more precise netlist. Eventually, this will
have a low scope of conges on and other issues.

SPG and non-SPG placement: During topographical synthesis, the tool writes out DEF, which
is equivalent to coarse/ini al placement. Reading this DEF during placement for coarse placement
is called SPG placement. If we don’t consider DEF for coarse placement and let the PnR tool, do
it itself, it is non-SPG placement. One should try both techniques, as either one will be helpful for
conges on allevia on.
o set_app_op ons -name place_opt.flow.do_spg -value true
o read_def -add_def_only_objects {cells} -convert_sites <def file>
o Place_opt

Conges on related variable:

o set_app_op ons -name place_opt.place.conges on_effort -value high
o set_app_op ons -name place.coarse.cong_restruct_effort -value ultra
o set_app_op ons -name place.coarse.conges on_layer_aware -value true

o Refine placement: The refine placement performs incremental conges on

op miza on for congested designs. One should perform this aLer detailed
placement.refine_placement -effort high -conges on_effort high

Shorts: When the shape (small segment of net) of two different nets intersects/touches each
other in the same layer, a short is reported. As depicted in Figure –9, the small por on of the red
highlighted net is touching the yellow highlighted net. Since both nets are different and in the
same metal layer, a short occurs.
 Fig-9 Fig-10

Mi ga on: As depicted in Figure10, shiL the the red highlighted net to the leL. Now, they don’t
interfere with each other, and the short is fixed. To verify and report shorted nets, run one of the
following commands:
o Check_routes
o Check_lvs
If the design has shorts in single or double digits, they can be fixed manually quickly and easily.
However, if the design has shorts in mul ple thousands, the following approaches are preferred
to get rid of shorts.

1. Delete shorted nets and reroute them by running eco route while freezing the rest of the nets.
To remove shorted nets:

o Remove_routes -detail_route -global_route -shield_route -nets “$net_nam”

To route the removed nets:

o route_eco -open_net_driven true.

2. Run “route_detail”, which performs detail rou ng to help fix shorts and DRCs. The following
command performs detail rou ng with a maximum itera on of 5. Try running mul ple loops of
route_detail with increasing values of max_number_itera ons to minimize DRCs and shorts.

o route_detail –max_number_itera ons 5

3. If there are shorts at corners of the design, especially in a rec linear shape, to fix such shorts,
add a decent-sized rou ng blockage, as shown in Figure 11, at the shorted corner of the design
during the floorplan stage. Remove it during the rou ng stage once the detail route is done. ALer
removing the blockages, perform incremental detail route as demonstrated below.

o remove_rou ng_blockages *corner_blockages*

o route_detail -incremental true

Fig-11

4. If there are shorts in a specific layer’s region, to fix such shorts, limit the number of rou ngs in
that layer by applying a rou ng guide. A Rou ng guide must be applied during the placement
stage only. In the example below, we are only considering 70 % of the rou ng resources of metal
layer M2 to limit the rou ng.
Set bbox {{ 1125.8800 -210.1300} { 1404.2000 747.9400}}
create_rou ng_guide -layers METAL2 -ver cal_track_u liza on 70 -boundary $bbox -name rg1
Author: Ishu Shukla is a Physical Design engineer working with eInfochips, an Arrow company.
He holds a bachelor’s degree in Electronics and Communica on from VGEC, Ahmedabad. He has
more than 2 years of experience in ASIC design, including various technology nodes like 3nm,
5nm, 7nm, 28nm, 90nm, 110nm, and 180nm. Experienced in Place & Route, Sta c Timing
Analysis, Physical Verifica on, and Low-power technique implementa on.

References:
• ICC2 implementa on user guide - Version T-2022.03, March 2022
• ICC2 commands - Version T-2022.03, March 2022