C HAPTER 6 ARM PROGRAMMING WITH

E MBEDDED C
 S YLLABUS

Topic Fine Detailing No of Week

Hours
ARM • General purpose Input 04 1
Programming Output
with • Timer Mode
Embedded C • Pulse- Width Modulator
Configuration
 R EVISION

CPSR

Exception Handling

Memory Management

ARM Family
CISC &RISC
CPSR
 E XCEPTIONS

Exception Mode Description

Reset Supervisor When RESET pin is activated
Undefined Undefined It occurs when processor cannot decode the instruction.Try to
Instruction attempt undefined instruction
Software Supervisor It occurs when SWI Instruction is executed . Frequently invoke
Interrupt (SWI) an operating system routine
Prefetch Abort Abort It occurs when processor attempts to fetch instruction from
address without correct access permissions. This exception can
be generated as a result of breakpoint
Data Abort Abort It occurs when an instruction attempts to access data memory
without the correct access permission
IRQ (Interrupt IRQ It occurs When receives interrupt request by hardware on IRQ
request) Input on the processor.(for this I bit in CPSR should be 0)
FIQ (fast Interrupt FIQ It occurs when receives FAST interrupt request by hardware
request) can on FIQ Input on the processor (for this F bit in CPSR should
be 0 )
 E XCEPTION H ANDLING
 Exception handling- Exception handling covers the specific details of how the
ARM processor handles exceptions.

 When exception occurs, ARM stops the execution of current instruction.

Processor then copies the contents of CPSR to SPSR. Contents of program
counter are stored at R14 Loads Program Counter with vector memory address
corresponding to exception and transfers the control to the memory address
referred as exception vector in memory .

 To return from exception handler the CPSR is restored from SPSR and PC from
R14

 Interrupts-ARM defines an interrupt as a special type of exception.

 E XCEPTION H ANDLING

 Exception handling is the method of processing these

exceptions.
 Most exceptions have an associated software
exception handler—a software routine that executes
when an exception occurs.
 Data Abort exception
 will have a Data Abort handler. The handler first
determines the cause of the exception and then
services the exception. Servicing takes place either
within the handler or by branching to a specific
service routine
 M EMORY M ANAGEMENT

 Embedded System mostly use multiple memory

devices
 ARM processors use memory management hardware
to organize memory devices and protect system from
application trying to make inappropriate accesses to
hardware
 It has 3 types memory hardware
 No extension-do not provide any protection
 Memory Protection unit(MPU)-provides limited
protection
 Memory Management unit(MMU)- provides full
protection
 M EMORY M ANAGEMENT

 No extension
 Memory with no protection provides very little
flexibility
 It is used for small and simple embedded system that
requires no protection

 MPU
 Memory protection unit is used in simple systems that
use limited memory regions
 Special Processor registeres are used to control these
memory regions
 MPU is used in system where memory protection is
required but don’t have a complex memory mapping
 M EMORY M ANAGEMENT

MMU(FULL PROTECTION)
 It uses a set of translation table to provide extensive
control over memory
 The translation table are stored in main memory and
they provide virtual physical address translation as
well as access permissions
 It gives most compresnhensive memeory
management hardware and platform for multitasking
 ARM7 FAMILY

 Original ARM7 is based on earlier ARM6 and use

ARMv3 instruction set

 It is the current low end ARM core and is widely

used across a range of applications, mostly notably
in many digital mobile telephones.

 ARM7,3 volt compatible rework of ARM6

 ARM7TDMI,ARM7TDMI-S(implementing the
ARMv5TE instruction set) , ARM7J-S
ARM FAMILY
 T HE ARM7 FAMILY

 ARM7TDMI: An integer core with three-stage pipeline delivering

high performance together with very low power consumption on a
small die size. This outstanding combination makes the ARM7TDMI
processor the most widely shipped 32-bit embedded RISC
processor in the world

 ARM7TDMI-S: A synthesizable version of the ARM7TDMI core, ideal

for modern design flows where portability and flexibility are key

 ARM7EJ-S: An enhanced, synthesizable core with architecture and

instruction set extensions to support DSP operations and
accelerated execution of Java™ applications using ARM Jazelle™
technology

 ARM720T: An integer core with memory management unit and 8KB

unified cache for open platform applications such as Windows CE,
Linux, Palm OS and Symbian OS.
 F EATURES

 Established ,high volume 32 bit RISC architecture

 Small die size and very low power consumption
 High code density, comparable to 16 bit
microcontroller
 Wide choice of development tools
 Simulation models for leading EDA environments
 Available in 0.25µm.018µm,0.13µm processes
 Migration and support across new process technology
 K EY B ENEFITS

 All ARM7 family processors offer significant benefits

to developers and integrators:

 Established, high-volume 32-bit RISC architecture

 Fast time-to-market

 Wide choice of development tools

 Code-compatible upward migration path to ARM9™

and ARM10™ families allowing re-use of application
code

 Migration and support across new process

technologies
 A PPLICATIONS

 Basic wireless handset

 Pager
 Ink-jet/bubble-jet printer
 Digital still camera
 PDA
 Java-Enabled Applications
 Entry-level Java wireless handset
 Home automation
 Entertainment systems
 Gaming
 Information delivery
M ODULE 6
 A RM P ROGRAMMING WITH
E MBEDDED C

 General Purpose Input Output

 Timer Mode

 Pulse Width Modulation

 G ENERAL P URPOSE I NPUT
O UTPUT

 There are 2 32 bit ports

 Port 0
 Port 1
 Port 0 is 32bit I/o bit with individual direction controls for
each bit.28 pins can be of port 0 can be configured as
general purpose bidirectional digital I/O
 While port 0.31provides digital output function only
 Pin 0.24,0.26,0.27 are reserved and not available for use
 The operation of Port 0 depends upon the pin function
selected via the pin connect block
 G ENERAL P URPOSE I NPUT
O UTPUT

 Port 1

 The operation of Port 1 depends upon the pin

function selected via the pin connect block

 Pin 0 to 15 are not avaialble

 Pins 16 to 25 are reserved

 In effect very few pins are available and can be

used for GPIO
P IN C ONFIGURATION
 P IN C ONNECTION

 Each pin of the chip has maximum 4 functions. To select one

specific function for a pin,a multiplexer with 2 select pins is
necessary. The select pin function is provided bybits of
PINSEL registers
 Pin Function Select Registers are 32-bit registers. These
registers are used to select or configure specific pin
functionality.
 There are 3 Pin Function Select Registers in LPC2148:
 1. PINSEL0 : - PINSEL0 is used to configure PORT0 pins P0.0
to P0.15.
 2. PINSEL1 : - PINSEL1 is used to configure PORT0 pins P0.16
to P0.31.
 3. PINSEL2 : - PINSEL2 is used to configure PORT1 pins P1.16
to P1.31.
E XAMPLE -PINSELO REGISTER
R EGISTERS OPERATING TO 1
GPIO PIN
 R EGISTERS

 IOPIN: It is a GPIO Port Pin Value register and can be used to read or write values directly
to the pin. The status of the Pins that are configured as GPIO can always be read from this
register irrespective of the direction set on the pin (Input or Output).The syntax for this
register is IOxPIN, where ‘x’ is the port number i.e. IO0PIN for PORT0 and IO1PIN for
PORT1.

 IODIR: It is a GPIO Port Direction Control register and is used to set the direction i.e.
either input or output of individual pins. When a bit in this register is set to ‘0’, the
corresponding pin in the microcontroller is configured as Input. Similarly, when a bit is set
as ‘1’, the corresponding pin is configured as Output.The syntax for this register is IOxDIR,
where ‘x’ is the port number i.e. IO0DIR for PORT0 and IO1DIR for PORT1.

 IOSET: It is a GPIO Port Output Set Register and can be used to set the value of a GPIO pin
that is configured as output to High (Logic 1). When a bit in the IOSET register is set to ‘1’,
the corresponding pin is set to Logic 1. Setting a bit ‘0’ in this register has no effect on the
pin.

 The syntax for this register is IOxSET, where ‘x’ is the port number i.e. IO0SET for PORT0
and IO1SET for PORT1.

 IOCLR: It is a GPIO Port Output Clear Register and can be used to set the value of a GPIO
pin that is configured as output to Low (Logic 0). When a bit in the IOCLR register is set to
‘1’, the corresponding pin in the respective Port is set to Logic 0 and at the same time
clears the corresponding bit in the IOSET register. Setting ‘0’ in the IOCLR has no effect on
the pin.
 TO GENERATE SQUARE WAVE

 To write a program to blink LED or to generate square

wave as an output using ARM processor.
 Algorithm:-
 For LED Interfacing:-
 Make the port connected to LED high i.e. send a high
signal on the respective port.
 Call Delay.
 Send a low signal on the port to switch off the LED.
 Repeat the steps one to three to blink the LED
continuously i.e. put the steps in a continuous loop.
TO GENERATE SQUARE WAVE
Program to generate square wave using GPIO
#include <LPC210x.H>
delay()
{
int i,j;
for(i = 1;i<= 500;i++)
for(j = 1; j<= 500;j++)
;
}
int main()
{
IODIR = 0x00000700;

while(1)
{
IOCLR = 0x00000700;
delay(); //delay
IOSET = 0x00000700;
delay(); //delay
}
}
 LPC2148 T IME R & C OUNTER

 LPC2148 has two 32-bittimers/counters:Timer0/Counter0 &

Timer1/Counter1.

 LPC2148 Timer has input of peripheral clock (PCLK) or an

external clock. It counts the clock from either of these clock
sources for its operation.

 LPC2148 Timer/Counter can generate an interrupt signal at

specified time value.

 LPC2148 has match registers that contain count value which is

continuously compared with the value of the Timer register.
When the value in the Timer register matches the value in the
match register, specific action (timer reset, or timer stop, or
generate an interrupt) is taken.
LPC2148 T IME R & C OUNTER
 T IMER COUNTER C ONTROL
REGISTER

 Timer count register (TOTC):

 Timer control register(TOTCR)

 Match register(MR0-MR3)

 Match Control Register (TOMCR)

I MPORTANT SFR S OF T IMER
 T IMER COUNT REGISTER

 Timer count register (TOTC):

 32 bit register,which gives range of counting from

0 to 0xFFFF FFFF. Then wraps back to the value
0x0000 0000. This register is incremented on
every tick of clock(PCLK) if prescale count is
made 0.
T IMER COUNTER C ONTROL
REGISTER
 M ATCH REGISTER (MRO TO MR 3)

 There are four 32 bit match registers available MR0 to

MR3

 For the operations of timer ,one of the match

registers may be sufficient and used by loading
number into it

 During operation ,the timer count register starts

incrementing, and at the same time,its count matches
with the number in the match register

 When this match occurs some action can be done by

configuring the bits of match control register
M ATCH CONTROL REGISTER
T IMER O PERATION
T IMER FOR GENERATING A
SYMMETRIC SQUARE WAVE
T IMER FOR GENERATING A
SYMMETIC SQUAREWAVE
 Q UESTION B ANK

1. Explain the Timer unit of ARM

2. Explain the functions of following registers with respect to LPC 2148

a) Timer count register (TOTC):
b) Timer control register(TOTCR)
c) Match register(MR0-MR3)
d) Match Control Register (TOMCR)
e) IODIR
f) IOSET
g) IOPIN
h) IOCLR

3. Explain GPIO of ARM

4. Mention the contents of PINSEL0 register for activating PWM1,PWM2,PWM3

OUTPUTS, which are at pins P0.1,P0.1,P0.6
 Q UESTION B ANK

1. Design a microprocessor based system to

interface ARM7 with seven segment display and
WAP to display 0 to 9 numbers

2. Design a microprocessor based system to

interface ARM7 with 2LEDs and WAP to blink it
alternately. Write delay programme using timer
of ARm