CRC CN
CRC CN
➢ Cyclic codes are special linear block codes with one extra property.
➢ In a cyclic code, if a code word is cyclically shifted (rotated), the result is another code word.
➢ For example, if 1011000 is a code word and we cyclically left-shift, then 0110001 is also a
code word.
➢ In this case, if we call the bits in the first word ao to a6' and the bits in the second word bo to
b6, we can shift the bits by using the following:
In the rightmost equation, the last bit of the first word is wrapped around and becomes the first bit of
the second word.
Cyclic Redundancy Check
We can create cyclic codes to correct errors. In this section, we simply discuss a category of cyclic
codes called the cyclic redundancy check (CRC) that is used in networks such as LANs and WANs.
➢ CRC is based on binary division.
➢ In CRC, a sequence of redundant bits, called cyclic redundancy check bits, are appended to the
end of data unit so that the resulting data unit becomes exactly divisible by a second,
predetermined binary number.
➢ At the destination, the incoming data unit is divided by the same number. If at this step there is no
remainder, the data unit is assumed to be correct and is therefore accepted.
➢ A remainder indicates that the data unit has been damaged in transit and therefore must be
rejected.
➢ Table below shows an example of a CRC code. We can see both the linear and cyclic properties
of this code
➢ In the encoder, the data word has k bits (4 here);
➢ The code word has n bits (7 here).
➢ The size of the data word is augmented by adding n - k (3 here) Os to the right-hand side of
the word.
➢ The n-bit result is fed into the generator.
➢ The generator uses a divisor of size n - k + I (4 here), predefined and agreed upon.
➢ The generator divides the augmented data word by the divisor (modulo-2 division).
➢ The quotient of the division is discarded; the remainder (r2rl ro) is appended to the data word
to create the code word.
➢ The decoder receives the possibly corrupted code word. A copy of all n bits is fed to the
checker which is a replica of the generator.
➢ The remainder produced by the checker is a syndrome of n - k (3 here) bits, which is fed to
the decision logic analyser.
➢ The analyser has a simple function. If the syndrome bits are all as, the 4 leftmost bits of the
code word are accepted as the data word (interpreted as no error); otherwise, the 4 bits are
discarded (error).
➢ The encoder takes the data word and augments it with n - k number of as. It then divides the
augmented data word by the divisor, as shown in Figure below.
➢ The process of modulo-2 binary division is the same as the familiar division process we use for
decimal numbers.
➢ We use the XOR operation to do both addition and subtraction.
➢ As in decimal division, the process is done step by step. In each step, a copy of the divisor is
XORed with the 4 bits of the dividend.
➢ The result of the XOR operation (remainder) is 3 bits (in this case), which is used for the next
step after 1 extra bit is pulled down to make it 4 bits long.
➢ If the leftmost bit of the dividend (or the part used in each step) is 0, the step cannot use the
regular divisor; we need to use an all-Os divisor.
➢ When there are no bits left to pull down, we have a result.
➢ The 3-bit remainder forms the check bits (r2' rl' and ro). They are appended to the data word to
create the code word
Decoder
➢ The code word can change during transmission.
➢ The decoder does the same division process as the encoder.
➢ The remainder of the division is the syndrome.
➢ If the syndrome is all Os, there is no error; the data word is separated from the received code
word and accepted.
➢ Otherwise, everything is discarded. Figure 10.16 shows two cases:
➢ The left hand figure shows the value of syndrome when no error has occurred; the syndrome is
000.
➢ The right-hand part of the figure shows the case in which there is one single error. The syndrome
is not all Os (it is OIl)
Checksum
➢ In checksum error detection scheme, the data is divided into k segments each of m bits.
➢ In the sender’s end the segments are added using 1’s complement arithmetic to get the sum. The
sum is complemented to get the checksum.
➢ The checksum segment is sent along with the data segments.
➢ At the receiver’s end, all received segments are added using 1’s complement arithmetic to get the
sum. The sum is complemented.
➢ If the result is zero, the received data is accepted; otherwise discarded.
Traditionally, the Internet has been using a 16-bit checksum. The sender calculates the checksum by following
these steps
Sender site:
1. The message is divided into 16-bit words.
2. The value of the checksum word is set to O.
3. All words including the checksum are added ushtg one's complement addition.
4. The sum is complemented and becomes the checksum.
5. The checksum is sent with the data