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Verilog_Code_and_Explanation

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12 views

Verilog_Code_and_Explanation

Uploaded by

maathirah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Verilog Code and Detailed Explanation

File: dsd code lab 1a.txt

Module: part1_1a

Purpose: Implements an 8-bit 2-to-1 multiplexer.

Inputs: s (selection input), x and y (8-bit data inputs).

Output: m (8-bit output based on s).

Logic: If s = 0, m is taken from x; if s = 1, m is taken from y.

Verilog Code:

module part1_1a (s, x, y, m);

input s;

input [7:0] x, y;

output [7:0] m;

assign m[0] = (~s & x[0]) | (s & y[0]);

assign m[1] = (~s & x[1]) | (s & y[1]);

assign m[2] = (~s & x[2]) | (s & y[2]);

assign m[3] = (~s & x[3]) | (s & y[3]);

assign m[4] = (~s & x[4]) | (s & y[4]);

assign m[5] = (~s & x[5]) | (s & y[5]);

assign m[6] = (~s & x[6]) | (s & y[6]);

assign m[7] = (~s & x[7]) | (s & y[7]);

endmodule

Module: part2_1a

Purpose: Implements a 5-input multiplexer.

Inputs: u, v, w, x, y (1-bit inputs), s (3-bit selection input).


Output: m (selected 1-bit output).

Verilog Code:

module part2_1a (u, v, w, x, y, s, m);

input u, v, w, x, y;

input [2:0] s;

output m;

wire [4:0] mux;

assign mux[0] = u;

assign mux[1] = v;

assign mux[2] = w;

assign mux[3] = x;

assign mux[4] = y;

assign m = mux[s];

endmodule

File: dsd code lab 1b.txt

Module: part1_1b

Purpose: Implements a 7-segment decoder for a 3-bit input.

Inputs: c (3-bit input representing a number).

Output: s (7-bit output for 7-segment display).

Verilog Code:

module part1_1b (c, s);

input [2:0] c;

output reg [6:0] s;

always @(c) begin


case (c)

3'b000: s = 7'b0001001;

3'b001: s = 7'b1001111;

3'b010: s = 7'b0010010;

3'b011: s = 7'b0000110;

3'b100: s = 7'b1001100;

3'b101: s = 7'b0100100;

3'b110: s = 7'b0100000;

3'b111: s = 7'b0001111;

default: s = 7'b1111111;

endcase

end

endmodule

Module: part2_1b

Purpose: Implements a 6-input multiplexer.

Inputs: a, b, c, d, e, f (1-bit inputs), s (3-bit selection input).

Output: m (selected 1-bit output).

Verilog Code:

module part2_1b (a, b, c, d, e, f, s, m);

input a, b, c, d, e, f;

input [2:0] s;

output m;

wire [5:0] mux;

assign mux[0] = a;

assign mux[1] = b;
assign mux[2] = c;

assign mux[3] = d;

assign mux[4] = e;

assign mux[5] = f;

assign m = mux[s];

endmodule

File: lab2a dsd code.txt

Module: part1

Purpose: Main module that integrates components for 7-segment display output.

Inputs: v (4-bit binary input), b (4-bit input for comparison).

Outputs: d1 (tens digit), d0 (units digit).

Verilog Code:

module part1 (v, b, d0, d1);

input [3:0] v, b;

output [6:0] d1, d0;

wire z;

wire [2:0] CAout;

wire [3:0] m;

comparator call (v, b, z);

genericmux call (z, v[3], 1'b0, m[3]);

circuitA callA (v[2:0], CAout[2:0]);

circuitB callB (z, d1);

genericmux mux2 (z, v[2], CAout[2], m[2]);

genericmux mux1 (z, v[1], CAout[1], m[1]);

genericmux mux0 (z, v[0], CAout[0], m[0]);


d0 calld0 (m, d0);

endmodule

File: lab2b dsd code.txt

Module: lab2bmain

Purpose: Main module for arithmetic operations and 7-segment display.

Inputs: A0-A3, B0-B3 (4-bit inputs), cin (carry-in).

Outputs: disp1, disp0 (7-segment display outputs).

Verilog Code:

module lab2bmain (A0, B0, A1, B1, A2, B2, A3, B3, cin, disp1, disp0);

parameter Bcomp = 4'b1001;

input A0, A1, A2, A3, B0, B1, B2, B3;

input cin;

wire [3:0] s;

wire cout1, cout2, cout3, cout4;

wire [3:0] M, Aout;

wire z, compOUTFLOW;

output [6:0] disp1, disp0;

lab2b_adder call0(A0, B0, cin, cout1, s[0]);

lab2b_adder call1(A1, B1, cout1, cout2, s[1]);

lab2b_adder call2(A2, B2, cout2, cout3, s[2]);

lab2b_adder call3(A3, B3, cout3, cout4, s[3]);

comparator callc (s, Bcomp, compOUTFLOW);

circuitA callA (s, cout4, Aout);

Zeddo zetton (compOUTFLOW, cout4, z);

genericmux mux3(z, s[3], Aout[3], M[3]);


genericmux mux2(z, s[2], Aout[2], M[2]);

genericmux mux1(z, s[1], Aout[1], M[1]);

genericmux mux0(z, s[0], Aout[0], M[0]);

circuitB displayONE(z, disp1);

d0 displayRANGE (M, disp0);

endmodule

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