Scribd
Upload
12 views4 pages

Combinational Logic Circuits Verilog

Uploaded by

maathirah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
12 views4 pages

Combinational Logic Circuits Verilog

Uploaded by

maathirah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Combinational Logic Circuits in Verilog

1. Combinational Logic Circuits Overview

Combinational circuits use logic gates to perform operations such as addition, comparison, and selection.

The output depends only on the current input values. Examples include multiplexers, decoders, adders, and simple

logical functions.

2. Simple Logic Gate Implementation

Example: AND, OR, and NOT Gates in Verilog:

module simple_gates (a, b, c, d, e);

input a, b;

output c, d, e;

assign c = a & b; // AND gate

assign d = a | b; // OR gate

assign e = ~a; // NOT gate

endmodule

Explanation: The 'assign' statement is used for continuous assignment to create simple gates.

3. Multiplexer (MUX)

A MUX selects one of several input signals based on select lines and forwards it to the output.

Example: 4-to-1 Multiplexer in Verilog:

module mux4to1 (w0, w1, w2, w3, s, f);

input w0, w1, w2, w3;

input [1:0] s; // 2-bit select input

output reg f;

always @(*) begin


case (s)

2'b00: f = w0;

2'b01: f = w1;

2'b10: f = w2;

2'b11: f = w3;

default: f = 0;

endcase

end

endmodule

Explanation: The 'case' statement selects the input based on the value of 's'.

4. Decoder

A decoder activates one output line based on a binary input.

Example: 2-to-4 Decoder in Verilog:

module decoder_2to4 (w1, w0, en, y0, y1, y2, y3);

input w1, w0, en;

output reg y0, y1, y2, y3;

always @(*) begin

if (en) begin

case ({w1, w0})

2'b00: {y0, y1, y2, y3} = 4'b1000;

2'b01: {y0, y1, y2, y3} = 4'b0100;

2'b10: {y0, y1, y2, y3} = 4'b0010;

2'b11: {y0, y1, y2, y3} = 4'b0001;

default: {y0, y1, y2, y3} = 4'b0000;

endcase
end else

{y0, y1, y2, y3} = 4'b0000;

end

endmodule

Explanation: The 'case' statement decodes the input and activates the corresponding output.

5. Full Adder

A full adder adds two single-bit numbers and a carry-in, producing a sum and a carry-out.

Verilog Code:

module full_adder (a, b, cin, sum, cout);

input a, b, cin;

output sum, cout;

assign sum = a ^ b ^ cin; // XOR for sum

assign cout = (a & b) | (b & cin) | (a & cin); // Carry-out

endmodule

Explanation: The full adder uses 'assign' statements to compute the sum and carry-out.

6. Priority Encoder

A priority encoder outputs the binary representation of the highest-priority active input.

Example: 4-to-2 Priority Encoder in Verilog:

module priority_encoder (in, out, valid);

input [3:0] in;

output reg [1:0] out;

output reg valid;

always @(*) begin

valid = 1;
casez (in) // 'z' allows don't-care conditions

4'b1???: out = 2'b11; // Highest priority

4'b01??: out = 2'b10;

4'b001?: out = 2'b01;

4'b0001: out = 2'b00; // Lowest priority

default: begin

out = 2'b00;

valid = 0; // No valid input

end

endcase

end

endmodule

Explanation: The 'casez' statement handles priority encoding, with '?' as a wildcard.

You might also like