Digital Electronics

Unit wise Questions Bank

UNIT- 1

1. Explain various number systems and codes and their conversion with examples for each.
2. Convert the following:
i) (AB)16 = ( )10
ii) (1234)8= ( )10
iii) (10110011)2=( )10
iv) (772)10= ( )16
v) (0.513)10=( )8
3. Find the value of X in the following numbers

i) (ACDF.BDE) 16 = (X)2

ii) (235.0657)8 = (X)10

iii) (101010011)2 = X in gray code

4. Convert (0011001.0101)2 to decimal and octal.

5. Convert the following to Decimal and then to Binary.
i) (3214)16 ii) (2716)8
6. Express the following numbers in decimal:
(10110.0101)2, (16.5)16, (26.24)8.
7. Given 2 binary numbers X=1010100(2) and Y=1000011(2). Perform 2’s complement subtraction
for: i) X-Y ii) Y-X
8. Simplify the following expressions
a) XY + XYZ + XYZ’ + X’YZ b) AB + A’+C’+AB’C (AB+C) c) {(bc’+a’d) (ab’+ cd’)}’
9. Explain about all logic gates.
10. Realize all gates Using Universal (NAND and NOR) Gates.
11. Simplify the following Boolean Function using K-map & draw its equivalent NAND
representation
F(w,x,y,z) = ∑m(0,7,8,9,10,12)+ ∑d(2,5,13)
12. Explain & Prove De Morgan’s Theorem.
13. Simplify the following Boolean Function using K-map
F(P, Q,R,S) = πM (0,3,4,7,8,10,12,14) + ∑d(2,6)
14. Write the Properties/Laws of Boolean algebra?
15. State and prove Conesus theorem.
16. Demonstrate by means of truth tables the Boolean Associative law and distributive law. Simplify
the Boolean expression to minimum number of literals: (A+B)' (A'+B').
17. Simplify the following three variable expression using Boolean algebra and implement using
NAND gates.
f(A, B,C) = ABC+A’B’C+A’BC+ABC’+A’B’C’
18. Simplify the following Boolean expressions to a minimum number of literals:
i) ABC+A'B+ABC'
ii) (ii) xy + x(wz+wz')
19. a) Express the following function in standard SOP form:
F(A,B, C,D) = B'D + A'D + BD

b) Express the following function in standard POS form:

F(A,B, C,D) = (A+C) (B+D') (C+D)

20. Obtain a 3-bit and 4-bit Gray code from a 2-bit Gray code by reflection

UNIT -2
1. Simplify the function F (A, B, C, D) = Σ (0, 1, 3, 4, 6, 8, 15) using K-Map.
2. Solve the following function using K-MAP A=f(w, x, y, z)=π(1,2,3,4,8,9,10,11,12,13,14,15) and
implement it using NOR gates only.
3. Simplify the following Boolean expression
F(A, B,C,D)= ∑m(1,3,5,7,8,12,13), ∑d(2,4,9) using k-map
4. Find F in POS form for F (A, B, C, D) = Π (1, 3, 7, 11, 15) + d (0, 2, 5).
5. Express the following function in standard SOP form:
F(A,B, C,D) = B'D + A'D + BD

6. Design a full adder and implement it using multiplexer.

7. Simplify the following Boolean functions, using a four variable Karnaugh map method and
implement the simplified function using NAND gates. F(A, B,C,D) = ∑0,2,4,5,6,7,8,10,13,15)
8. Show that the dual of the exclusive OR is also its compliment.
9. Draw the multiple level NAND circuit for the following expression:
(AB'+CD’) E + BC(A+B)
10. Solve the following function using K-MAP and implement it by using NAND gates
f(w,x,y,z)=∑(1,2,34,9)+∑d(10,11,12,13,14,15)
11. Simplify the following Boolean function together with don’t care conditions d, F(A,B,C,D) =
∑m(0,6,8,13,14) + ∑d(2,4,10)

UNIT -3
12. Design a 4-bit adder-subtractor and explain its operation.
13. Design half adder using only NAND gates.
14. Explain the operation of 3 x 8 decoder with a neat diagram.
15. Realize a full adder using 2 half adders and explain the truth table.
16. Realize a full subtractor using decoders
17. Design 2-bit and 4-bit comparator using gates.
18. Explain the differences between a MUX and a DEMUX.
19. Design the 16X1 multiplexer with a dual a 2 line to 1-line multiplexer and explain its
working
20. Design BCD to Gray code convertor and draw the logic Diagram.
21. Realize the function f(A, B,C,D) = ∏(1,4,6,10,14) + d (0,8,11,15) using (i) 16:1 MUX (ii) 8:1
MUX.
22. Realize the expression F=Σm(0,1,3,5,8,11,12,14,15)using 8×1 MUX.
23. Design a 3 to 8 decoder using 2 to 4 decoders.
24. Explain how a decoder can be converted into a demultiplexer with relevant block diagram tables.
25. Implement the following Boolean function using 4:1 MUX F(A, B,C,D)=∑m(0,1,2,4,6,9,12,14)
26. What is a combinational logic circuit? Implement a Full adder using two half adders and one OR
gate.
27. With a neat diagram explain in detail about Decimal Adder.
28. explain briefly about priority encoder?
29. Implement Full Adder using Decoder.
30. Implement the following Boolean function using 3-to-8-line decoder
F1=∑m(0,1,2,6)
F2=∑m(2,4,6)
F3=∑m(0,1,5,6)
31. With the help of Logic Diagram and truth table explain an Octal to Binary Priority Encoder

UNIT -4
1. What is the difference between edge triggering and level triggering? Explain about edge
triggered D flip-flop with a neat diagram.
2. compare combinational and sequential circuits.
3. Draw the schematic circuit of J-K flip-flop and explain its operation with the help of truth
Table.
4. characteristic equation for all Flip Flops and truth tables and excitation tables of all flipflops
5. All flipflop conversions.
6. Design 4-bit Asynchronous counter using J-K flip flops with its timing diagram L3 5
7. What is a register? Explain in detail different types of Shift registers
8. Design a Modulo-7 synchronous counter using J K Flip-Flop. Draw its state diagram and
Timing Waveforms.
9. Draw the circuit diagram of 8-bit Johnson counter using D-flip flop and explain its operation
with the help of bit pattern.
10. Design a mod-5 synchronous counter using JK flip flops. Write excitation table and state table.
11. Implement a 3-bit down counter using D flip flop.
12. Design 4-bit SISO shift register using D flip-flops.
13. Discuss the applications of shift registers.
14. With a neat diagram explain about 4-bit bidirectional shift register
15. Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6, use JK flip-
flops
16. Design a 4-bit synchronous counter with D flip - flops and explain its working.
17. Derive the Characteristic equation for listed flip-flops: a) SR F/F b) JK F/F c) T F/F d) D F/F
18. Design a modulus Synchronous counter for the sequence using D Flip flop.

19. compare synchronous and ripple counters.

20. Design SR flip-flop using NOR gates and NAND gates.
21. What is race around condition, Explain the operation JK master slave flip flop. Explain its truth
table
22. Design, draw and explain a 4-bit ring counter and Johnson ring counter using D- flip flops with
relevant timing diagrams.
23. Design a MOD-10 ripple counter.
24. Design and construct MOD-5 synchronous counter using JK flip flops.
25. What is State Assignment. Explain with suitable example.
 UNIT -5

1. What are the draw backs of PLAs? How PLAs are used to implement combinational and
sequential logic circuits?
2. A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from memory.
What is the original 8-bit word if the 12-bit read out is 1010 1001 1101.
3. A combinational circuit is defined by the functions: F1= ∑m(3, 5, 7), F2 = ∑m(4, 5,7)
Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs.
4. Decode the following message assuming that at most a single bit error occurred in each code
word when it is transmitted through a noisy channel using 7-bit Hamming code. 1110111,
0011011, 1101101.
5. Design a 3×8 decoder and implement using a suitable PLA.
6. The 8-bit data word 01011011, generate the 12-bit composite word for the hamming code that
corrects and detects single errors.
7. Describe DRAM with an appropriate diagram and explain its timings.
8. Implement the following Boolean functions using PROM
F1 (A, B, C) = ∑m (0, 1, 2, 4), & F2 (A, B, C) = ∑m (0, 5, 6, 7)
9. Draw a PLA circuit to implement the functions.
F1 = A′B + AC′ + A′BC′ F2 = (AC + AB + BC)’
10. Design a combinational logic circuit using a ROM that accepts a 3-bit binary number and
generates an output binary equal to the square of the input number
11. Explain semiconductor memories
12. Given the 8‐bit data word 01011011, generate the 13‐bit composite word for the Hamming code
that corrects single errors.
13. Design an BCD to Excess-3 code converter using PROM
14. Compare all PLDs
15. Explain memory decoding in RAM
16. Design a combinational circuit to convert bcd to excess3 and implement using PROM
17. What is a hazard? How do you eliminate hazards?
18. For the state table shown below, minimize the state table and draw the minimized state diagram

N. S OUTPUT
P. S
x=0 x=1 x=0 x=1
 a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
19. For the state table shown below, minimize the state table and draw the minimized state diagram

N. S OUTPUT
P. S
x=0 x=1 x=0 x=1
a a b 0 0
b c b 0 1
c d a 1 1
d d a 1 1
20. For the machine given below find the equivalence partition and a corresponding reduced
machine in standard form and also explain the procedure