B.Sc.

, COMPUTER SCIENCE
MICROPROCESSOR AND ITS APPLICATIONS
SECOND YEAR NON – SEMESTER
Dr.A.SHAIK ABDUL KHADIR
HOD & Associate Professor
Dept of Computer Science,
Khadir Mohideen College,
Adirampattinam, Thanjavur - 614 701.

July-2020 (New Print)

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 MICROPROCESSOR AND ITS APPLICATIONS

Unit I

Evaluation of Microprocessors – Single Chip Microcomputer Microprocessor Applications –

Programming Digital Computers – Memory – Buses – Memory addressing capacity and CPU –
Microcomputers – Processor Architecture – Intel 8085 – Instruction Cycle – Timing diagram.
Unit II
Instruction set of Intel 8085 – Instruction and Data Formats – Addressing Modes – Status flags –
Intel 8085 Instructions – Programming of Microprocessors – Assembly language – Assemblers –
Stacks and Subroutines – MACRO – Microprogramming.
Unit III
Assembly language Programming – Simple examples – Addition and Subtraction of Binary and
Decimal Numbers – Complements – Shift – Masking – Finding the largest and smallest numbers
in an Array – Arranging a series of numbers – Sum of a series of Numbers – Multiplication –
Division – Multibyte Addition and Subtraction.
Unit IV
Peripheral Devices and Interfacing – Address Space Partitioning – Memory and I/O Interfacing –
Data transfer schemes – Interrupts of Intel 8085 – Interfacing memory and I/O devices – I/O
ports – Programmable peripheral Interface – Programmable Counter / Interval Timer – A/D
Converter and D/A Converter.
Unit V
Microprocessor Applications – Delay Subroutines – Interfacing of 7 Segment Displays –
Frequency measurement – Temperature measurement and Control – Water Level Indicator –
Microprocessor based Traffic Control.
Text Book:
1.Fundamentals of Microprocessors and Microcomputers – Badri Ram – Fourth Revised and
Enlarged Edition – Dhanpat Rai and Sons – 1993.
Reference Book:
1.Microprocessor Architecture, Programming and Applications with the 8085 / 8080A – Romesh
S.Gaonkar – Wiley Eastern – 1990
 UNIT-I MICROPROCESSOR ARCHITECTURE
1.1. Introduction
A CPU built into a single chip LSI or VLSI chip is called a microprocessor.
The term LSI refers to ICs containing components usually transistors in the
range of 1000-10,000. A VLSI chip contains more than 10,000 transistors. A
digital computer whose CPU is a microprocessor is called a microcomputer.

1.2. Evolution of Microprocessors

9 The first Microprocessor was introduced in 1971 by Intel Corporation. This was
the Intel 4004, a processor on a single chip. It had the capability of performing
simple arithmetic and logical operations. For example, addition, subtraction,
comparison, logical AND and OR operations. It also had a control unit which
could perform various control functions like fetching an instruction from the
memory, decoding it and generating control signals to execute it.
9 It was a 4 bit Microprocessor operating on 4 bits of data at a time.
9 The processor was the central component in the chip set, which was called the
MCS-4. The other components in the set were a 4001 ROM, 4002 ROM and a
4003 shift register.
9 Shortly after the 4004 appeared in the commercial market place, three other
general purpose microprocessors were introduced. These devices were the
Rockwell International 4-bit PPS-4, the Intel
8-bit 8008 and the National Semiconductor 16-bit IMP-16. Other
companies had also contributed in the development of Micropro
cessor.
9 The first 8 bit Microprocessor, which would perform arithmetic and logic
operations on 8 bit words, was introduced in 1973, by Intel. This was 8008 that
was followed by an improved version- the 8080 from the same company. The
microprocessors introduced between 1971and 1972 were the first generation
systems. They were designed using the PMOS technology. This technology
provided low cost, slow speed and low output currents and was compatible with
TTL.
9 After 1973, the second generation microprocessors such as Motorola 6800 and
6809, Intel 8085 and Zilog Z80 evolved. These microprocessors were fabricated
using NMOS technology. The NMOS process offered faster speed and higher
density than PMOS and was TTL compatible. The distinction between the 1st &
2nd generation devices was primarily the use of new a semiconductor technology
to fabricate the chips. This new technology resulted in a significant increase in
instruction execution speed & higher chip densities.

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 9 After 1978, the 3rd generation microprocessors were introduced.
Typical microprocessors were Intel 8086/ 80186/ 80286 and Motorola 68000/
68010. These microprocessors were designed using HMOS technology.

1.3. Single Chip Microcomputers

Putting a CPU, ROM, RAM, and data input/output circuitry into a single IC will make
a single-chip microprocessor. ... Single-chip microprocessors are also known as
"microcomputer units (MCUs)," because they are made of a single IC. Single-chip
computers are mainly of the form known as Microcontroller chips and used in embedded
devices.

1.4. Microprocessor Applications

A microprocessor makes daily life easier because of its low cost, low power, small
weight, and vast application in every field. There are several applications of
microprocessors. Some of the important applications are:
House hold Devices.
9 The programmable thermostat allows the control of temperature at homes.
In this system, a microprocessor works with the temperature sensor to
determine and adjust the temperature accordingly.
9 High-end coffee makers, Washing machines, and radio clocks contain
microprocessor technology.

Industrial Applications of Microprocessors

9 Some industrial items which use microprocessors technology include:

cars, boats, planes, trucks, heavy machinery, elevators, gasoline pumps,
credit-card processing units, traffic control devices, computer servers,
most high tech medical devices, surveillance systems, security systems,
and even some doors with automatic entry.

Transportation Industry

9 Automobiles, trains and planes also use microprocessor technology.

9 Consumer vehicles-buses, cars, trucks -integrate microprocessors to
communicate important information throughout the vehicle. E.g.,
navigation systems provide information using microprocessors and
global positioning system (GPS) technology.

Computers and Electronics

9 Microprocessor-drives technology is the brain of the computer. They
are used in all type of computers ranging from microcomputers to
supercomputers.

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 9 A cell phone or mobile device executes game instructions by way of
the microprocessor.
9 VCRs, televisions and gaming platforms also contain microprocessors
for executing complex instructions and tasks.

Instrumentation

9 Microprocessor is also very useful in the field of instrumentation.

Function generators, frequency counters, frequency synthesizers,
spectrum analyses and many other instruments are available, when
microprocessors are used as controller.

Entertainment

9 The use of microprocessor in entertainment equipment, toys and home

entertaining applications is making them more useful and full of
features.

1.5. Programming
9 To perform a particular task the programmer prepares a set of instructions known
as a program. A program written in the form of zeros and ones is called a machine
language program. The writing of a program in the machine language is difficult.
The simplest symbolic language used for microprocessor is assembly language.
9 Translators are used for the conversion of an assembly language or high level
language into Machine language for the operation of the computer. A program
which converts an assembly language program into a machine language program
is called an assembler. Similarly, a program, which translates a program written in
a high level language into a machine language program is called a compiler.

1.6. Digital Computers

A digital computer is a programmable machine specially designed for making
computation. Its main components are:
i. CPU(Central Processing Unit)
ii. Memory
iii. Input device
iv. Output device

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 1.1. Schematic Diagram of a Digital Computer

The CPU of a microcomputer is a microprocessor. The physical devices and circuitry of a

computer are called hardware. A set of programs written for a particular computer is known as
software for that computer.

1.2. Schematic Diagram of a Microcomputer

1.6.1 CPU

The Central Processing Unit fetches instructions from the memory and performs specified
tasks. It stores results in the memory or sends results to the output devices. The CPU of a large
computer is implemented on one or more circuit boards. ICs are used as its components. The
major sections of a CPU are:

i. ALU (Arithmetic and Logic Unit). The function of an ALU is to perform arithmetic
operations such as addition and subtraction.

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 ii. Timing and Control Unit. This unit controls the entire operations of a computer.
iii. Accumulator and General Purpose Registers. The accumulator is a register which
contains one of the operands and stores results of most arithmetic and logical operations.
General purpose registers are used for temporary storage of data.

1.3. Schematic Diagram of a CPU or microprocessor

1.6.2. Microprocessor

A CPU built into a single chip LSI or VLSI chip is called a microprocessor. A digital
computer using microprocessor as its CPU is called a microcomputer.

1.6.3. Memory

The memory is storage device. It stores program, data, results etc.

1.6.4. Input Device

An input device is a hardware or peripheral device used to send data to a computer. An

input device allows users to communicate and feed instructions and data to computers for
processing, display, storage and/or transmission.

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1.6.5. Output Device

The computer sends results to output devices. An output device may store, print, display or
send electrical signal to control certain equipment. The example of simple output devices are
printers, CRT, LEDs, controllers etc.

1.7. Memory
9 A memory is just like a human brain. It is used to store data and instructions.
Computer memory is the storage space in the computer, where data is to be
processed and instructions required for processing are stored.
9 The memory is divided into large number of small parts called cells. Each
location or cell has a unique address, which varies from zero to memory size
minus one. For example, if the computer has 64k words, then this memory unit
has 64 * 1024 = 65536 memory locations. The address of these locations varies
from 0 to 65535. There are two kinds of memories:
i. Semiconductor memories
ii. Magnetic memories

1.7.1. Semiconductor memories

Semiconductor memories are faster, smaller, lighter and consume less power.
Semiconductor memories are used as the main memory of a computer. There are two
important types of semiconductor memories:
i. RAM (Random Access Memory)
ii. ROM(Read Only Memory)

1.7.1.1. RAM
9 RAM is a form of short term or volatile memory. Information stored in short
term storage is lost when the computer is switched of (or when power fails).
9 This means that any location in memory may be accessed in the same amount
of time as any other location. Memory access means one of two things, either
the CPU is reading from a memory location or the CPU is writing to a
memory location.
9 When the CPU reads from a memory location, the contents of the memory
location are copied to a CPU register. When the CPU writes to a memory
location, the CPU copies the contents of a CPU register to the memory
location, overwriting the previous contents of the location. RAM is of two
types:
i. Static RAM
ii. Dynamic RAM

Static RAM(SRAM). The word static indicates that the memory retains its contents as
long as power is being supplied. However, data is lost when the power gets down due to volatile

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nature. SRAM need not have to be refreshed on a regular basis in order to maintain the data
.SRAM is used as cache memory and has very fast access.

Characteristic of the Static RAM .

• It has long life

• There is no need to refresh

• Faster

• Used as cache memory

Dynamic RAM(DRAM). DRAM, unlike SRAM, must be continually refreshed

(recharged)in order to maintain the data. This is done by placing the memory on a refresh circuit
that rewrites the data several hundred times per second. DRAM is used for most system memory
because it is cheap and small.

Characteristics of the Dynamic RAM

• It has short data lifetime

• Need to be refreshed continuously

• Slower as compared to SRAM

• Used as RAM

1.7.1.2 ROM READ ONLY MEMORY (ROM) ROM stands for Read Only Memory. The
memory from which we can only read but cannot write on it. This type of memory is non-
volatile. The information is stored permanently in such memories during manufacture. A ROM,
stores such instructions that are required to start a computer.

Following are the various types of ROM,

PROM . (Programmable Read only Memory) PROM is read-only memory that can be
modified only once by a user. It can be programmed only once and is not erasable.

EPROM. (Erasable and Programmable Read Only Memory) The EPROM can be erased
by exposing it to ultra-violet light for a duration of up to 40 minutes.

EEPROM. (Electrically Erasable and Programmable Read Only Memory) The EEPROM is
programmed and erased electrically. It can be erased and reprogrammed about ten thousand
times.

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1.7.2. Magnetic memories
9 Magnetic memories are non-volatile. They are slower than semiconductor
memories. They are used in computer system for bulk storage. The important
types of magnetic memories are: magnetic tape, floppy disk, hard disk and
magnetic bubble type memories.
9 It was used as a main memory in earlier computers. Today semiconductor
memories have replaced core memories. Magnetic tapes, floppy disks are used as
mass storage devices.

Magnetic Tape Storage. Magnetic tape is a medium for magnetic recording, made of a
thin, magnetizable coating on a long, narrow strip of plastic film. A device that stores computer
data on magnetic tape is known as a tape drive. Magnetic tape revolutionized sound recording
and reproduction and broadcasting.

Magnetic tape recording works by converting electrical audio signals into magnetic
energy, which imprints a record of the signal onto a moving tape covered in magnetic particles.
As the tape passes by, these pulses align the tiny magnetic particles into patterns, leaving a
record of the sound.

Floppy Disk. A floppy disk is a magnetic storage medium for computer systems. The
floppy disk is composed of a thin, flexible magnetic disk sealed in a square plastic carrier. In
order to read and write data from a floppy disk, a computer system must have a floppy disk drive
(FDD). A floppy disk is also referred to simply as a floppy. Since the early days of personal
computing, floppy disks were widely used to distribute software, transfer files, and create back-
up copies of data. When hard drives were still very expensive, floppy disks were also used to
store the operating system of a computer.

Optical Disk. An optical disc is an electronic data storage medium that can be written to
and read from using a low-powered laser beam. Originally developed in the late 1960s, the first
optical disc, created by James T. Russell, stored data as micron-wide dots of light and dark.

Optical storage, electronic storage medium that uses low-power laser beams to record and
retrieve digital (binary) data. In optical-storage technology, a laser beam encodes digital data
onto an optical, or laser, disk in the form of tiny pits arranged in concentric tracks on the disk's
surface.

1.8. BUSES
Various input/output devices and memories are connected to the CPU by a group of
lines called a bus. There are three types of buses: address bus, data bus and control bus.
9 The data bus allows data to travel back and forth between the microprocessor
(CPU) and memory (RAM).
9 The address bus carries information about the location of data in memory.

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 9 The control bus carries the control signals that make sure everything is flowing
smoothly from place to place.

1.4. Bus structure

1.9. Memory Addressing Capacity of CPU

The memory addressing capacity of a CPU depends on the width of its address bus. If
a CPU has n-bit wide address bus, it can directly address 2n memory locations. For
example, a CPU having a 16-bit wide address bus can directly address up to 216= 64K
memory locations. One memory location stores 1 byte of information. Therefore, a CPU
having a 16-bit wide can directly access 64K bytes of memory.

1.10. Microcomputers

Low-cost small digital computers are known as microcomputers. The word length of a
microcomputer may be 8-bit, 16-bit or 32-bit. Microcomputers are widely used in industrial
control, instrumentation, general purpose computation, home appliances, commercial appliances,
office automation, automobiles, and so on and so forth.

1.11. Microprocessor Architecture

The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5 V
for power. It can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and address
bus width is 16-bit, thus it can address 216 = 64 KB of memory.

The internal architecture of 8085 is shown below.

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 1.5. Architecture of 8085 Microprocessor

Arithmetic and Logic Unit . The ALU performs the actual numerical and logical
operations such as Addition (ADD), Subtraction (SUB), AND, OR etc. It uses data from
memory and from Accumulator to perform operations. The results of the arithmetic and
logical operations are stored in the accumulator.

Registers. The 8085 includes six registers, one accumulator and one flag register, as
shown in Fig. 3. In addition, it has two 16-bit registers: stack pointer and program
counter. They are briefly described as follows.

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The 8085 has six general-purpose registers to store 8-bit data; these are identified as B, C,
D, E, H and L. they can be combined as register pairs - BC, DE and HL to perform some
16-bit operations. The programmer can use these registers to store or copy data into the
register by using data copy instructions.

Accumulator. The accumulator is an 8-bit register that is a part of ALU. This register is
used to store 8-bit data and to perform arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.

Flag register. The ALU includes five flip-flops, which are set or reset after an operation
according to data condition of the result in the accumulator and other registers. They are
called Zero (Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags.
For example, after an addition of two numbers, if the result in the accumulator is larger
than 8-bit, the flip-flop uses to indicate a carry by setting CY flag to 1. When an
arithmetic operation results in zero, Z flag is set to 1. The S flag is just a copy of the bit
D7 of the accumulator. A negative number has a 1 in bit D7 and a positive number has a
0 in 2’s
Complement representation. The AC flag is set to 1, when a carry result from bit D3 and
passes to bit D4. The P flag is set to 1, when the result in accumulator contains even
number of 1s.

Program Counter (PC). This 16-bit register deals with sequencing the execution of
instructions. This register is a memory pointer. The microprocessor uses this register to
sequence the execution of the instructions. The function of the program counter is to
point to the memory address from which the next byte is to be fetched. When a byte is
being fetched, the program counter is automatically incremented by one to point to the
next memory location.

Stack Pointer (SP). The stack pointer is also a 16-bit register, used as a memory pointer.
It points to a memory location in R/W memory, called stack. The beginning of the stack
is defined by loading 16-bit address in the stack pointer.

Instruction Register/Decoder. It is an 8-bit register that temporarily stores the current

instruction of a program. Latest instruction sent here from memory prior to execution.
Decoder then takes instruction and decodes or interprets the instruction. Decoded
instruction then passed to next stage.

Control Unit. Generates signals on data bus, address bus and control bus within
microprocessor to carry out the instruction, which has been decoded. Typical buses and
their timing are described as follows:

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 9 Data bus carries data in binary form between icroprocessor and other
external units such as memory. It is used to transmit data i.e.
information, results of arithmetic etc. between memory and the
microprocessor. Data bus is bidirectional in nature. The data bus width
of 8085 microprocessor is 8-bit i.e. 28 combination of binary digits and
are typically identified as D0 – D7. Thus size of the data bus determines
what arithmetic can be done. If only 8-bit wide then largest number is
11111111 (255 in decimal). Therefore, larger numbers have to be
broken down into chunks of 255. This slows microprocessor.
9 Address Bus: The address bus carries addresses and is one way bus
from microprocessor to the memory or other devices. 8085
microprocessor contain 16-bit address bus and are generally identified
as A0 - A15. The higher order address lines (A8 – A15) are
unidirectional and the lower order lines (A0 – A7) are multiplexed
(time-shared) with the eight data bits (D0 – D7) and hence, they are
bidirectional.

I. Control Bus: Control bus are various lines which have specific functions for
coordinating and controlling microprocessor operations. The control bus carries control
signals partly unidirectional and partly bidirectional. The following control and status
signals are used by 8085 processor:
II. ALE (output): Address Latch Enable is a pulse that is provided when an address appears
on the AD0 – AD7 lines, after which it becomes 0.
III. RD (active low output): The Read signal indicates that data are being read from the
selected I/O or memory device and that they are available on the data bus.
IV. WR (active low output): The Write signal indicates that data on the data bus are to be
written into a selected memory or I/O location.
V. IO/M(output): It is a signal that distinguished between a memory operation and an I/O
operation. When IO/M= 0 it is a memory operation and IO/M=1 it is an I/O operation.
VI. S1 and S0 (output): These are status signals used to specify the type of operation being
performed.

The microprocessor performs primarily four operations:

I. Memory Read: Reads data (or instruction) from memory.

II. Memory Write: Writes data (or instruction) into memory.

III. I/O Read: Accepts data from input device.

IV. I/O Write: Sends data to output device.

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The 8085 processor performs these functions using address bus, data bus and control bus shown
as below.

1. 6 The 8085 bus structure

1.11.1. 8085 pin description

Properties:
x It is a 8-bit microprocessor
x Manufactured with N-MOS technology
x 40 pin IC package
x It has 16-bit address bus and thus has 216 = 64 KB addressing capability.
x Operate with 3 MHz single-phase clock
x +5 V single power supply
The logic pin layout and signal groups of the 8085 microprocessor are shown in the
following figure.

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 1.7. Pin configuration of 8085

Address Bus and Data Bus:

The address bus is a group of sixteen lines i.e A0-A15. The address bus is unidirectional, i.e.,
bits flow in one direction from the microprocessor unit to the peripheral devices and uses the
high order address bus.

Control and Status Signals:

ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle
and enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.

IO/M’ – It is a status signal which determines whether the address is for input-output or
memory. When it is high(1) the address on the address bus is for input-output devices. When it is
low(0) the address on the address bus is for the memory.

SO, S1 – These are status signals. They distinguish the various types of operations such as halt,
reading, instruction fetching or writing.

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RD’ – It is a signal to control READ operation. When it is low the selected memory or input-
output device is read.

WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is
written into the selected memory or I/O location.

READY – It senses whether a peripheral is ready to transfer data or not. If READY is high(1)
the peripheral is ready. If it is low(0) the microprocessor waits till it goes high. It is useful for
interfacing low speed devices.

Power Supply and Clock Frequency:

Vcc – +5v power supply

Vss – Ground Reference

XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by two,
therefore, to operate a system at 3MHZ the crystal should have frequency of 6MHZ.

CLK (OUT) – This signal can be used as the system clock for other devices.

Interrupts and Peripheral Initiated Signals:

The 8085 has five interrupt signals that can be used to interrupt a program execution.

(i) INTR

(ii) RST 7.5

(iii) RST 6.5

(iv) RST 5.5

(v) TRAP

The microprocessor acknowledges Interrupt Request by INTA’ signal. In addition to Interrupts,

there are three externally initiated signals namely RESET, HOLD and READY. To respond to
HOLD request, it has one signal called HLDA.

INTR – It is an interrupt request signal.

INTA’ – It is an interrupt acknowledgment sent by the microprocessor after INTR is received.

Reset Signals:

RESET IN’ – When the signal on this pin is low(0), the program-counter is set to zero, the buses
are tristated and the microprocessor unit is reset.

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RESET OUT – This signal indicates that the MPU is being reset. The signal can be used to reset
other devices.

DMA Signals:

HOLD – It indicates that another device is requesting the use of the address and data bus.
Having received HOLD request the microprocessor relinquishes the use of the buses as soon as
the current machine cycle is completed. Internal processing may continue. After the removal of
the HOLD signal the processor regains the bus.

HLDA – It is a signal which indicates that the hold request has been received after the removal
of a HOLD request, the HLDA goes low.

Serial I/O Ports:

Serial transmission in 8085 is implemented by the two signals,

SID and SOD – SID is a data line for serial input where as SOD is a data line for serial output.

1.12. Timing Diagram

Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The 8085 microprocessor has 5 basic machine cycles. They are

x Opcode fetch cycle

x Memory read cycle
x Memory write cycle
x I/O read cycle
x I/O write cycle

Timing Diagram for opcode fetch Cycle

x Each instruction of the processor has one byte opcode.

x The opcodes are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory. Hence, every instruction starts with opcode
fetch machine cycle.
x The time taken by the processor to execute the opcode fetch cycle is 4T.
x In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

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 1.8. Timing Diagram for opcode fetch Cycle

Timing Diagram for Memory Read

x The memory read machine cycle is executed by the processor to read a data byte from
memory.
x The processor takes 3T states to execute this cycle.
x The instructions which have more than one byte word size will use the machine cycle
after the opcode fetch machine cycle.

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 1.9. Timing Diagram for Memory Read

Timing Diagram for Memory Write

x In a memory write cycle the CPU sends data from the accumulator or any other
register to the memory. The timing diagram for a memory for a memory write
cycle is shown in the following figure.
x The status signals S0 and S1 are 1 and 0 respectively for write operation. WR
goes low in T2 indicating that the write operation is to be performed.
x During T2 the AD bus is not disabled as it is done in case of memory or I/O
operation.

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 1.10. Timing Diagram for Memory Write

Review Questions

1. What is microprocessor?
2. What are the functions of an accumulator?
3. List the 16 – bit registers of 8085 microprocessor.
4. What is the purpose of READY and TRAP pins in 8085 Microprocessor?
5. List the operations performed by IO/M in 8085.
6. What are the basic units of a microprocessor?
7. What is a bus?
8. List few applications of microprocessor-based system.
9. Give the power supply & clock frequency of 8085.
10. Define ALU.
11. What do you mean by input port & output port?
12. What is the difference between a Microprocessor & CPU?
13. Why is the data bus bidirectional?
14. Specify the four control signals commonly used by the 8085 MPU.

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15. What determines that Microprocessor is an 8, 16 or 32 bit?
16. Explain about evolution of microprocessor in detail.
17. Discuss about the real time applications of microprocessor.
18. Write a short note about Digital computers.
19. What are the various types of semiconductor memory? Describe them briefly.
20. Define Microprocessor. Illustrate the architecture of microprocessor and explain its
components.
21. Draw the pin diagram of 8085 Microprocessor and explain the function of various
signals.

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 UNIT II: Instruction Set Of Intel 8085
2.1. Introduction

An instruction is a command given to the computer to perform a specified operation

on given data. The instruction set of a microprocessor is the collection of the instructions that the
microprocessor is designed to execute. Instruction set of INTEL 8085 have been classified into
five types.

Different types of Instruction set:

1. Data Transfer Group

2. Arithmetic Group
3. Logical Group
4. Branch control Group
5. I/O and Machine Control Group

Data Transfer Group:

Data transfer instructions are used to transfer data from one register to another
register, from memory to register or register to memory. In this group data transferred from
source to destination without any modification of data. Examples are: MOV, MVI, LXI, LDA,
STA etc.

Arithmetic Group:

Arithmetic group instructions add, subtract, increment or decrement data in registers

or in memory. In addition, there is one instruction which adjusts 8-bit data to form BCD
numbers. Examples are: ADD, SUB, INR, DAD etc.

Logical Group:

Logic group instructions perform logic operations such as AND, OR and XOR,
compare data between registers or between register and memory, rotate and complement data in
registers. Examples are: ANA, XRA, ORA, CMP, RAL etc.

Branch control Group:

The branch group instructions allow the microprocessor to change the sequence of a
program, either unconditionally or under certain test conditions. This group includes:

x Jump instructions
x Call and Return instructions
x Restart instructions

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Examples are: JMP, JC, JNC, CALL, RST etc.

I/O and machine Control Group:

This group includes the instructions for input/output ports, stack and machine control.
Examples are: IN, UT, PUSH, POP, HLT etc.

2.2. Instruction and Data Formats

Each instruction has two parts: one is task to be performed, called the operation code
(opcode), and the second is the data to be operated on, called the operand. The operand (or data)
can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, a
memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit. The
8085 instruction set is classified into the following three groups according to word size:

9 One-word or 1-byte instructions

9 Two-word or 2-byte instructions
9 Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.

2.3. Addressing Modes

The way by which the microprocessor identifies the operands for a particular
instruction is known as Addressing mode. Intel 8085 uses the following addressing modes:

ƒ Immediate addressing mode

ƒ Direct addressing mode
ƒ Register addressing mode
ƒ Register indirect addressing mode

2.3.1. Immediate Addressing

In this type of addressing mode the operand is specified within the instruction
itself. Consider the following instruction: ADI 34H – This instruction adds the immediate data,
34H to the accumulator.

34H is the data here. H represents Hexadecimal value and the immediate value is
added to the accumulator. In this case 34H is added to the accumulator. Suppose if accumulator
has a value 8H and when this instruction is executed, 34H is added to the 8H and the result is
stored in accumulator.

22
2.3.2 Register Addressing

In this type of addressing mode the instruction specifies the name of the register
in which the data is available and Opcode specifies the name (or) address of the register on
which the operation would be performed.

Examples are:

(1)MOV A, B

Here the Opcode is MOV. If the above instruction is executed, the contents of Register
B are moved to the Register A, which is nothing but the accumulator.

(2) SUB H

If we execute the above instruction the contents of Register H will be subtracted from
the contents of the accumulator.

2.3.3. Direct Addressing

In this mode of addressing, the address of the data (operand) is specified within the
instruction.

There is a subtle difference between the direct addressing modes and immediate addressing
modes. In immediate addressing mode the data itself is specified within instruction, but in direct
addressing mode the address of the data is specified in the instruction.

Examples are:

OUT 10H, LDA 4100H, STA 2000H

Consider the instruction STA 2000H. When this instruction is executed, the contents of
the accumulator are stored in the memory location specified. In the above example the contents
of accumulator are stored in memory location 2000H.

2.3.4 Register Indirect Addressing

This is indirect way of addressing. In this mode the instruction specifies the name of the
register in which the address of the data is available.

Examples are: MOV A, M, SUB M, DCR M

Consider MOV A, M. This instruction will move the contents of memory location, whose
address is in H-L register pair to the accumulator. M represents the address present in the H-L
register pair. So when MOV A, M is executed, the contents of the address specified in H-L
register pair are moved to accumulator.

23
2.4. Status Flags

The Flag register is a Special Purpose Register. Depending upon the value of result after
any arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085
microprocessor, flag register consists of 8 bits and only 5 of them are useful. The five flags are

x Carry flag (Cy),

x Auxiliary carry flag (AC),
x Sign flag (S),
x Parity flag (P), and
x Zero flag (Z).

The respective position of these flag bits in flag register has been show the below figure. The
positions marked by “x” are to be considered as don't care bits in the flags register. The user is
not required to memorize the positions of these flags in the flags register.

Figure 2.1. Status Flags

2.4.1. Sign Flag(S)

Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it indicates the
number is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number
is positive and the sign flag becomes reset i.e. 0, from 00H to 7F, sign flag is 0,from 80H to FF,
sign flag is 1,1- MSB is 1 (negative),0- MSB is 0 (positive)

Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)

SUB B (A = A – B)

These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number.

2.4.2. Zero Flag (Z)

After any arithmetical or logical operation if the result is 0 (00)H, the zero flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0. Example:

MVI A 10 (load 10H in register A)

24
SUB A (A = A – A)

These set of instructions will set the zero flag to 1 as 10H – 10H is 00H

2.4.3. Carry Flag (Cy)

Carry is generated when performing n bit operations and the result is more than n bits,
then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. During subtraction (A-B), if
A>B it becomes reset and if (A<B) it becomes set. Carry flag is also called borrow flag.
Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)

SUB B (A = A – B)

These set of instructions will set the carry flag to 1 as 30 – 40 generates a carry/borrow.

2.4.4. Auxiliary Carry Flag (AC)

This flag is used in BCD number system(0-9). If after any arithmetic or logical
operation D(3) generates any carry and passes on to B(4) this flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0. This is the only flag register which is not accessible by the programmer.
Example:

MOV A 2B (load 2BH in register A)

MOV B 39 (load 39H in register B)

ADD B (A = A + B)

These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39, addition of
lower order nibbles B and 9 will generate a carry.

2.4.5 Parity flag (P)

If after any arithmetic or logical operation the result has even parity, an even number
of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0. Example:

MVI A 05 (load 05H in register A)

This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which contains
even number of ones i.e. 2.

25
2.5. Intel 8085 instructions

2.5.1. Data Transfer Group

Instructions which are used to transfer the data from a register to another register from
memory to register or register to memory come under this group.

(1) MOV r1,r2: Move the content of the one register to another. For example, the
instruction MOV A,B moves the content of register B to register A.

(2) MOV r,M: Move the content of memory to register. For example the instruction
MOV B,M will move the content of memory location to register B.

(3) MOV M,r: Move the content of register to memory. For example the instruction
MOV M,C will move the content of register C to memory.

(4) MVI r,data: Move immediate data to register. For example the instruction MVI A,05
moves 05 to register A.

(5) MVI M,data: Move immediate data to memory. For example the instruction MVI
M,08 will move 08 to memory.

2.5.2. Arithmetic group

The instructions of this group perform arithmetic operations such as addition, subtraction,
increment or decrement of the content of a register or a memory. Examples are:

(1) ADD r : Add register to accumulator. The content of register r is added to the content
of accumulator, and the sum is placed in the accumulator.
(2) ADD M: Add memory to accumulator. The content of memory location addressed by
H-L pair is added to the content of the accumulator. The sum is placed in the
accumulator.
(3) ADC r: Add register with carry to accumulator. The content of register r and carry
status are added to the content of the accumulator. The sum is placed in the
accumulator.
(4) ADC M: ADD memory with carry to accumulator. The content of the memory
location addressed by H-L pair and carry status are added to the accumulator. The sum
is placed in the accumulator.
(5) ADI data: Add immediate data to accumulator. The immediate data is added to the
content of the accumulator. The 1st byte of the instruction is opcode. The 2nd byte of
the instruction is data, and it is added to the content of the accumulator, The sum is
placed in the accumulator.

26
2.5.3. Logical Group

The instructions in this group perform logical operation such as AND, OR, compare,
rotate, etc. Examples are:

(1) ANA r: AND register with accumulator. The content of register r is ANDed with the
content of the accumulator, and the result is placed in the accumulator. All status
flags are affected. The flag CS is cleared, i.e. it is set to 0. Auxiliary carry flag AC is
set to 1.

(2) ANA M: AND memory with accumulator. The content of the memory location
addressed by H-L pair is ANDed with the accumulator. the result is placed in the
accumulator. All flags are affected. The CS is set to 0 and AC to 1.
(3) ANI data: AND immediate data with accumulator. The second byte of the instruction
is data and it is ANDed with the accumulator. The CS flag is set to 0 and AC to 1.
(4) ORA r: OR-register with accumulator. The content of register r is ORed with the
content of the accumulator. The CS flag is set to 0 and AC to 1.
(5) ORA M: OR-memory with accumulator. The content of the memory location
addressed by H-L pair is ORed with the accumulator. The CS nd AC flags are set to
0.

2.5.4. Branch Control Group

This group contains the instructions for conditional and unconditional jump, subroutine
call and return, and restart. Examples are:

(1) Unconditional jump:

(i) JMP addr(label). Jump to the instruction specified by the operand. The address of
the label is the address of memory location for next instruction to be executed. The
program jumps to the instruction specified by the address unconditionaly.

(2) Conditional jump:

i. JZ addr(label). Jump if the result is zero. The program jumps to the

instruction specified by the address if the result is zero.
ii. JNZ addr(label). Jump if the result is not zero. The program jumps to the
instruction specified by the address if the result is non zero.

27
 (3) CALL addr(label). Call the subroutine identifies by the operand. CALL
instruction is used to call a subroutine. Before the control is transferred to the
subroutine the address of the next instruction of the main program is saved in the
stack. The content of the stack pointer is decremented by two to indicate the new stack
top. Then the program jumps to subroutine starting at address specified by the label.
(4) RET. Return from subroutine. RET instruction is used at the end of the
subroutine. Before the execution of the subroutine the address of the next instruction
of the main program is saved on the stack. The execution of the RET instruction brings
back the saved address from the stack of the program counter. The content of the stack
pointer is incremented by 2 to indicate the new stack top. Then the program jumps to
the instruction of the main program next to CALL instruction which called the
subroutine.
Examples are: RST n, PCHL.

2.5.5. I/O and Machine Control Group

This group contains the instructions for input/output ports, stack and machine control.
Examples are:

(1) IN port – address: Input to accumulator from I/O port. The data available on the port
is moved to the accumulator. After the instruction IN, the address of the port is
specified. The second byte of the instruction contains the address of the port.
(2) OUT port-address: Output from accumulator to I/O port. The content of the
accumulator is moved to the port specified by its address. After the OUT instruction,
the port address is specified. The second byte of the instruction contains the address
of the port.
(3) PUSH rp: Push the content of register pair to stack . The content of the register pair
rp is pushed into the stack.
(4) PUSH PSW: Push processor word. The content of the accumulator is pushed into the
stack. The content of status flags are also pushed into the stack. The content of the
register SP is decremented by 2 to indicate new stack top.
(5) SPHL: Moves the contents of H-L pair to stack pointer. The contents of H-L pair are
transferred to the SP register.

2.6. Programming of Microprocessors

2.6.1. Introduction

x To perform a particular task the programmer prepares a sequence of instructions

called a program. A computer uses binary digits for its operation and understands
information composed of only zeros and ones. Hence the instructions are coded
and stored in the memory in the form of zeros and ones.

28
 x A program written in the form of zeros and ones called a machine language
program. In the machine language there is a specific binary code for each
instruction. For example for Intel 8085 to add the contents of register A and
register B the binary code is 10000000.

2.6.2. Assembly Language

A programmer can easily write a program in alphanumeric symbols instead of zeros and
ones. Meaningful and remember able symbols are chosen for the purpose. Examples are: ADD
for addition, SUB for subtraction etc. Such symbols are called mnemonics. A program written in
mnemonics is known as assembly language program. The writing of a program in assembly
language is much easier and faster as compared to the writing of a program in machine language.

When a program is written in a language other than machine language, a computer cannot
understand it. Consequently, a program written in other languages has to be translated into
machine language before it is executed. A program which translates an assembly language
program into machine language is called an assembler.

2.6.2.1 ONE-PASS AND TWO-PASS ASSEMBLER.

An assembler which goes through an assembly language program only once is known as
one-pass assembler. Such an assembler must have some technique to take the forward
references into account.

An assembler which goes through an assembly language program twice is known as

two-pass assembler. Such an assembler does not face difficulty with forward references. During
the first pass it collects all the labels. During the second pass it produces the machine code for
each instruction and assigns addresses to each of them.

One-pass assembler is faster as it goes through a program only once. Its disadvantage is
that it does not provide as many features as a two-pass assembler can.

Example: An assembly language program for the addition of two numbers placed in two
consecutive memory locations 2501H and 2502H is given below. The sum is stored in the
memory location 2503H.

Mnemonics, operands, data of the program and starting address for the program are
fed to the computer. The assembler converts the program into a machine language program
before the execution of the program. The codes are written in hexadecimal system.

Mnemonics operands

LXI H,2501H
MOV A, M
INX H

29
 ADD M
STA 2503H
HLT

DATA

2501- 49H

2502- 56H

Result:

2503- 9F

2.6.2.2 Advantages and disadvantages of assembly language

The advantages over to high level language such as FORTRAN, COBOL etc. is that the
computation time is less. An assembly language program is faster to produce result. The
disadvantages of assembly language are:

1. Programing is difficult and time consuming.

2. The assembly language is computer oriented.
3. Assembly language is not portable.
4. An assembly language program is longer as compared to a high level l language
program.

2.7. Stacks

The stack is a group of memory location in the R/W memory that is used for temporary
storage of binary information during the execution of a program. The stack is a LIFO structure
Last In First Out. The starting location of the stack is defined by loading a 16 bit address into the
stack pointer that spaced is reserved, usually at the top of the memory.

The stack normally grows backwards into memory. The stack can be initialized
anywhere in the user memory map, but stack is initialized at the highest memory location so that
there will not be any interface with the program.

In 8085 microprocessor system the beginning of the stack is defined in the program by
using the instruction LXI SP,16 bit. The LXI SP,a 16 bit state that load the 16 bit address into the
stack pointer register.

The 8085 provide two instructions PUSH & POP for storing information on the stack
and retrieving it back. Information in the register pairs stored on the stack in reverse order by

30
using the instruction PUSH. Information retrieved from the stack by using the instruction POP.
PUSH & POP both instruction works with register pairs only. The storage and retrieval of the
content of registers on the stack fallows the LIFO(Last-In-First-Out) sequence. Information in
the stack location may not be destroyed until new information is stored in that memory location.

2.8. Subroutines

A subroutine is group of instruction written separately from the main program to

perform a function that occurs repeatedly in the main program. When a main program calls a
subroutine the program execution is transferred to the subroutine after the completion of the
subroutine, the program execution returns to the main program. The microprocessor uses the
stack to store the return address of the subroutine.

The 8085 has two instructions for dealing with subroutines. The CALL instruction is
used to redirect program execution to the subroutine. The RET instruction is used to return to the
main program at the end of the subroutine.

The CALL instruction: Call subroutine in conditionally located at the memory

address specified by the 16 bit operand. This instruction places the address of the next instruction
on the stack and transfers the program execution to the subroutine address.

The RET instruction: Return unconditionally from the subroutine. This instruction
locates the return address on the top of the stack and transfers the program execution back to the
calling program.

2.9. MACRO

A sequence of instructions to which a name is assigned is called a macro. The name of

the macro is used in assembly language programming. The macro facility is available with many
assemblers. Each macro is clearly defined and unique name is assigned to it.

Example.

COMPLE MACRO ADDRESS

LXI H, ADDRESS

MOV A,M

CMA

ENDM

31
 In the above example COMPLE is the name of the macro. MACRO is written in the
beginning of the definition. ADDRESS is a parameter. ENDM is used to end the macro.

2.10. Microprogramming

The CPU performs the following tasks to execute an instruction:

1. The CPU places the content of the program counter on the address bus to fetch the
opcode of the instruction from the memory.
2. The CPU reads the opcode from the memory and places it in the instruction register.
3. The CPU decodes the instruction.
4. The CPU takes other data, if necessary, from the memory or other register to execute the
instruction.
5. The CPU executes the instruction.

Review Questions

1. What is an instruction?
2. List the types of instructions.
3. What are three types of instructions based on length?
4. Define addressing modes.
5. What are the types of addressing modes?
6. What is status flag?
7. What is assembly language?
8. Define assembler.
9. What do you mean by assembly language program?
10. What is Stack?
11. What is meant by subroutines?
12. Classify 8085 instruction in various groups. Give examples of instructions for each
group.
13. What are the various types of data formats for Intel 8085 instructions? Give examples for
each type of data format.
14. Discuss various types of addressing modes of Intel 8085 with suitable examples.
15. Write short notes on assembly language program.
16. What is stack? What is the function of stack pointer? Discuss PUSH and POP operation.
17. Explain subroutine. What instruction is used to call a subroutine?
18. Explain macro. What is the difference between a macro and subroutine?

32
 UNIT III- ASSEMBLY LANGUAGE PROGRAMMING
3.1. Introduction

To learn assembly language programming the beginner should write simple programs and
try to execute them n Intel 8085 microprocessor kit. The memory addresses given in the
programs are for a particular microprocessor kit. Before writing assembly language program, one
should learn some important Intel 8085 instructions such as MOV, MVI, ADD, SUB, LXI, LDA,
INX, INR, HLT etc.

3.2. Simple Examples

Example 1. Object: Place 05 in register B.

PROGRAM

Memory Machine Mnemonics Operands Comments

address codes
FC00 06,05 MVI B,05 Get 05 in register B
FC02 76 HLT Stop
9 The instruction MVI B, 05 moves 05 to register B. HLT halts the program. A program is
fed to the microprocessor kit in machine codes. The machine code for the instruction
MVI B, 05 is 06, 05. The first byte of the instruction is 06 which is machine code for the
MVI B. The code HLT is 76.
9 The machine code 06 entered in the memory FC00H, 05 in FC01 and 76 in FC02H.
After the execution of the program the register B will contain 05. The symbol H after a
digit denotes that it is in hexadecimal system.

Example 2. Get 05 in register A ; Then move it to register B.

Memory Machine Mnemonics Operands Comments

address codes
FC00 3E,05 MVI A,05 Get 05 in register A.
FC02 47 MOV B,A Transfer 05 from register A to B.
FC03 76 HLT Stop

The instruction MVI A,05 will move 05 to register A. In the code from it is written as
3E, 05. The first byte of the instruction is 3E. This code is for MVI A. The second byte 05 is the

33
data which is to be placed in A. The instruction MOV B,A transfers the content of register A to
register B. After the execution of the program register B will contain 05.

3.3. Addition and Subtraction

3.3.1. Addition of two 8-bit Numbers

Problem:

Add 49H and 56H.

The first number 49H is in the memory location 2501H.

The second number 56H is in the memory location 2502H.

The result is to be stored in the memory location 2503H.

Numbers are represented in hexadecimal system.

Memory Machine codes Mnemonics Operands Comments

address
2000 21,01,25 LXI H,2501H Get address of first number in
H-L pair.

2003 7E MOV A,M First number in accumulator.

2004 23 INX H Increment content of H-L pair.

2005 86 ADD M Add first and second number.

2006 32,03,25 STA 2503H Store sum in 2503H.

2009 76 HLT

34
DATA

2501- 49H

2502- 56H

The sum is stored in the memory location 2503H.

Result

2503- 9F H.

9 2501 H is the address of memory location for the first number. 2501 is placed in H-L pair
by the instruction LXI H, 2501 H. The next instruction is MOV A,M which moves the
content of the memory location addressed by H-L pair to the accumulator.
9 In this case H-L pair contains 2501 H and, therefore, the content of the memory location
2501H is moved to the accumulator. Thus the first number 49H has been moved to the
accumulator.
9 The instruction INX H increases the content of H-L pair by one. Previously the content of
H-L pair was 2501H. After the execution of INX H it becomes 2502H. ADD M adds the
content of the accumulator and the content of the memory location addressed by H-L
pair.
9 The content of 2502 H is the second number 56H. So 56H is added to 49H. Sum resides
in the accumulator. The instruction STA 2503H stores the sum in the memory location
2503H. The instruction HLT ends the program.

3.3.2. Subtraction of two 8-bit Numbers

Problem:

Subtract 32H from 49H.

The first number 49 H is in the memory location 2501H.

The second number 32 H is in the memory location 2502H.

The result is to be stored in the memory location 2503H.

Memory address Machine codes Mnemonics Operands Comments

2000 21,01,25 LXI H,2501 H Get address f first number in

H-L pair.

2003 7E MOV A,M First number in accumulator.

35
2004 23 INX H Content of H-L pair
increases from 2501H to
2502H.
2005 96 SUB M First number – Second
number.

2006 23 INX H Content of H-L pair

becomes 2503H.

2007 77 MOV M,A Store result in 2503H.

2008 76 HLT Halt.

DATA

2501- 49H

2502- 32H

Result is stored in the memory location 2503H.

2503- 17H.

9 The first number is in the memory location 2501H. 2501 is placed in H-L pair by the
execution of the instruction LXI H, 2501 H. The instruction MOV A,M moves the
content of the memory location addressed by H-L pair to the accumulator.
9 Thus the first number 49H has been moved to the accumulator. The instruction INX H
increases the content of H-L pair by one. Previously the content of H-L pair was 2501H.
After the execution of INX H it becomes 2502H.
9 SUB B subtracts the content of the accumulator from the content of the memory location
addressed by H-L pair. The content of 2502 H is the second number 32H. So 32H is
subtracted from 49H. The result resides in the accumulator. The instruction STA 2503H
stores the result in the memory location 2503H. The instruction HLT ends the program.

3.3.3. Decimal addition of two 8-bit Numbers

Problem:

Add 84D and 75 D, D stands for decimal number.

Sum=159=01, 59 D

59 is the LSDs of the sum.

36
01 is the MSDs of the sum.

The first number 84D is in the memory location 2501H.

The second number 75D is in the memory location 2502H.

The sum is to be stored in 2503H and 2504H.

DATA

2501- 84D

2502- 75D

Result

2503- 59 D, LSDs of the sum.

2504- 01 D, MSDs of the sum.

Memory Machine code Mnemonics Operands Comments

address
2000 21,01,25 LXI H, 2501H Address of first number in H-L
pair.
2003 0E,00 MVI C,00 MSBs of sum in register C.
Initial value = 00.
2005 7E MOV A,M First number in accumulator.

2006 23 INX H Address of second number

2502 in H-L pair.
2007 86 ADD M First number +
second number.
2008 27 DAA Decimal adjust.

2009 D2,0D,20 JNC AHEAD Is carry? No, go to the label

AHEAD.
200C 0C INR C Yes, increment C.

200D 32,03,25 STA 2503H LSDs of sum in 2503H.

37
2010 79 MOV A,C MSDs of sum in accumulator.

2011 32,04,25 STA 2504H MSDs of sum in 2504H.

2014 76 HLT

The program for “Decimal addition of two 8-bit number” is same as that for “addition of two
8-bit numbers” except that DAA instruction has been used for decimal adjustment after the
instruction ADD M. After the execution of the ADD M the sum is in hexadecimal. The DAA
instruction makes correction and the final result is obtained in decimal system.

3.3.4. Decimal subtraction of two 8-bit Numbers

Problem:

The first number 96 D is in the memory location 2501 H.

The second number 38 D is in the memory location 2502H.

Result 58 D is to be stored in the location 2503H.

DAA instruction cannot be used after SUB or SBB instruction for decimal subtraction. It is
used only after DD, ADC. Therefore, for decimal subtraction the number which is to be
subtracted is converted into 10’s complement. In this example 38D is to be subtracted. 10’s
complement of 38 is first obtained and then it is added to 96D.

DATA

2501- 96

2502- 38

Result

2503- 58

Memory Machine codes Mnemonics Operands Comments

address
2000 21,02,25 LXI H,2502H Get address of second number in H-
L pair.

38
2003 3E,99 MVI A,99 Place 99 in accumulator.

2005 96 SUB M 9’s complement of second number.

2006 3C INR A 10’s complement of second number.

2007 2B DCX H Get address of first number.

2008 86 ADD M Add first number and 10’s

complement of second number.
2009 27 DAA Decimal adjust

200A 32,03,25 STA 2503H Store result in 2503H.

200D 76 HLT Halt.

3.4. Complements

3.4.1. Find one’s complement of an 8-bit number

Example: Find one’s complement of 96 H. The number in the binary form is represented as
follows:

96 H = 1001 0110

(9) (6)

One’s complement =0110 1001= 69 H

(6) (9)

To obtain one’s complement of a number its 0 bits are replaced by 1 and 1 by 0. The number is
placed in the memory location 2501 H. The result is stored in the memory location 2502 H.

Memory address Machine codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501 H Get data in

accumulator.

39
2003 2F CMA Take its
complement.
2004 2,02,25 STA 2502 H Store result in 2502
H.
2007 76 HLT Halt

DATA

2501- 96 H

Result

2502- 69 H

The instruction LDA 2501 H transfers the number from memory location 2501 H to the
accumulator. CMA takes complement of the number. STA 2502 H stores the result in the
memory location 2502 H. HLT ends the program.

3.4.2. Find one’s complement of a 16-bit number

Example: Find one’s complement of 5485 H.

The number in the binary form can be represented as follows:

5485= 0101 0100 1000 0101

(5) (4) (8) (5)

One’s complement = 1010 1011 0111 1010= AB7A H

(A) (B) (7) (A)

The number is in the memory location 2501 and 2502 H. The result is to be stored in the memory
locations 2503 H and 2504 H.

Memory address Machine codes Mnemonics Operands Comments

2000 21,01,25 LXI H, 2501 H Address of LSBs of the

number.
2003 7E MOV A,M 8 LSBs of the number in
accumulator.

40
2004 2F CMA Complement of 8 LSBs of
the number.
2005 32,03,25 STA 2503 H Store 8 LSBs of result.
2008 23 INX H Address of 8 MSBs of the
number.
2009 7E MOV A,M 8 MSBs of the number in
accumulator.
200A 2F CMA Complement of 8 MSBs of
the number.
200B 32,04,25 STA 2504 Store 8 MSBs of the result.

200E 76 HLT Halt

DATA

2501- 85 H, LSBs of the number.

2502- 54 H, MSBs of the number.

Result

2503- 7A H, LSBs of the result.

2504- AB H, MSBs of the result.

The 8 LSBs of the number re in the memory location 2501 H. The address 2501 is placed in
H-L pair. The 8 LSBs of the number are transferred from 2501 H to the accumulator. The
instruction CMA takes one’s complement of 8 LSBs. The 8 LSBs of the result are stored in the
memory location 2503 H. The address of 8 MSBs of the number is 2502 H, and it is placed in H-
L pair. The 8 MSBs of the number are transferred from 2502 H to the accumulator. The
instruction CMA takes one’s complement 0f 8 MSBs. The 8 MSBs of the result are stored in
memory location 2504.

3.5. Shift

3.5.1. Shift an 8-bit number Left by One Bit

Example: Shift 65 left by one bit.

The binary representation of 65 is given below:

41
 65= 0110 0101

(6) (5)

Result of shifting

65 left by one bit = 1100 1010= CA

To shift a number left by one bit the number is added to itself or it is doubled. If 65 is added
to 65, the result is CA as shown below.

65= 0110 0101

+65= 0110 0101

1100 1010= CA

The number is placed in memory 2501 H.

The result is to be stored in memory 2502 H.

Memory Machine codes Mnemonics Operands Comments

Address
2000 3A,01,25 LDA 2501 H Get data in
accumulator.
2003 87 ADD A Shift it left by one
bit.
2004 32,02,25 STA 2502 H Store result in 2502
H.
2007 76 HLT

DATA

2501- 65 h

Result

2502- CA H

The instruction LDA 2501 H transfers the number from memory location 2501 H to the
accumulator. ADD A adds the contents of the accumulator to itself. The result is twice the
number and thus the number is shifted left by one bit. This program does not take carry into

42
account after ADD instruction. If numbers to be handled are likely to produce carry the program
may be notified to store it.

3.5.2. Shift an 8-bit number Left by 2 Bits

Example: Shift 15 left by two bits.

15= 0001 0101

(1) (5)

Shift left by one bit =0010 1010= 2A

(2) (A)

Shift the result bit by one bit = 0101 0100= 54

i.e. Shift the number left by two bits (5) (4)

The shifting of number left by two bits can be achieved by adding the number to itself and
again adding the sum to itself. This is obtained by using the instruction ADD A twice.

The number is placed in the memory location 2501 H.

The result is to be stored in the memory location 2502 H.

PROGRAM

Memory address Machine codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501 H Get data in
accumulator.
2003 87 ADD A Shift it left by
one bit.
2004 87 ADD A Again shift left
one bit.
2005 32,02,25 STA 2502 H Store result in
2502 H.
2008 76 HLT Stop

DATA

2501- 15 H

Result

2502- 54H

43
3.5.3. Shift a 16-bit number Left by One Bit

Example: Shift 7596 H left by one bit.

7596= 0111 0101 1001 0110

(7) (5) (9) (6)

Result of shifting left by one bit = 1110 1011 0010 1100= EB2C

(E) (B) (2) (C)

The number is placed in the memory locations 2501 and 2502 H.

The result is to be stored in memory locations 2503 and 2504 H.

Memory address Machine codes Mnemonics Operands Comments

2000 2A,01,25 LHLD 2501 H Get data in H-L
pair
2003 29 DAD H Shift left by one
bit
2004 22,03,25 SHLD 2503 H Store result in
2503 and 2504 H.
2007 76 HLT Stop

DATA

2501- 96, LSBs of the number.

2502- 75, MSBs of the number.

Result

2502- 2C, LSBs of the result

2504- EB, MSBs of the result.

3.5.4. Shift a 16-bit number Left by Two Bits

Example: Shift 1596 H left by 2 bits.

1596= 0001 0101 1001 0110

(1) (5) (9) (6)

44
Result of shifting left by one bit =0010 1011 0010 1100= 2B2C

(2) (B) (2) (C)

Result of shifting 2 bits left =0101 0110 0101 1000= 5658

(5) (6) (5) (8)

The result is stored in the memory locations 2501 and 2502 H.

The result is to be stored in the memory locations 2503 and 2504 H.

Memory address Machine Mnemonics Operands Comments

codes
2000 2A,01,25 LHLD 2501 H Get data in H-L
pair.
2003 29 DAD H Shift left by one
bit.
2004 29 DAD H Again shift left by
one bit.
2005 22,03,25 SHLD 2503 H Store result in
2503 and 2504 H
2008 76 HLT Stop

DATA

2501- 96, LSBs of the number

2502- 15, MSBs of the number.

Result

2503- 58, LSBs of the result.

2504-56, MSBs of the result.

3.5. Mask

3.5.1. Mask off least significant 4 bits of an 8-Bit number

Example:

Number = A6

= 1010 0110

(A) (6)

45
 Result = A0 = 1010 0000

(A) (0)

The LSD of the given number A6 is 6. The MSD of the number A6 is A. In the binary form it
is 1010. If this number is multiplied by 1111 i.e. F, it will not be affected. Similarly the LSD of
the number is 6. In the binary form is represented by 0110. If it is multiplied by 0000, it becomes
0000 i.e. it is cleared. Thus if the number A6 is multiplied by F0, the LSD of the number is
masked off.

DATA

2501- A6

Result

2502- A0

Memory address Machine Mnemonics Operands Comments

codes
2000 3A,01,25 LDA 2501 H Get data in
accumulator.
2003 E6,F0 ANI F0 Mask off the least
significant 4 bits.
2005 32,02,25 STA 2502 H Store result in
2502 H.

2008 76 HLT Stop

3.5.2. Mask off most significant 4 bits of an 8-Bit number

Example:

Number = A6

= 1010 0110

(A) (6)

Result= 06 = 0000 0110

(0) (6)

46
 To mask off 4 most significant bits of a number, 4 MSBs are multiplied by 0000. The least
significant bits are not to be affected and, therefore, they are multiplied by 1111 i.e. F. Thus if an
8 bit number is multiplied by 0F, the 4 most significant bits are cleared.

Memory address Machine codes Mnemonics Operands Comments

2000 3A,01,25 LDA 2501 H Get data in
accumulator.
2003 E6,0F ANI 0F Mask off the
most
significant 4
bits.
2005 32,02,25 STA 2502 H Store result in
2502 H.
2008 76 HLT Stop

DATA

2501- A6

Result

2502- 06

3.6. Finding the largest and smallest number in an array

x One by one all elements are compared with B and C register.

x Element is compared with maximum, if it greater than maximum then it is stored in B
register. Else, it is compared with minimum and if it is less than minimum then it stored
in C regiter.
x Loop executes 10 number of times.
x At the end of 10 iterations, maximum and minimum are stored at 2060H and 2061H
respectively.

Memory Mnemonics Comments

Address

2000H LXI H, 2050H Load starting address of list

2003H MOV B, M Store maximum

2004H MOV C, M Store minimum

47
2005H MVI D, 0AH Counter for 10 elements

2007H LOOP MOV A, M Retrieve list element in Accumulator

2008H CMP B Compare element with maximum number

2009H JC MIN Jump to MIN if not maximum

200CH MOV B, A Transfer contents of A to B as A > B

200DH MIN CMP C Compare element with minimum number

200EH JNC SKIP Jump to SKIP if not minimum

2011H MOV C, A Transfer contents of A to C if A < minimum

2012H SKIP INX H Increment memory

2013H DCR D Decrement counter

2014H JNZ LOOP Jump to LOOP if D > 0

2017H LXI H, 2060H Load address to store maximum

201AH MOV M, B Move maximum to 2060H

201BH INX H Increment memory

201CH MOV M, C Move minimum to 2061H

201DH HLT Halt

example: 42H, 21H, 01H, 1FH, FFH, 25H, 32H, 34H, 0AH, ABH

Minimum: 01H Maximum: FFH

3.7. Arranging a Series of numbers

Arrange E5, A9, 96, B4 and 15 in ascending order. These numbers are in the memory
locations 2501 to 2505 H.

Count= 05, it is stored in 2500H.

Results are to be stored in 2601 to 2605H.

48
Address Machine Label Mnemonics Operands Comments
Codes
2000 11, 01, 26 LXI D,2601 Memory locations to store
result.
2003 21, 00, 25 LXI H,2500 Count address in H-L pair.
2006 46 MOV B,M
2007 C2,00,22 START CALL 2200 Call subroutine-1 to find
smallest number.
200A 12 STAX D Store the result.
200B CD,50,20 CALL 2050 Call subroutine-2 to check
which number is smallest
200E 13 INX D
200F 05 DCR B
2010 C2,07,20 JNZ START
2013 HLT stop

SUBROUTINE-1 To find smallest number

2200 21,00,25 LXI H, 2500

2203 4E MOV C,M
2204 3E,FF MVI A,FF Get FF in accumulator
2206 23 LOOP INX
2207 BE CMP M Compare next number
2208 DA,OC,22 JC AHEAD No, Go to AHEAD
220B 7E MOV A,M Yes, get smaller number in
accumulator
220C 0D DCR C
220D C2,06,22 JNZ LOOP
2210 C9 RET

SUBROUTINE-2

2050 21,00,25 LXI H, 2500

2053 4E MOV C,M
2054 23 BEHIND INX H
2055 BE CMP M Compare the next number
with smallest number which
is in accumulator
2056 CA,5D,20 JZ FORWARD
2059 0D DCR C
205A C2,54,20 JNZ BEHIND
205D 3E,FF FORWARD MVI A,FF

49
205F 77 MOV M,A Replace the smallest
number by FF
2060 C9 RET

EXAMPLE:

DATA

2500 – 05, 2501 – E5, 2502 – A9, 2503 – 96, 2504 – B4, 2505 – 15

RESULT

2601 – 15, 2602 – 96, 2603- A9, 2604 – B4, 2605 – E5

3.8. Sum of a series of Numbers

Address Machine codes Label Mnemonics Operands Comments

2400 21,00,25 LXI H,2500 Address for the count
in H-L pair
2403 4E MOV C,M The count in register
C
2404 3E,00 MVI A,00 Initial value of sum
=00
2406 23 LOOP INX H
2407 86 ADD M Previous sum + next
number
2408 0D DCR C
2409 C2,06,24 JNZ LOOP
240C 2,50,24 STA 2450 H Store sum in 2450H
240F 76 HLT

x The numbers are placed in the memory locations 2501 to 2504 H

x The sum is stored in the memory location 2450 H.
x As there are 4 numbers in the series, count = 04. The initial value of the sum is made 00.
The number of the series are taken one by one and added to the sum.

DATA: 2500 – 04, 2501 – 16, 2502 – 2B, 2503 – 39, 2504 – 12

Result: 2450 – 8C

3.9. Multiplication

MEMORY ADDRESS MNEMONICS COMMENTS

2000 LHLD 2050 Load H-L pair with address 2050

50
2003 SPHL SAVE IT IN STACK POINTER

2004 LHLD 2052 Load H-L pair with address 2052

2007 XCHG EXCHANGE HL AND DE PAIR CONTENT

2008 LXI H,0000H H<-00H,L<-00H

200B LXI B,0000H B<-00H,C<-00H

200E DAD SP

200F JNC 2013 JUMP NOT CARRY

2012 INX B INCREMENT BC BY 1

2013 DCX D DECREMENT DE BY 1

2014 MOV A, E A<-E

2015 ORA D OR THE CONTENT OF ACCUMULAOR

2016 JNZ 200E JUMP NOT ZERO

2019 SHLD 2054 L<-2054,H<-2055

201C MOV L,C L<-C

201D MOV H,B B<H

201E SHLD 2056 L<-2055,H<-2056

2021 HLT TERMINATES THE PROGRAM

x Starting address of program: 2000

x Input memory location: 2050, 2051, 2052, 2053
x Output memory location: 2054, 2055, 2056, 2057

INPUT:

(2050H) = 04H

(2051H) = 07H

(2052H) = 02H

(2053H) = 01H

OUTPUT:

51
 (2054H) = 08H

(2055H) = 12H

(2056H) = 01H

(2057H) = O0H

3.10. Division

x Starting address of program: 2000

x Input memory location: 2050, 2051, 2052, 2053
x Output memory location: 2054, 2055, 2056, 2057.

INPUT:

(2050H) = 04H

(2051H) = 00H

(2052H) = 02H

(2053H) = 00H

OUTPUT:

(2054H) = 02H

(2055H) = 00H

(2056H) = FEH

(2057H) = FFH

MEMORY ADDRESS MNEMONICS COMMENTS

2000 LXI B, 0000H INITIALISE QUOTIENT AS 0000H

2003 LHLD 2052H LOAD THE DIVISOR IN HL

2006 XCHG EXCHANGE HL AND DE

2007 LHLD 2050 LOAD THE DIVIDEND

52
200A MOV A, L A<-L

200B SUB E A<-A-E

200C MOV L, A L<-A

200D MOV A, H A<-H

200E SBB D A<-A-D

200F MOV H, A H<-A

2010 JC 2018 JUMP WHEN CARRY

2013 INX B B<-B+1

2014 JMP 200B

2017 DAD D HL<-DE+HL

2018 SHLD 2056 HL IS STORED IN MEMORY

201B MOV L, C L<-C

201C MOV H, B H<-B

201D SHLD 2054 H L IS STORED IN MEMORY

2020 HLT TERMINATES THE PROGRAM

Review Questions

1. Write an assembly language program to add two 8- bit numbers, the sum may be of
16 bits.
2. Write an assembly language program to add two 8-bit decimal numbers, sum may be
of 16 bits.
3. Write an assembly language program to get 2’s complement of a 16-bit number.
4. Write an assembly language program to find the largest number in a data array.
5. Write an assembly language program to find the sum of a series of 8-bit numbers,
sum may be of 16-bits.
6. Write an assembly language program to find the smallest number in a array.
7. Write an assembly language program for 8- bit multiplication.
8. Write an assembly language program for 8-bit division.

53
 UNIT IV- PERIPHERAL DEVICES AND THEIR INTERFACING

4.1. Introduction

A microprocessor combined with memory and input/output devices forms a

microcomputer. The microprocessor is the heart of a microcomputer. Memories and input/output
devices are interfaced to microprocessor to form a microcomputer.

4.1. Address space partitioning

Intel 8085 uses a 16-bit wide address bus or addressing memory and I/O devices. It
can access 216=64k bytes of memory and I/O devices. There are two schemes for the allocation
of address to memories or I/O devices.

1. Memory mapped I/O scheme

2. I/O mapped I/O scheme

Memory Mapped I/O Scheme

In this scheme there is only one address space. Address space is defined as set of all
possible addresses that a microprocessor can generate. Some address are assigned to memories
and some address to I/O devices. Suppose memory locations are assigned the address 2000-2500.
One address is assigned to each memory location. These addresses cannot be assigned to I/O
devices. The addresses assigned to I/O devices are different from address assigned to memory.
For example, 2500, 2501, 2502 etc. may be assigned to I/O devices. One address is assigned to
each I/O device.

In this scheme all the data transfer instruction of the microprocessor can be used for
both memory as well as I/O devices. For example, MOV A, M will be valid for data transfer
from the memory location or I/O device whose address is in H-L pair. This scheme is suitable for
small system.

I/O Mapped I/O Scheme

In this scheme the address are assigned to memory locations can also be assigned to I/O
devices. To distinguish whether the address on an address bus is for memory location or I/O
devices. The Intel 8085 issues IO/M…… signal for this purpose. When the signal is high the
address of an address bus is for I/O device. When low, the address is for a memory location. Two
extra instructions IN and OUT are used to address I/O device. The IN instruction is used to read
data from an input device. And OUT instruction is used to an output device. This scheme is
suitable for large system.

54
4.2. Memory Interfacing

An address decoding circuit is employed to select the required I/O device or a memory
chip. When IO/M is high, decoder is to active and the require IO device is selected. If IO/M is
low, the decoder1 is activated the required memory chip is selected. A few MSB of address line
is applied to the decoder to select the memory chip or an I/O device.

4.1. Schematic Diagram for memory and I/O interfacing

4.3. Data Transfer Schemes

The method that is used to transfer information between internal storage and external I/O
devices is known as I/O interface. The CPU is interfaced using special communication links by
the peripherals connected to any computer system. These communication links are used to
resolve the differences between CPU and peripheral. There exists special hardware components
between CPU and peripherals to supervise and synchronize all the input and output transfers that
are called interface units.

Data transfer to and from the peripherals may be done in any of the three possible ways

1. Programmed data transfer scheme

2. DMA (Direct Memory Access)

Programmed I/O: It is due to the result of the I/O instructions that are written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually the

55
transfer is from a CPU register and memory. In this case it requires constant monitoring by the
CPU of the peripheral devices.

Example of Programmed I/O: In this case, the I/O device does not have direct access to
the memory unit. A transfer from I/O device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from device to the
CPU and store instruction to transfer the data from CPU to memory. In programmed I/O, the
CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This is
a time consuming process since it needlessly keeps the CPU busy. This situation can be avoided
by using an interrupt facility.

Direct Memory Access: The data transfer between a fast storage media such as magnetic disk
and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly
communicate with each other using the memory buses, removing the intervention of the CPU.
This type of data transfer technique is known as DMA or direct memory access. During DMA
the CPU is idle and it has no control over the memory buses. The DMA controller takes over the
buses to manage the transfer directly between the I/O devices and the memory unit.

Types of DMA transfer using DMA controller:

Burst Transfer : DMA returns the bus after complete data transfer. A register is used as a byte
count, being decremented for each byte transfer, and upon the byte count reaching zero, the
DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the
duration of the data transfer.

Cyclic Stealing :

An alternative method in which DMA controller transfers one word at a time after which it
must return the control of the buses to the CPU. The CPU delays its operation only for one
memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.

Synchronous Data Transfer

Synchronous means “ at the same time”. The device which spends data and the device which
receives data are synchronized with the same clock. When the CPU and I/O devices match in
speed this technique of data transfer is employed.

Synchronous transmission is effective, dependable, and often utilised for transmitting a large
amount of data. It offers real-time communication between linked devices. An example of
synchronous transmission would be the transfer of a large text file. Before the file is transmitted,
it is first dissected into blocks of sentences. The blocks are then transferred over the
communication link to the target location.

56
 Because there are no beginning and end bits, the data transfer rate is quicker but there’s an
increased possibility of errors occurring. Over time, the clocks will get out of sync, and the
target device would have the incorrect time, so some bytes could become damaged on account of
lost bits. To resolve this issue, it’s necessary to regularly re-synchronise the clocks, as well as to
make use of check digits to ensure that the bytes are correctly received and translated.

ASynchronous Data Transfer

In asynchronous transmission, data moves in a half-paired approach, 1 byte or 1 character at a

time. It sends the data in a constant current of bytes. The size of a character transmitted is 8 bits,
with a parity bit added both at the beginning and at the end, making it a total of 10 bits. It
doesn’t need a clock for integration—rather, it utilizes the parity bits to tell the receiver how to
translate the data.It is straightforward, quick, cost-effective, and doesn’t need 2-way
communication to function.

4.2. Asynchronous Data Transfer

Interrupt Driven Data Transfer

In the asynchronous mode of transfer, microprocessor is busy all the time in checking for the
availability of data from the slower I/O devices. And it also busy in checking if I/O device is
ready for the data transfer or not. In other words in this data transfer scheme, some of the
microprocessor time is wasted in waiting while an I/O device is getting ready. To overcome this

57
problem interrupt driven I/O data transfer introduced. In this interrupt driven I/O data transfer
method the I/O device informs the microprocessor for the data transfer whenever the I/O device
is ready. This is achieved by interrupting the microprocessor by using the interrupt pins of
microprocessor.

4.3. Interrupt Driven Data Transfer Scheme for an A/D Converter

In the beginning the microprocessor initiates data transfer by requesting the I/O device ‘to get
ready’ and then continue executing its original program rather wasting its time by checking the
status of I/O device. Whenever the device is ready to accept or supply data, it informs the
processor through a control signal. This control signal known as interrupt (INTR) signal. In
response to this interrupt signal, the microprocessor sends back an interrupt acknowledge signal
to the I/O device. Interrupts driven data transfer is better from asynchronous mode but it is still
not very effective technique when data needs to be transferred in large amounts because it
requires an interrupt for every character read or written. This leads us to an another approach
called direct memory access(DMA) mode.

4.4. Interrupts of intel 8085

Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device. The process is asynchronous, means can occur at any
time during execution of program. ,QRUGHUWRFRPPXQLFDWHZLWKȝ3 ,2GHYLFHVHLWKHU3ROOLQJ
or Interrupt method is used. An interrupt is considered to be an emergency signal. The
Microprocessor should respond to it as soon as possible.

58
 4.4. Schematic Diagram of 8085 Interrupts

Polling Method LQSROOLQJȝ3SROOVLHDVNHDFKGHYLFHLQVHTXHQFHZKHWKHULWLVUHDG\IRU

communication (data transfer). If device is ready, then data transfer takes place between device
& ȝ3,IGHYLFHLVQRWUHDG\RUFRPSOHWHGLWVGDWDWUDQVIHUWKHQȝ3DVNVWKHQH[WGHYLFHLQFKDLQ
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useful tasks get less time to execute. This method is useful oQO\ LI ȝ3 KDV FRQWDLQV IHZ ,2
devices.

Interrupt is signal send by an external device to the microprocessor to request the processor
to perform a particular task or work. It is a simple routine program that keeps a check for the
occurrence of the interrupt. Mainly in the microprocessor based system the interrupts are used
IRU GDWD WUDQVIHU EHWZHHQ WKH SHULSKHUDO ,2  DQG WKH PLFURSURFHVVRU ,I WKH ȝ3 DFFHSW WKH
interrupt and send the INTA (active low) signal to the peripheral. When interrupt is receLYHGȝ3
suspends its current activity and upon completion, it resumes the suspended activity. The
processor executes an interrupt service routine (ISR) addressed in program counter. It returned to
PDLQ SURJUDP E\ 5(7 LQVWUXFWLRQ $GYDQWDJH LV WKDW ȝ3 QHHG not waste time in polling the
devices.

4.4.1. Interrupt process

x When the MPU is executing a program it checks all the interrupt lines during the
execution of each instruction.

59
 x If any Interrupt line is enables, the processor completes the current going
instruction execution.
x If more than one lines are enabled simultaneously then the processor pick up the
request which have the highest priority and all other are discarded.
x After completion of the current instruction execution, processor checks for the
respective conditions for the activated interrupt or selected interrupt in case of
more than one.
x If condition are not favorable then request is discarded or stored or if the condition
are favorable then the processor generates an external INTA or internal
acknowledges signal to insert a RST(restart) instruction or the vector location
respectively.
x Now the processor save the address of the next instruction (program counter
value) on to stack and switch to the related RST location or vector location.
x Service routine written on the location is completed which have RET as its last
instruction which returns the program control to the main program by retrieving
the return address from the stack.

4.4.2. Types of interrupts

i. Software Interrupt
ii. Hardware Interrupt

Software interrupts: It is a instruction based Interrupt which is completely control by software.

That means programmer can use this instruction to execute interrupt in main program. There are
HLJKWVRIWZDUHLQWHUUXSWDYDLODEOHLQȝ3WKDWDUH567WR567

The vector address for these interrupts can be calculate as Interrupt number * 8 = vector address
For RST 5 5*8 = 40(in decimal) =28H (in Hexa) Vector address for interrupt RST5 is 0028H.
This vector address is stored in Program Counter(PC). These instruction allow transfer of
program control from the main program to predefined service routine is also referred to as
ISR(Interrupt Service Routine).

Hardware interrupts: This interrupt is caused by sending a signal on one of the interrupt pins of
the microprocessor. An external device initiates the hardware interrupts and placing an
appropriate signal at the interrupt pin of the processor. If the interrupt is accepted then the
process or executes an interrupt service routine (ISR). Hardware interrupt is Asynchronous(it
can occur at any time). The 8085 has five hardware interrupts (1)TRAP (2)RST7.5 (3)RST6.5
(4)RST5.5 (5)INTR(address is supplied externally). The hardware interrupts are classified Two
types:

i. Maskable Interrupts
ii. Non-Maskable Interrupts

60
Maskable interrupts: An interrupt which can be disabled by software that means we can disable
the interrupt by sending appropriate instruction, is called a maskable interrupt. RST 7.5, RST 6,
RST 5.5 , INT R are the example of Maskable Interrupt.

Non-Maskable interrupts: Cannot disable the interrupt by sending any instruction is called Non
Maskable Interrupt. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an
interrupt comes via TRAP, 8085 will have to recognize the interrupt we cannot mask it.

Triggering levels: When a device interrupts, it actually wants the MP to give a service which is
equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service
Routine). This interrupts can be enable and disable by using EI (enable interrupt) & DI (disable
interrupt) instructions. The ‘EI’ instruction is a one byte instruction and is used to Enable the
non-maskable interrupts. The ‘DI’ instruction is a one byte instruction and is used to Disable the
non-maskable interrupts.

Enable Interrupt(EI) The interrupt process is enable by using EI instruction in the main
program. It is 1-byte instruction. It enables the interrupt process. Enabling will save the current
status and jumps to an interrupt service routine (ISR). After completion it will return back to the
main program again.

4.5. Accumulator Content for SIM

Disable Interrupt(DI) This DI instruction is used to disable the interrupt. It is 1-byte

instruction. This instruction reset the interrupt enable and disables the interrupt. Both EI & DI
are used to enable and disable the interrupts. If the interrupt is masked (disabled), they will not

61
be recognized by microprocessor. To enable It again they must be unmasked (enabled) by using
EI.

4.5. Interfacing Devices and I/O Devices

To communicate with the outside worls microcomputers use peripherals(I/O Devices).

Commonly used peripherals are

x A/D converter
x D/A converter
x CRT
x Printers
x Hard disks
x Floppy disks
x Magnetic tapes

Peripherals are connected to the microcomputer through the electronic circuits known as
interfacing circuits.

4.6 . Accumulator content after the execution of RIM

Some of the general purpose devices are:

i. I/O port
ii. Programmable Peripheral Interface(PPI)
iii. DMA controller
iv. Interrupt controller
v. Communication interface
vi. Programmable Counter/Interval Timer

62
Special purpose interfacing devices are designed to interface a particular type of I/O device to
the microprocessor. Examples of such devices are:

i. CRT controller
ii. Floppy Disk Controller
iii. Key Board and Display Interface.

4.5.1. Generation of control signals for memory and I/O devices

The Mp provides RD and WR signals to initiate read and write cycle. Because these signals
are used both for reading / writing memory or reading writing an input/output device, it is
necessary to generate separate read and write signals for memory and I/O devices. 8085 provides
IO/M signal to indicate that initiated cycle is for I/O device or for memory device. Using IO/M
signal along with RD and WR, it is possible to generate four signals shown below.

MEMR- Memory read

MEMW- Memory write

IOR- I/O read

IOW- I/O write

4.7. Control signals for Mmeory I/O Read/Write Operation

4.6. I/O Ports

An input device is connected to the microprocessor through an input port. An input port is a
place for unloading data. An input device unloads data into the port. The microprocessor reads
data from the input port. Similarly, an output device is connected to the microprocessor through
an output port. As the output port is connected to the output device , data transferred to the
output device.

63
 4.8. Interfacing of I/O device through I/O port

The Intel 8212 is an 8-bit nonprogrammable I/O port. It can be connected to the
microprocessor either as an input port or an output port. If we require one input port and one
output port, two units of 8212 will be required. One of them will be connected in input mode and
other in output mode.

(a) Input mode (b) Output

Mode
4.9. Interfacing of Intel 8212

64
 The SCL 6532 is a RAM, I/O, Interval Timer Device(RIOT) manufactured
semiconductor Complex LTD. It has an 8-bit bidirectional data bus, 12x8 state R two 8-
bit bidirectional data ports.
It operates with 1 MHz and 2 MHz clock and single supply +5V implemented in a 40-
pin IC. It has been designed to operate in conjunction with the SCL microprocessor
family. SCL 6502 is also manufactured by semiconductor Complex Ltd.

4.6.1. Programmable peripheral Interface (PPI).

A programmable peripheral interface is a multiport device. The ports may be

programmed in a variety of ways as required by the programmer. The device is very useful for
interfacing peripheral devices. The term IA, Peripheral Interface Adapter is also used by some
manufacturer.

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor. It consists of three 8-bit bidirectional
I/O ports i.e. PORT A, PORT B and PORT C. We can assign different ports as input or output
functions.

4.6.2. Architecture of Intel 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus.
Data is transmitted or received by the buffer as per the instructions by the CPU. Control words
and status information is also transferred using this bus.

4.10. Schematic Diagram of Intel 8255A

65
Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word.
It accepts the input from the CPU address and control buses, and in turn issues command to both
the control groups.

CS

It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are
connected to the microprocessor address lines.

WR

It stands for write. This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or control register.

RESET

This is an active high signal. It clears the control register and sets all ports in the input mode.

RD

It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1 ( Address pins )

These pins in conjunction with RD and WR pins control the selection of one of the 3 ports.
Group A and Group B controls receive control from the CPU and issues commands to their
respective ports.

Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3
modes – mode 0, mode 1, mode 2.

Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in
mode 0, mode1.

Port C : This has an 8 bit latched input buffer and 8 bit output latched/buffer. This port can be
divided into two 4 bit ports and can be used as control signals for port A and port B. it can be
programmed in mode 0.

66
Operating modes of 8255:

These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR). In
I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C
(PC0-PC7) can be used to set or reset its individual port bits.

Under the I/O mode of operation, further there are three modes of operation of 8255, so as to
support different types of applications, mode 0, mode 1 and mode 2.

Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode. This mode
provides simple input and output capabilities using each of the three ports. Data can be simply
read from and written to the input and output ports respectively, after appropriate initialization.

Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input and
output action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for
port B. This group which includes port B and PC0-PC2 is called as group B for Strobed data
input/output. Port C lines PC3-PC5 provide strobe lines for port A. This group including port A
and PC3-PC5 from group A. Thus port C is utilized for generating handshake signals.

Mode 2 ( Strobed bidirectional I/O ): This mode of operation of 8255 is also called as strobed
bidirectional I/O. This mode of operation provides 8255 with an additional features for
communicating with a peripheral device on an 8-bit data bus. Handshaking signals are provided
to maintain proper data flow and synchronization between the data transmitter and receiver. The
interrupt generation and other functions are similar to mode 1.

4.7. Programmable counter/ Interval Timer

The programmable Interval Timers are specially designed by Intel called as 8253 and 8254
constructed for microprocessors to perform timing and counting functions by using three 16-bit
registers. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin is for “OUT” output. To
perform a counter, a 16-bit count is loaded in its register. On giving command, it begins to
decrease the count until it reaches 0, then it produces a pulse that can be used to interrupt the
CPU.

67
Intel 8253

4.11. Schematic Diagram Of Intel 8253

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions are Programming the modes of 8253/54, Loading
the count registers, Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memory
mapped I/O mode, these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS
is tied to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command
word, which specifies the counter to be used, its mode, and either a read or write operation.

68
MODE 0 Interrupt on terminal count:

In this mode, the output is initially low after the mode is set. The counter starts decrementing the
count value after the falling edge of the clock till the terminal count is reached. When the
terminal count is reached, the output goes high and remains high until the selected control word
register or the corresponding count register is reloaded. This high output may be used to interrupt
the processor. The GATE signal should be high for normal counting and When GATE goes low
counting is terminated.

MODE 1 Programmable one-shot :

The gate input is used as trigger input in this mode of operation. Normally the output remains
high. After the application of the trigger, the output goes low and remains low until the count
becomes zero.

MODE 2 Rate generator:

The output is normally high after initialization. If GATE goes high, the counter starts counting
down from the initial value. In this mode, if N is loaded as the count value, then, after N pulses,
the output becomes low only for one clock cycle. The count N is reloaded and again the output
becomes high and remains high for N clock pulses.

MODE 3 Square wave generator:

When the count N loaded is even, then for half of the count, the output remains high and for the
remaining half, it remains low. If the count N loaded is odd, then for (N+1)/2 pulses the output
remains high and for (N-1)/2 pulses it remains low. This procedure is repeated continuously
resulting in the generation of a square wave.

MODE 4 Software triggered strobe:

After the mode is set, the output goes high. On terminal count, the output goes low for one clock
cycle, and then it again goes high. The GATE input when low disables the counting and when
high, enables the counting. The difference between Mode 4 and Mode 2 is that in Mode 2, the
OUT pulses are generated continuously after every N clock pulses, but in Mode 4, the OUT
pulse is generated only once after N clock pulses.

MODE 5 Hardware triggered strobe

The output is initially high. The counter starts counting after the rising edge of the trigger input
(GATE). The output goes low for one clock period when the terminal count is reached. The
hardware circuit should trigger the GATE input to initiate the counting operation, thereby
generating the OUT pulse.

69
Review Questions

1. Explain what is (a) Memory Mapped I/O Scheme, (b) I/O Mapped I/O Scheme.
2. What are the various schemes of data transfer from CPU/memory to I/O devices and
vice-versa? Discuss interrupt driven data transfer scheme with suitable example.
3. Explain in detail about DMA data transfer scheme.
4. What is interrupt? Explain enabling, disabling and masking of interrupts.
5. Explain what is vectored input and device polling.
6. Explain in detail about hardware and software interrupts.
7. What are I/O ports? What are programmable and nonprogrammable ports?
8. Explain in detail about different operating modes of 8255.
9. Discuss how to determine the control word for 8255.
10. Explain about programmable counter in detail.
11. Discuss the various operating modes of 8253.
12. Define Memory mapped I/O.
13. What is an interrupt I/O?
14. What are the two categories of an interrupt?
15. What is the purpose of an interrupt enable?
16. What is the size of ports in 8255?

70
 UNIT-V MICROROCESSOR APPLICATIONS
5.1. Delay subroutines

A delay program is used to provide the desired delay in industrial control before issuing the
control signal by the microcomputer.. To generate delay a few registers of the microprocessor are
loaded with desired numbers and then decremented to zero. The delay time depends on the
numbers loaded in the registers.

5.1.1. Delay subroutine Using One Register

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FC00 06,10 MVI B,10H Get 10 in register B.

FC02 05 LOOP DXR B Decrement register B.

FC03 C2,02,FC JNZ LOOP Has the content of register B become

zero? No, jump to LOOP. Yes, proceed
ahead.

FC06 C9 RET

To generate very small delay only one register can be used. In the above program register B
has been loaded by 10H(16 decimal). Then the register B is decremented and program moves in
a loop till the content of register B becomes zero. After this program returns to the main
program. The delay time may be calculated as follows:

To calculate delay time it is examined that how many times each instruction of the above
program executed. Number of states required for the execution of each instruction are:

Instructions States

MVI B,10 7

DCR B 4

JNZ 7/10

RET 10

71
 The instruction JNZ takes 10 states when the content of register B is not zero and the program
jumps to the label LOOP. JNZ takes only 7 states when the content of register B has become
zero and the program proceeds further to execute RET instruction.

The instructions MVI B, 10H and RET are executed only once. The instruction DCR B is
executed 16 times. The instruction JNZ is executed 16 times, out of which 15 times the program
jumps to the label LOOP as the content of register B has not become zero, and takes 10 states
each time.

At last when the content of register B becomes zero, JNZ is executed and the program proceeds
further. The last execution of instruction JNZ takes only 7 states. The number of states required
for the execution of each instruction and how many times each instruction has been executed are
as follows:

Instruction How many times the instruction is executed States

MVI B, 10H 1 7X1
DCR B 16 4X16
JNZ 16 10X15+7X1
RET 1 10X1

Total states = 7x1+4x16+(10x15+7x1)+10x1

= 7+64+150+7+10

= 238

Time for one state for Intel 8085 is 320 ns

Delay time = 238x320x10-9 second

= 0.238x0.320 millisecond

= 0.07616 millisecond.

To generate maximum delay register B is loaded by FF(255 decimal). The maximum delay using
one register is

= 7x1+4x255+(10x254+7x1)+10x1

= 7+1020+2540+7+10

= 3584 states

72
 = 3584x320x10-9 second

= 1.11688 millisecond.

5.1.2 Delay subroutine Using Register Pair

Label Mnemonics Operands Comments

LXI D, FFFF Get FFFF in register pair D-E.
LOOP DCX D Decrement count.
MOV A,D Move content of register D to accumulator.
ORA E Check if D and E are zero.
JNZ LOOP If D-E is not zero, jump to LOOP.
RET Return to main program

States required for each instruction of the above program are:

Instruction States

LXI D 10

DCX D 6

MOV A, D 4

ORA E 4

JNZ 7/10

RET 10

If the count in register pair D-E is N the total number of states are:

States = 10+ N(6+4+4)+(N-1)x10+1x7+10

= 24N+17

Delay = (24N+17)x time for one state.

Maximum delay will occur when count N = FFFF hex

= 65,535 decimal.

Maximum delay = (24x65,535+17)x320x10-9 second

= 20.97664 millisecond.

73
5.1.3. Delay Subroutine Using TWO Registers

Memory Machine Labels Mnemonics Operands Comments

Address Codes
2400 06,10 MVI B,10 H Get desired number in
register B
2402 0E,78 LOOP I MVI C,78 H Get desired number in
register c
2405 0D LOOP II DCR C Decrement C
2406 C2,05,24 JNZ LOOP II Is C zero? No, go to
LOOP II. Yes, proceed
further.
2409 05 DCR B Decrement register B
240A C2,02,24 JNZ LOOP I Is B zero? No, go to
LOOP I. Yes, proceed
further.
240D C9 RET Return to main program

States for instructions are:

Instructions States

MVI 7

DCR 4

JNZ 7/10

RET 10

Total States = 7x1+7x16+4x120x16+10x(120-1)x16+7x16+4x16+10

x(16-1)+7x1+10x1

= 7+122+7680+19040+112+64+150+7+10

= 27182 states

Delay time = 27182x320x10-9 second= 8.6912 millisecond.

5.2. Interfacing of 7 segment Displays

An output device which is very common is, especially in the kit of 8085 microprocessor and
it is the Light Emitting Diode consisting of seven segments. Moreover, we have eight segments
in a LED display consisting of 7 segments which includes ‘.’, consisting of character 8 and

74
having a decimal point just next to it. We denote the segments as ‘a, b, c, d, e, f, g, and dp’ where
dp signifies ‘.’ which is the decimal point. Moreover, these are LEDs or together a series of Light
Emitting Diodes.

5.1. Schematic Diagram of 7- segment Display

In seven segment displays there are seven light emitting diodes as shown in the above figure.
Each LED can be controlled separately. To display a digit or letter the desired segments are
made ON as shown in the figure.

There are two types of 7-segment displays namely common-cathode type and common-anode
type. In a common-cathode type display all the 7 cathodes of LEDs are tied together to the
ground.

Vd.c.is applied to any segment, the corresponding diode emits light. Thus applying logic'1'i.e.,
positive logic to the desired segments, the desired letter or decimal number can be displayed. In a
common-anode type display all the 7 anodes are tied together and connected to +5 V supply. A
particular segment will emit light when 0 logic is applied to it.

75
 5.2. 7-Segment Representations of Digits and Letters

The seven-segment displays are not connected to 1/O ports directly. They are connected
through buffers or drivers/decoders.7446A,74L46,7447,74L47 and /4Ls47 are decoders/drivers
for common-anode type seven segment displays.7448,74LS48,7449 and 74LS49 are
decoders/drivers for common-cathode type seven segment displays.

76
 5.3. Common-Cathode 7-Segment Display

5.4. Common-Anode 7-Segment Display

5.2.1. FND 500 and FND 503

FND 500 and FND 503 are common-cathode 7-segment displays. The following figure
shows thepin diagram of FND 503.

77
 5.5. Pin Diagram of 74LS48, BCD to 7-Segment.

5.2.2. MAN 74A

MAN 74A is a common-cathode 7-segment display.The pin configuration of MAN 74 A is

shown in the following figure.

MAN 72: MAN 72 is a common-anode 7-segment display. If pin diagram of a 7-segment

display is not known,it can be checked using multimeter.Set multimeter for ohm
measurement.Connect its terminals to any two pins of the 7-segment display.Find correct pins by
trial and error.

Fig5.7 shows the interfacing of decoder/driver 74LS48 and 7-segment display MAN 74 A
with microprocessor.The program to display the decimal number is as follows: Example.Write a
program to display 5.

78
 5.6. Interfacing of 74LS48 and MAN 74A

Memory Machine Codes Mnemonics Operands Comments

Address

2400 3E, 98 MVI A, 98H Get control word

2402 D3, 03 OUT 03 Initializes I/O ports
2404 3E, 05 MVI A,05 Get 05 in accumulator
2406 D3, 01 OUT 01 Send 05 at port b
2408 76 HLT Stop

The control word 98H makes the port B an output port. Thr microprocessor outputs 05 at the
port B. The pins PB0 – PB3 of the port B are connected to the decoder/driver 74LS48. Thus the
binary bits corresponding to the decimal number 5 are applied to 74LS8 and it is displayed by
the 7-segment display.

79
 5.7. Interfacing of 7-Segment Displays

x Pins LT, RBO and RBI may not be used. In case the seven segment display is not
working properly, it may be tried with keeping LT, RBO and RBI high.
x If RBI, A, B, C and D are low and LT is high, no segment glows and RBO goes low.
x If RBO is kept open or made high and LT low, all segments glow.
x If inputs A, B, C and D correspond to the decimal number 10 or more, unknown figures
are displayed.

5.3. Frequency Measurement

To measure the frequency of a signal, the time period for half cycle is measured which is
inversely proportional to the frequency. A sinusoidal signal is converted to square wave using a
voltage comparator LM 311 or operational amplifier LM 747 or LM 324 is shown in the
following figure. A diode is used to rectify the output signal. A potential divider is used to
reduce the magnitude to 5 volts.

80
 5.8. Schematic Diagram of interface for Reactance Relay.

A program has been developed to sense the zero instant of the rectified square wave. The
microprocessor measures the magnitude of the square wave at two consecutive points as shown
in the following figure. The two magnitudes are compared and decision is taken on the basis of
carry and zero status flags, whether the point is zero instant.

Various points are shown in the figure. Very near to P3 at its left side the magnitude of square
wave is zero, and at P4, 5V, at logic ‘1’. The microprocessor subtracts the first value from the
2nd, so the result is non-zero and there is no carry. This is the basis for the selection of zero
instant point supposes the microprocessor takes reading at P1 and P2 where both magnitudes are
zero.

81
 5.9. Rectified Square Wave

As soon as the zero instant point is detected the microprocessor initiates a register pair to count
the number how many times the loop is executed. The microprocessor reads the magnitude of the
square wave again and again, and moves in the loop.

5.10. Interface for frequency Measurement

It crosses the loop when the magnitude of the square waves becomes zero. Thus the time for
half cycle is measured. The count can be compared with the stored numbers in a look-up table
and the frequency can be displayed.

82
Frequency measurement using SID line:

The sinusoidal wave is converted into square wave using Op.am. The output is reduced to 5V
and applied to SID line of a microprocessor. The execution of RIM instruction reads the status of
SID line and stores it in the 7th bit of the accumulator. It also reads status of interrupt masks and
stores them in other bits of the accumulator. A program to measure the frequency is given
below.

Memory Machine Label Mnemonics Operands Comments

Address codes
2400 20 LOOP RIM Read frequency signal
2401 E6, 80 ANI 80 7th bit of the accumulator is
retained.
2403 4F MOV C,A Read frequency signal again.
2404 20 RIM
2405 E6, 80 ANI 80
2407 B9 CMP C . Compare with previous value.
2408 CA,00,24 JZ LOOP Detect low to high transition.
240B DA,00,24 JC LOOP
240E 21,00,00 LXI H,0000 Initialize H-L pair to count
frequency
2411 23 COUNT INX H Count frequency
2412 20 RIM Read frequency of signal.
2413 17 RAL
2414 DA,0F,24 JC COUNT Is frequency signal high? Yes, go
to the count.
2417 76 HLT

5.4. Temperature Measurement

For the measurement of temperature one of the following devices are used:

x Resistance thermometers( -100 to + 3000 C)

x Thermocouples (-250 to +20000 C)
x Thermistors (-100 to +1000 C)
x Pyrometers (+100 to +50000 C)

Platinum wires are frequently used in resistance thermometers for industrial application because
of greater resolution, and mechanical and electrical stability as compared to copper or nickel
wires.

83
 A change in temperature causes a change in resistance. The resistance thermometer is laced
in an arm of a Wheatstone bridge to get a voltage proportional to temperature.

5.11. Schematic Diagram of Interface for physical Quantity Measurement

A thermistor is a semiconductor device fabricated from a sintered mixture of metal alloys,

having a large negative temperature coefficient. A thermistor is used in a wheatstone bridge to
get a voltage proportional to temperature. It can be used in the range of -100 to +1000 C for
greater accuracy as compared to platinum resistance thermometer.

Microprocessor-Based Scheme: The output of a thermocouple proportional to the temperature

of the furnace or oven etc. is in millivolt. It is to be amplified using multistage amplifier before it
is processed by microprocessor.

The amplified voltage is applied to an A/D converter. The microprocessor sends a start of
conversion signal to the A/D converter through the port of 8255PPI. When A/D converter
completes conversion, it sends an end of conversional signal to microprocessor.

84
 5.12. Microprocessor based scheme for Temperature Measurement

The microprocessor displays the measured temperature. If the temperature of a furnace, oven
or water-bath is to be controlled, the microprocessor first measures its temperature, and then
compares the measured temperature with a reference temperature at which the temperature is to
be maintained.

If the measured temperature is higher than the reference temperature, microprocessor sends
control signal to reduce temperature. If the measured temperature is less than the reference
temperature, the microprocessor sends a control signal to increase temperature.

The temperature of a furnace or oven can be increased or decreased by increasing or decreasing

the fuel input to the furnace. If heating is done by electric heaters, current in heating element is
controlled.

85
 5.13. Three stage Amplifier and D.C. Level Detector

5.5. Water Level Indicator

The water level Controller is a reliable circuit, it takes over the task of indicating and
controlling the water level in the overhead water tanks. The level of the water is displayed in the
LED Bar graph. The Copper probes are used to sense the water level. The probes are inserted
into the water tank which is to be monitored.

This water-level Controller-cum-alarm circuit is configured around the well-known 8 bit

Microprocessor 8085. It continuously monitors the overhead water level and display it and it also
switch Off the Motor when the tank fills and it will automatically switch On the Motor when the
water level is low.

The Microprocessor will also indicate the water level over the LED display. All the input and
output functions are done through the Programmable Peripheral Interface IC 8255.

The output of the inverter are connected to the port A of 8255. In the interface only six probes
have been used. The 6 output points of the inverter are connected to 6 pins of Port A. The
remaining 2 pins of Port A are grounded. The 2nd unit of 8255, i.e., 8255.2 has been used for this
purpose.

86
 5.14. Microprocessor Based water Level Indicator and Automatic pumping

The microprocessor reads the binary logic corresponding to water level from the port, and
displays it on 7-segment displays which are connected to port B. The values of water levels at
which probes are placed in the tank are stored in the memory in the form of look-up table.

The microprocessor counts how many probes are immersed in water and determines the LSB of
the memory address of look-u p table. Suppose 1st and 2nd and 3rd robes are immersed in water.
These robes are at logic 1. The microprocessor counts that 3 robes are immersed in water and it
picks up the water level corresponding to memory location FD03 which is 30cm.

Automatic pumping

Automatic pumping can be done on the basis of water level in the tank. The program given
below has been developed to switch on a pump when water level is 20cm or less than 20cms.
The pump is switched off when water level reaches 60 cms.

Memory Machine Labels Mnemonics Operands Comments

Address Codes
FBFD 31,00,FE LXI SP,FE00 Initialize stack pointer
FC00 3E,98 MVI A,98H Initialize I/O ports of 8255
FC02 D3,OB OUT 0B
FC04 26,FD MVI H,FD MSBs of memory address for
look-up table.
FC06 06,00 LOOP MVI B,00 No .of probes immersed in
water, initial value=00.
FC08 0E,08 MVI C,08 No. of counts
FC0A DB,08 IN 08 Read water level.
FC0C 17 READ RAL

87
FC0D D2,11,FC JNC LOOK
FC10 04 INR B
FC11 0D LOOP DCR C
FC12 C2,0C,FC JNZ READ
FC15 68 MOV L,B LSBs of memory address for
look-up table.
FC16 7E MOV A,M
FC17 D3,09 OUT 09 Display water level.
FC19 CD,40,FC CALL DELAY
FC1C FE,20 CPI 20
FC1E D2,27,FC JNC GO Yes; jump to Go
FC21 F5 PUSH PSW Save water level reading which
is in ACC.
FC22 3E,01 MVI A,01
FC24 D3,0A OUT 0A
FC26 F1 POP PSW
FC27 FE,60 CPI 60
FC29 DA,06,FC JC L00P Yes; jump to LOOP
FC2C 3E,00 MVI A,00 NO; switch off pump
FC2E D3,0A OUT OA
FC30 C3,06,FC JMP LOOP

5.6. Microprocessor-Based Traffic control

All ports of 8255 have been programmed as output ports. The control word to make all ports
output ports for Mode 0 operation is 80H. The connection of pins of the ports to LED have been
made through buffers(7407).

Positive logic has been used to switch on LEDs. Three types of LEDs have been used red,
yellow and green. Green light glows to allow crossing, yellow to make alert, and red does not
allow crossing. The following figure shows a simple arrangement and port connections for
microprocessor-based traffic control.

88
 5.15. Traffic Light Control

Green light for right turns have not been shown. One can add some more LEDs for this
purpose, connect them to ports and make additions to the program.

Memory Machine Labels Mnemonics Operands Comments

Address Codes
FC00 3E,80 MVI A,80H Get control word for 825
FC02 D3,0B OUT 0B Initialize ports of 8255.2.
FC04 3E,01 LOOP MVI A,01
FC06 D3,09 OUT 09 Red ON for south
FC08 D3,08 OUT 08 Red ON for north
FC0A 3E,44 MVI A,44 Green ON for east and
west
FC0C D3,0A OUT 0A
FC0E CD,00,FD CALL DELAY I
FC11 3E,22 MVI A,22 Yellow ON for east and
west.
FC13 D3,0A OUT 0A

89
FC15 3E,02 MVI A,02
FC17 D3,09 OUT 09 Yellow ON for south.
FC19 D3,08 OUT 08 Yellow ON for north
FC1B CD,13,FD CALL DELAY
II
FC1E 3E,11 MVI A,11
FC20 D3,0A OUT 0A Red ON east and west
FC22 3E,04 MVI A,04
FC24 D3,09 OUT 08 Green for north
FC26 CD,00,FD OUT 09 Green for south
FC28 3E,22 CALL DELAY I
FC2B D3,0A MVI A,22
FC2D 3E,02 OUT 0A
FC2F D3,09 MVI A,02
FC31 D3,08 OUT 09 Yellow ON for south
FC33 CD,13,FD OUT 08 Yellow ON for north
FC35 C3,04,FC CALL DELAY
II
FC38 JMP LOOP

DELAY I

FD00 06,20 MVI B,20

FD02 0E,FF G03 MVI C,FF
FD04 16,FF G02 MVI D,FF
FD06 15 G01 DCR D
FD07 C2,06,FD JNZ G01
FD0A 0D DCR C
FD0B C2,04,FD JNZ G02
FD0E 05 DCR B
FD0F C2,02,FD JNZ G03
FD12 C9 RET

DELAY II

FD13 06,10 MVI B,10

FD15 C3,02,FD JMP FD02 G03

90
Review Questions

1. What is a 7-segmnet LED Display? Discuss its applications.

2. Explain about common cathode type and common anode type 7-segment displays.
3. Show interface connections for a microprocessor based scheme for traffic control.
4. Show with a neat sketch and suitable interface of a microprocessor-based scheme to
measure, display and control water level.
5. Explain about frequency measurement in a microprocessor based system.
6. Discuss about a microprocessor based scheme to measure and control temperature.

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