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TG Lecture

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28 views11 pages

TG Lecture

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ubhatt
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EEC 116 Lecture:

Transmission Gate Logic

Rajeevan Amirtharajah
University of California, Davis

Jeff Parkhurst
Intel Corporation
Transmission Gate Logic

= =

• NMOS and PMOS connected in parallel


• Allows full rail transition – ratioless logic
• Equivalent resistance relatively constant during
transition
• Complementary signals required for gates
• Some gates can be efficiently implemented using
transmission gate logic (XOR in particular)

Amirtharajah/Parkhurst, EEC 116 Fall 2011 2


Equivalent Transmission Gate Resistance

0V

Vout = 0V @ t=0
Vin

VDD

• For a rising transition at the output (step input)


– NMOS sat, PMOS sat until output reaches |VTP|
– NMOS sat, PMOS lin until output reaches VDD-VTN
– NMOS off, PMOS lin for the final VDD – VTN to VDD
voltage swing
Amirtharajah/Parkhurst, EEC 116 Fall 2011 3
Equivalent Resistance

• Equivalent
resistance Req is Req,n
parallel combinaton
Req,p
of Req,n and Req,p
R
• Req is relatively
constant
Req

VTp VDD-VTn VDD


Vout

Amirtharajah/Parkhurst, EEC 116 Fall 2011 4


Resistance Approximations
• To estimate equivalent resistance:
– Assume both transistors in linear region
– Ignore body effect
– Assume voltage difference (VDS) is small

1 1
Req ,n ≈ Req , p ≈
k n (VDD − Vtn ) (
k p VDD − Vtp )
1
Req ≈
(
k n (VDD − Vtn ) + k p VDD − Vtp )
Amirtharajah/Parkhurst, EEC 116 Fall 2011 5
Equivalent Resistance – Region 1
• NMOS saturation:

Req ,n =
(VDD − Vout )
k n (VDD − Vout − Vtn )
1 2
2

(VDD − Vout )
• PMOS saturation:
Req , p =
k p (− VDD − Vtp )
1 2
2

Amirtharajah/Parkhurst, EEC 116 Fall 2011 6


Equivalent Resistance – Region 2
• NMOS saturation:

Req ,n =
(VDD − Vout )
k n (VDD − Vout − Vtn )
1 2
2

• PMOS linear:
2(VDD − Vout )
=
Req , p
(
k p 2(VDD − VTP )(VDD − Vout ) − (VDD − Vout )
2
)
2
=
k p [2(VDD − VTP ) − (VDD − Vout )]

Amirtharajah/Parkhurst, EEC 116 Fall 2011 7


Equivalent Resistance – Region 3
• NMOS cut off:
Req ,n = ∞

• PMOS linear:
2
Req , p =
k p [2(VDD − VTP ) − (VDD − Vout )]

Amirtharajah/Parkhurst, EEC 116 Fall 2011 8


Transmission Gate Logic
• Useful for multiplexers (select between multiple
inputs) and XORs
• Transmission gate implements logic function F =
A if S
– If S is 0, output is floating, which should be
avoided
– Always make sure one path is conducting from
input to output
• Only two transmission gates needed to
implement AS + AS
– Transmission Gate 1: A if S
– Transmission Gate 2: A if S
Amirtharajah/Parkhurst, EEC 116 Fall 2011 9
Transmission Gate XOR

S
S

A F = A⊕ S

S
S
• If S = 0, F = A and when S = 1, F = ~A
Amirtharajah/Parkhurst, EEC 116 Fall 2011 10
Transmission Gate Multiplexer

F = AS + BS
A

S
Amirtharajah/Parkhurst, EEC 116 Fall 2011 11

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