Analog and Mixed-Signal Center, TAMU

Sample-and-Hold Circuit

S/H:

S t

Vi

S/H circuit

Vo

Vo S/H command Vi

Block Diagram

Idealized Response

Performances of S & H
Realistic Transient Response:
Input & Output Voltage Vin Voltage Drift Vout t CK ta th t Track Error

Pedestal

S/H Circuit Waveforms and Performance Parameters

H S H Vi Vi Vo Droop Vo

Vi tap ts

Hold step

Feedthrough

Desired output

Vo

Droop

tac

Design of Track and hold

Performance Definition
Acquisition Time: the required time for the output transient after the sampling signal. Hold Settling Time: the time after the hold signal required for the output to settle within an acceptable error. Pedestal Error: due to the transition of sample to hold mode. Voltage Drift: the rate of discharge of the sampling capacitor during the hold mode. Dynamic Range: the ratio of the maximum and minimum input level, which can be sampled with a given resolution.

Performance Definition
Nonlinearity Error: the maximum deviation of the Vout/Vin characteristic from the straight line passed through the end points.

Gain Error: the deviation of the slope of the straight line from unity.
Vout Nonlinearity Error 1

G Gain Error= 1 - G

P 0 0 Vin
Analog and Mixed-Signal Center, TAMU

Track and hold

Performance Definition
Hold Mode Feedthrough: the percentage of the input signal that appears at the output during the hold mode.

Parasitic capacitors S

CK

Cp Vin CS Vout

Performance Definition
Aperture Error: the random variation of the turn off time of the switch results in an uncertain sampling time. Maximum Allowable Aperture Error for 1/2 LSB:
10nsec 1nsec
t ts b bi s t t 6 6 b ts bi ts 8 8 b t bii ts b bii
f

t max =

1 N +1 f in 2
Ideal sampling point

Vin

Sampling Error t

100psec 10psec

1MHz 10MHz 100MHz 1GHz

10 10 12 12

Aperture Error CK fin t

Performance Definition Performance Definition

Signal-to-Noise Ratio (SNR): the ration of the signal power to the noise power at the output. The sources of noise are the input and output buffer, switch, and clock jitter. Signal to Noise + Distortion Ratio (SNDR): the ration of signal power to the total noise and harmonic power at the output. The source of harmonics are the nonlinearity of the buffers and the switch. CK

* nBin
Vin

nsw *

* nBout
Vout

f clk

Sample-and-Hold Basic Architectures

V

Vin

Q1 Chld

Vout

Analysis QCH COX WLVeff 1 QC = = hld 2 2 where Veff 1 is given by Veff 1 = VGS1 Vtn = VDD Vtn Vin
V = QC hld
COX WLVeff 1 = 2Chld

Fig. 1 An open-loop track and hold realized using MOS technology. f clk

Vin

Q1

C hld

COXWL (VDD Vtn Vin ) 2Chld

Vout

Chld
f clk Fig. 2 An open-loop track and hold realized using a CMOS transmission gate.

COX WLOV (VDD VSS ) Chld

Input Buffer 1

CK X S

f clk

f clk

Vin

Q1

Q2

.. .

Vin
1

Vout

. C .

Output Buffer 1

Vout

Chld
Fig. 3 An open-loop track and hold realized using an n-channel switch along with a dummy switch for clock-feedthrough cancellation.

Analog and Mixed-Signal Center, TAMU

Buffered Sample & Hold Circuit

Input and Output Buffer: The capacitor voltage during the hold mode can be affected by the current drawn by the following circuit. Therefore, the output voltage is buffered.

CK Bin Vin S Bout Vout

Analog and Mixed-Signal Center, TAMU

Unity Gain Buffer Circuit: BJT and CMOS implementations

Bipolar Technology
Vcc Rc Q3 Vin Q1 Q2 Vout IF Vin M1 M2 Vout IF M3

CMOS Technology
VDD M4

IEE

ISS

Track & Hold (T&H) Circuit

Simple Closed-Loop Architecture:
During the sampling time, the drain and source voltage of MOS switch are closed to ground. Thus the charge injection and clock feedthrough introduce an offset voltage at the output and is independent of the input voltage.

CK Gm
V1

Vin

V-

Vout

Disadvantage: stability problems and low speed.

T&H Circuit: Closed-Loop Architecture

Offset Voltage Cancellation:
The charge injection and clock feedthrough can be cancel out by applying a replica of the offset voltage to the positive terminal of the second amplifier (common-mode voltage).

CK
+

Cs M1
V+

Vin

Gm

V1

Vout

CK

M2

T&H Circuit: Switched Capacitor

Switched-Capacitor Architecture:
This architecture consists of sampling capacitor CS, amplifier Gm, and MOS switches.
CK M3 CK CK M1 + M2 CS Gm Vout + Vin CS +

Gm Vout

Track Mode (CK=1)

CS Vin Gm Vout

Vin

Hold Mode (CK=0)

Evolution of S/H Architectures

CK
+

CH
X

Vin

Gm

.
Vout Vin
+

clk

A0

Q1 Chld

Vout

Fig A. Closed-loop sample-and-hold architecture.

clk

Fig B. Including an opamp in a feedback loop of a sample and hold to increase the input impedance.
clk

Q3
clk clk

Opamp 1 +

Chld Q1

Q2 Vin
+

Q1

.
Chld

.
Vout

Vin

.
Vout

+ Opamp 2

clk

Q2

C. Adding on additional switch to the S/H of Fig B to minimize slewing time.

Fig D An improved configuration for an S/H as compared to that of Fig C

Design of Track and hold

T&H Circuit: Current-Mode

Current-Mode Architecture:
Advantages: high-speed (over 100MHz) and low voltage (<1.2). The speed depends on the time constant given by:
VDD I Iin AI Iout CK Iin M2 CS Iout

CS g m1
=

CS

CK
M1

2 C ox (1 + A) W1 L1 3 W ( VGS VTn ) L

g m1

= C ox

Two Op Amps S/H Circuit

RF

D1 A1 + Vi +

D2 SW

A2 + + Vo
-

CH

S/H

Switch driver

VCC R1 Vi + 2k R3 20 S Cds D - A 3 LT118A + + A4 LT118A R8 CH 1nF 5k C5 10pF R9 D2 6.2V

+ A 1 LT118A -

A1 LT11010 R2 2k C2 D1

Q1
2N5432

+ Vo
-

C1 50pF

G R7 2k

Cgd

C3 100pF

R10

R5 150pF Q3 S/H + 1k 2N2907

HP2810 R6 1k

10k 50k R11 6.2k

Q2 2N2222

R7 200k

VEE

A 5 MHz track-and-hold circuit, using discrete components, with charge compensation to minimize the hold step.

ts1 actual Vin

f clk

ts1 ideal

ts 2 ideal ts 2 actual

Sampling jitter

Fig. The clock waveforms for V in and clk used to illustrate how a finite slope for the sampling clock introduces sampling-time jitter.

CK + Gm M1 X M2

CH

Vin

CK

. .

.
Vout

A0 + C2

Fig. Closed-loop sample-and-hold architecture with pedestal cancellation.

S/H Open Loop Architecture with Miller Capacitance

CK Vin Y. M1 M2
A0 +

.
C1

Vout

Vin X

.
A0 +

Vout

.Z

Y.

C1

.Z

C2

(a)
-

Vout X C1

C2

(b)

A0 +

.Z

C2 (c)
Fig. Open-loop architecture with Miller capacitance. (a) Basic circuit; (b) equivalent circuit in the acquisition mode; (c) equivalent circuit in the hold mode. The open-loop architecture with Miller capacitance employs two different values of capacitance in the acquisition and hold modes to achieve high speed and small pedestal error. This is accomplished using a Miller amplifier that multiplies the effective value of the sampling capacitor by a large number when the SHA enters the hold mode.

Switched-Capacitor S/H Implementations

1 2

vin

C1
1

. .

C2 +

. .

vout

A switched-capacitor sample and hole and low-pass filter.

2A 1A

S4 CS

vin

S1
1B

.
S2

2B

1B

.
S3

S5

.. .
CX 1

CH

. .
S6

Vout

2S

COF

1B

S7

A switched-capacitor S/H.

MULTIPLEXED-INPUT ARCHITECTURES
Vin Gm1 CK Gm2 CK (a)

. .
CH

R2 Vout R1 Vin

+-

Gm1
-+

+-

R
-+

.
C1 X Y

Vout

CK
-+

Gm2
+-

. .

S1

S2

CK C2 A Rout X CH Vout

Fig. 15(a) Dual-loop multiplexed architecture.

Multiplexed-input architecture. (a) Basic (single-ended) circuit; (b) equivalent circuit in the hold mode.
R2 R1 Vin
+-

R
+-

+-

Gm1
-+

R
-+

.
C1 C2

-+

.
C1 X Y C2

Vout

Vout
-+

Gm1

+-

(b)

(c)

Equivalent circuits of dual-loop multiplexed-input architecture. (b) Acquisition mode; (c) hold mode.

T&H Circuit: Current-Mode

Closed-Loop Current-Mode Architecture:
This architecture needs stability and speed considerations. The distortion of Gm2 affects directly the output current [21].

CK + -

Cs
M1 V+

Gm1
Iin

+ -

Gm2

Iout

CC

T&H Circuit: Example

BiCMOS Track & Hold Amplifier (12-Bit & 50Msps):
This circuit consists of input buffer, hold section, and output buffer [3].
Vcc VBB1 VBB2 M1 M2 Q5 Vin Q10 Q2 CS Q6 Q4 CK (Hold) Q13 R3 Q14 R4 R5 Q15 Q7 Q8 M3 M4 D1 Q9 Vout

CS=3pF CFF is a feedforward compensation capacitor for the charge injection of Q 4

Q1

VBB3 Q11 GND R1

CFF Q12 R2

Q3 CK (Track)

RECYCLING S/H ARCHITECTURE

S1 Vin

B1 X1 C1

. .

S5

S3 S4

B2 Y1 C2

. .

Vout

Vin B1 X1 C1

Vout

Vout B1 X1 C1 B2 Y1 C2 Gm + C3

B2 Y1 C2

..

Gm + C3

..
(a)

Gm + C3

S2

(b)

Fig. 16 Recycling architecture.

Fig. 17 Equivalent circuits of recycling architecture. (a) Sampling mode; (b) hold mode.

Integratating Amplifier S/H Circuit

VCC

Offset

Vi

+ A1 -

SW

CH

Cgd

A2 + + Vo
-

S/H SW driver

Improved S/H Circuit

SW3 R R

Vi

Buffer

SW1

CH

+ S/H SW driver SW2 C(=CH) + Vo

-

L.Dai and R. Harjani, CMOS Switched-Op-Amp Based Sample and Hold Circuit,IEEE JSSC, January 2000, pp 109-113

Charge injection and clock feedthrough mechanism

ON OFF Cgd
q

R vi

Cgs

+1

+ -

M1

Ch

vo

Q ch
'

= WLC ox (VGS

VT )

V =

k Q ch Ch

kWLC ox (VGS Ch VSS )C para

+

VT )

V =

''

( VDD

C para

Ch

Channel charge in (top) triode and (bottom) saturation

S G D VG S G D

VG

Vin

SOP +

A Ch

+1

Vout

Switched-Op-Amp-Based S/H Circuit

Vdd=5V Ib=5u M1 4/2 +1 Ch1=1p Vout+

+ Vin+ -

1m Gm S1

R1=100k

R2=100k + VinGm 1m

S2 M2 4/2

Ch2=1p +1 Vout-

Ib=5u Vdd=5V

Simplified model of the pseudo-differential SOP-based S/H

Folded cascode switched op-amp in the unity-gain feedback configuration

Vdd clk pbias M19 M5 M1 M3 M6 M8 M2 ncas nbias M7 clk Vin 3 M10 M11 2 M13 M17 Ch Vbuf M18 clk M15 M14 Vout

M4

pcas

M9

M16 M12 clk

VNerr VPerr

C Npara Ch Ch
+

C Npara C Ppara

VN GS VPGS

C Ppara
+

Simulation results for a complete cycle of sampledand-held waveform

Differential Input / Output (V) PSD of Input (dB/Hz)

Simulation results of the spectrum of the sampledand-held waveform

Time(us)

Frequency (kHz)

References
[1] U.L. McCreary and P.R. Gray, All-MOS charge redistribution analog-to-digital conversion techniques, IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975. [2] P. Van Peteghem and W. Sanaen, Single versus complementary switches: A discussion of clock feedthrough in SC circuits, in Proc. 12th Eur. Solid-State Circuits Conf. (ESSCIRC 86), Delft, the Netherlands, Sept. 1986, pp. 16-18. [3] C. Eichenberger and W. Guggenbuhl, Dummy transistor compensation of analog MOS switches, IEEE J. Solid-State Circuits, vol. 24, pp. 1143-1146, Aug. 1991. [4] M. Nayebi and B.A. Wooley, A 10-bit video BiCMOS track-and-hold amplifier, IEEE J. Solid-State Circuits, vol. 24, pp. 1507-1516, Dec. 1989. [5] P.J. Lim and B.A. Wooley, A high-speed sample-and-hold technique using a miller hold capacitance, IEEE Solid-State Circuits, vol. 26, pp. 643-651, Apr. 1991. [6] G.C. Temes, Y. Huang, and P.F. Ferguson Jr., A high-frequency track-and-hold stage with offset and gain compensation, IEEE Trans. Circuits Syst. II, vol. 42, pp. 559-560. Aug. 1995. [7] S. Brigati, F. Maloberti, and G. Torelli, A CMOS sample and hold for high-speed ADCs, in Proc. IEEE Int. Symp. Circuits and Systems Circuits and Systems Connecting the World, vol. 1, May 1996, pp. 163-166. [8] J.H. Shieh, M. Patil, and B.J. Sheu, Measurement and analysis of charge injection in MOS switches, IEEE J. Solid-State Circuits, vol. SC-22, pp. 277-281, Apr. 1986. [9] G. Wegman, E.A. Vittoz, and F. Rahali, Charge injection in analog MOS switches, IEEE J. Solid-State Circuits, vol. SC-22, pp. 1091-1097, Dec. 1987. [10] D. Jons and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [11] J. Crols and M. Steyaert, Switched-opamp: An approach to realize full CMOS switchedcapacitor circuits at very low power supply voltages, IEEE J. Solid-State Circuits, vol. 29, no. 8, Aug. 1994.