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North South University

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6 views1 page

North South University

Uploaded by

Farhan Labib
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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North South University

Department of Computer Science & Engineering

Quiz 2: Spring, 2022, Date: Mar 14, 2022.


EEE413/CSE 413 / ETE 419 - Verilog HDL: Modeling, Simulation and Synthesis.

Answer Question 1, 2 and any one from 3, 4 (10 points each):

1. a) In brief (any four) i) Module ii) Instance iii) Design Block or Design Under Test (DUT) iv)
Stimulus Block or Test bench v) Design Hierarchy In Brief with one example (any 5)
b) A Host Bus Adapter (HBA) contains the following components, a shared memory (RAM), a
processor interface (PIF) and a DMA Controller (DMACTL).

i)Define the modules RAM, PIF and DMACTL, using module/endmodule keywords. You
don’t need to define the internals. Assume that the modules have no terminal lists.
ii) Define the module HBA, using module/endmodule keywords. Instantiate the module
RAM, PIF and DMACTL and call the instances ram1, pif1 and dmactl1 respectively.
You do not need to define the internals. Assume that the module HBA has no terminals.
iii) Define the Test Bench block (stimulus) block HBA_TB, using the module/endmodule
keywords. Instantiate the design block HBA and call the instance hba1. This is the final
step in building the simulation environment.
2. Any 5:
a) Arrays and Memories.
b) Integer and Parameter
c) Identifiers and Keyword
d) Net and Registers
e) Comment and Strings
f) Part Select and Bit select of Vector
g) X and Z Values
h) Scalar, Vector and Arrays

3. a) What are the two basic types of design methodologies? List the four levels of abstraction to
describe a module using Verilog HDL with brief description of each.
b) Describe decimal middle 4 digit of you ID as per following Verilog number specification:
i) 16 bit binary ii) 32 bit Hexadecimal iii) 16 bit Octal iv) 31 bit decimal

4. a) Verilog supports four values to model the functionality of real hardware. List those. Verilog
also supports eight strength levels to resolve conflicts between drivers of different strength in
digital ckt. List those strength levels of value level 0 and 1.
b)List of 3 from each with function and example
a) System Tasks ($)
b) Compiler Directives (`)
c) String format specification to display values of signals.

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