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Full10+cau3 09

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8 views8 pages

Full10+cau3 09

Uploaded by

pvduc30092003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Library IEEE; use

IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL; use
IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity FF_JK is
Port ( J,K,CLK,S,R: in STD_LOGIC;
Q,Qd : out STD_LOGIC);
End FF_JK;
Architecture BHV of FF_JK is signal
Qt,Qdt: std_logic;
signal jk : std_logic_vector(1 downto 0);
Begin
Process(J,K,Clk,S,R)
Begin
if (S='0') and (R='0') then
Qt <='1'; Qdt <='1';
elsif (S='0') and (R='1')
then
qt <='1'; qdt <='0';
elsif (S='1') and (R='0') then
Qt <='0';
Qdt <='1';
elsif (S='1') and (R='1') then
if Clk='0' and clk'event then
JK <= J & K;
case JK is
when "11" => Qt <=not Qt;
Qdt <=not Qdt;
when "10" => Qt <='1';
Qdt <='0';
when "01" => Qt <='0';
Qdt <='1';
when others => null; -- khong doi tt
end case;
end if;
end if;
end
process; Q
<= Qt; Qd
<= Qdt;
end Behav;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Binary_DownCounter_4bit is
Port (
Clk : in STD_LOGIC; -- Xung nhịp 1Hz
Clr : in STD_LOGIC; -- Tín hiệu xóa
PL : in STD_LOGIC; -- Tín hiệu nạp giá trị đặt trước
Data : in STD_LOGIC_VECTOR(3 downto 0); -- Giá trị đặt trước
Q : out STD_LOGIC_VECTOR(3 downto 0); -- Đầu ra bộ đếm
Seg : out STD_LOGIC_VECTOR(6 downto 0) -- Led 7 đoạn (Katode chung)
);
end Binary_DownCounter_4bit;

architecture Behavioral of Binary_DownCounter_4bit is


signal Count : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- Bộ đếm 4 bit
begin
process(Clk, Clr)
begin
if Clr = '0' then -- Xóa đầu ra về 0
Count <= "0000";
elsif rising_edge(Clk) then
if PL = '0' then -- Nạp giá trị đặt trước
Count <= Data;
elsif Count = "0000" then
Count <= "1111"; -- Đếm từ 0 về 15 (lặp lại)
else
Count <= Count - 1; -- Đếm xuống
end if;
end if;
end process;

Q <= Count; -- Đầu ra bộ đếm

-- Giải mã Led 7 đoạn Katode chung (hiển thị mã Hexa)


with Count select
Seg <= "0000001" when "0000", -- 0
"1001111" when "0001", -- 1
"0010010" when "0010", -- 2
"0000110" when "0011", -- 3
"1001100" when "0100", -- 4
"0100100" when "0101", -- 5
"0100000" when "0110", -- 6
"0001111" when "0111", -- 7
"0000000" when "1000", -- 8
"0000100" when "1001", -- 9
"0001000" when "1010", -- A
"1100000" when "1011", -- B
"0110001" when "1100", -- C
"1000010" when "1101", -- D
"0110000" when "1110", -- E
"0111000" when others; -- F
end Behavioral;
Thời Luồng Luồng
gian 1 2
Xanh Vàng 1 Đỏ1 Xanh Vàng 2 Do2 vector
1 2
0-26 0 0 1 1 0 0 001100
26- 0 0 1 0 1 0 001010
29
29- 1 0 0 0 0 1 100001
56
56- 0 1 0 0 0 1 010001
59
0-26 0 0 1 1 0 0 001100

Thời gian Luồng 1 Luồng 2

Xanh Vàng 1 Đỏ1 Đỏ 2 Vàng 2 Xanh 2 vector


1
0-53 0 0 1 1 0 0 001100
53-56 0 0 1 0 1 0 001010
56-110 1 0 0 0 0 1 100001
110-113 0 1 0 0 0 1 010001
0-53 0 0 1 1 0 0 001100

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity denGT is
Port (
Clk : in STD_LOGIC; -- Xung nhịp 50MHz
Sel : in STD_LOGIC_VECTOR(1 downto 0); -- Tín hiệu điều khiển
Led : out STD_LOGIC_VECTOR(5 downto 0) -- Đầu ra Led(0) đến Led(5)
);
end denGT
architecture Behavioral of denGT is
signal dent: STD_LOGIC_VECTOR (5 downto 0);
signal den: STD_LOGIC_VECTOR (5 downto 0);
signal qt: Integer range 0 to 59;
signal yt: Integer range 0 to 113;
begin process(clk,sel,qt,yt) begin if (CLK='1' and CLK'event)
then qt<=qt +1;
if qt = 59 then qt <= 0;
end if;
end if;
case qt is
when 0 to 26 => den <="001100";
when 26 to 29 => den <="001010 ";
when 29 to 56 => den <="100001";
when 56 to 59 => den <="010001";
when others => null;
end case;
if (CLK='1' and CLK'event) then yt <= yt + 1;
if yt = 113thenyt<= 0;
end if;
end if;
case yt is
when 0 to 53 => dent <="001100";
when 53 to 56 => dent <="001010 ";
when 56 to 110 => dent <="100001";
when 110 to 113 => dent <="010001";
when others => null;
end case;
case sel is
when “00” => led<= den;
when "01" => Led <= '0'&clk&"00"&clk&'0';
when "10" => Led <= den;
when "10" => Led <= dent;
when others => Led <= “000000”;
end case;
end process;
end Behavioral;

Thời Luồng Luồng


gian 1 2
Xanh Vàng 1 Đỏ1 Xanh Vàng 2 Do2 vecto
1 2 r
0-21 0 0 1 1 0 0 001100
21- 0 0 1 0 1 0 001010
24
24- 1 0 0 0 0 1 100001
46
46- 0 1 0 0 0 1 010001
49
0-21 0 0 1 1 0 0 001100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity denGT is
Port ( clk : in STD_LOGIC;
SL : in STD_LOGIC_VECTOR (1 downto 0);
Led : out STD_LOGIC_VECTOR (5 downto 0));
end denGT;
architecture BHV of denGT is
signal qt: Integer range 0 to 49;
signal dent: STD_LOGIC_VECTOR (5 downto 0));
begin
process(clk,sl,qt) begin
if (CLK='1' and CLK'event) then qt<=qt + 1;
if qt = 49 then qt <= 0;
end if;
end if;
case qt is
when 0 to 21 =>dent<="001100";
when 21 to 24 =>dent<="001010";
when 24 to 46=>dent<="100001";
when 46 to 49 =>dent<="010001";
when others => dent<="000000";
end case;
case sl is when "00" => Led <= '0'&clk&"00"&clk&'0';
when "01" => Led <= "100001";
when "10" => Led <= "001100";
when “11” => Led <= dent;
when others => Led <= “000000”;
end case;
end process;
end Behavioral;

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