ELC323: Microprocessor II

Dr. Abouelmaaty M. Aly

Agenda: Memory Interface – Chapter 10
 Introduction
 Memory devices
 Address Decoding
 8088 and 80188 (8-Bit) Memory Interface

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Memory Interface - Introduction

 Every microprocessor-based system, a simple or complex, has a memory system.

 The Intel family of microprocessors contains two main types of memory:
 Read - only memory (ROM) contains system software and permanent system data.
 Random access memory (RAM) or read/write memory contains temporary data and
application software.
 This chapter explains how to interface both memory types to the Intel family of microprocessors.
 We demonstrate memory interface to an 8-, 16-, 32-, and 64-bit data bus by using various memory
address sizes.
 This allows virtually any microprocessor to be interfaced to any memory system.

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Memory Interface – Memory devices

 Before attempting to interface memory to the microprocessor, it is essential to completely

understand the operation of memory components.
 In this section, we explain the functions of the four common types of memory:
• read-only memory (ROM),
• flash memory (EEPROM),
• static random access memory (SRAM), and
• dynamic random access memory (DRAM).

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Memory Interface – Memory devices (Memory Pin Connections)

 Pin connections common to all memory devices are the address inputs, data outputs or
input/outputs, some type of selection input, and at least one control input used to select a read or
write operation.
 See next Figure for ROM and RAM generic-memory devices.
 We have four different connections:
 Address Connections
 Data Connections
 Selection Connections
 Control Connections

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Memory Interface – Memory devices (Memory Pin Connections)

 Address Connections
 All memory devices have address inputs that select a memory location within the memory device.
 Address inputs are labeled from A0, the least significant address input, to An where subscript n can
be any value but is always labeled as one less than the total number of address pins.
 The number of address pins found on a memory device is determined by the number of memory
locations found within it.
 A 1K memory device has 10 address pins (A0 – A9); therefore, 10 address inputs are required to
select any of its 1024 memory locations.
 If a memory device has 11 address connections (A0 – A10), it has 2048 (2K) internal memory
locations, and so on.
 A device that contains 1M locations requires a 20 - bit address (A0 – A19).

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Memory Interface – Memory devices (Memory Pin Connections)

 Data Connections
 All memory devices have a set of data outputs or input/outputs.
The device illustrated in this Figure has a common set of
input/output (I/O) connections.
 Today, many memory devices have bidirectional common I/O pins.
 The data connections are the points at which data are entered for
storage or extracted for reading.
 Data pins on memory devices are labeled D0 through D7 for an 8-
bit-wide memory device.
 In this sample memory device there are 8 I/O connections,
meaning that the memory device stores 8 bits of data in each of its
memory locations.

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Memory Interface – Memory devices (Memory Pin Connections)

 Data Connections
 An 8-bit-wide memory device is often called a byte-wide memory.
 Although most devices are currently 8 bits wide, some devices are
16 bits, 4 bits, or just 1 bit wide.
 A memory device with 1K memory locations and 8 bits in each
location is often listed as a 1K × 8 by the manufacturer. A 16K × 1 is
a memory device containing 16K 1-bit memory locations.

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Memory Interface – Memory devices (Memory Pin Connections)

 Selection Connections
 Each memory device has an input, sometimes more than one, that
selects or enables the memory device.
 This type of input is most often called a chip select (CS), chip enable
(CE), or simply select (S) input.
 RAM memory generally has at least one CS or S input, and ROM has at
least one CE.
 If the CE, CS, or S input is active (logic 0), the memory device performs
a read or write operation; if it is inactive (logic 1), the memory device
cannot do a read or a write because it is turned off or disabled.
 If more than one CS connection is present, all must be activated to
read or write data.

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Memory Interface – Memory devices (Memory Pin Connections)

 Control Connections
 All memory devices have some form of control input or inputs.
 A ROM usually has only one control input, while a RAM often has
one or two control inputs.
 The control input most often found on a ROM is the output enable
(OE) or gate (G) connection, which allows data to flow out of the
output data pins of the ROM.
 If OE and the selection input (CE) are both active, the output is
enabled; if OE is inactive, the output is disabled at its high-
impedance state.

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Memory Interface – Memory devices (Memory Pin Connections)

 Control Connections
 RAM memory device has either one or two control inputs.
 If there is only one control input, it is often called R/W. This pin selects a
read operation or a write operation only if the device is selected by the
selection input (CS).
 If the RAM has two control inputs, they are usually labeled WE (Write
Enable), and OE (Output Enable). WE must be active to perform a memory
write, and OE must be active to perform a memory read operation.
 When these two controls (WE and OE) are present, they must never both
be active at the same time.
 If both control inputs are inactive (logic 1s), data are neither written nor
read, and the data connections are at their high-impedance state.

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 Memory Interface – Memory devices (ROM Memory)

 The read-only memory (ROM) permanently stores programs and data and must not change when
power supply is disconnected.
 This type of memory is often called nonvolatile memory.
 It programmed during its fabrication at the factory.
 The EPROM (erasable programmable read-only memory), a type of ROM, is more commonly used
when software must be changed often.
 An EPROM is programmed in the field on a device called an EPROM programmer.
 The EPROM is also erasable if exposed to high-intensity ultraviolet light for about 20 minutes.
 Newer type of ROM is called the flash memory, it is also often called an EEPROM (electrically erasable
programmable ROM).
 NOVRAM (nonvolatile RAM) is electrically erasable in the system, but they require more time to erase
than a normal RAM.

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 Memory Interface – Memory devices (ROM Memory)

 This Figure shows the 2716 EPROM, which is representative of most common EPROMs.
 This device contains 11 address inputs and eight data outputs. The 2716 is a 2K × 8 read-only memory
device.

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 Memory Interface – Memory devices (ROM Memory)

 This Figure shows the timing diagram for the 2716 EPROM.
 Note that, the memory access time (TACC) is measured from the appearance of the address at the
address inputs until the appearance of the data at the output connections.

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 Memory Interface – Memory devices (Static RAM Devices)

 Static RAM (SRAM) memory devices retain data for as long as DC power
is applied.
 The main difference between a ROM and a RAM is that a RAM is written
under normal operation, whereas a ROM is programmed outside the
computer and normally is only read.
 The SRAM, which stores temporary data, is used when the size of the
read/write memory is relatively small.
 This Figure shows the 4016 SRAM, which is a 2K × 8 read/write memory.
 This device has 11 address inputs and eight data input/output
connections.
 This device is representative of all SRAM devices, except for the number
of address and data connections.

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 Memory Interface – Memory devices (Dynamic RAM Memory)

 Dynamic RAM (DRAM) is available in much larger sizes than SRAM.

 DRAM is essentially the same as SRAM, except that it retains data for only 2 or 4ms on an integrated
capacitor.
 After 2 or 4ms, the contents of the DRAM must be completely rewritten (refreshed) because the
capacitors, which store a logic 1 or logic 0, lose their charges.
 Another disadvantage of DRAM memory is that it requires many address pins that the manufacturers
have decided to multiplex the address inputs.

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 Memory Interface – Memory devices (Dynamic RAM Memory)

 This Figure shows a 64K × 4 DRAM, which stores 256K bits of data.
 Notice that it contains only eight address inputs where it should
contain 16—the number required to address 64K memory locations.
 The only way that 16 address bits can be forced into eight address
pins is in two 8-bit increments.
 This operation requires two special pins: the column address strobe
(CAS) and row address strobe (RAS).
 First, A0 – A7 are placed on the address pins and strobed into an
internal row latch by RAS as the row address.
 Next, the address bits A8 - A15 are placed on the same eight address
inputs and strobed into an internal column latch by CAS as the
column address.

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 Memory Interface – Memory devices (Dynamic RAM Memory)

 This Figure shows a set of multiplexers used to strobe the

column and row addresses into the eight address pins on a pair
of DRAMs.
 Here, the RAS signal not only strobes the row address into the
DRAMs, but it also selects which part of the address is applied
to the address inputs.
 When RAS is a logic 1, the B inputs are connected to the Y
outputs of the multiplexers; when the RAS input goes to a logic
0, the A inputs connect to the Y outputs.

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 Memory Interface – Address Decoding

 To attach a memory device with the microprocessor, it is necessary decode the address sent from the
microprocessor.
 Without an address decoder, only one memory device can be connected to a microprocessor.
 In this section, we describe a few of the more common address-decoding techniques, as well as the
decoders that are found in many systems.

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 Memory Interface – Address Decoding

Why Decode Memory?

 When the 8088 microprocessor is compared to the 2716 EPROM, a difference in the number of
address connections is apparent — the EPROM has 11 address connections and the microprocessor
has 20.
 This means that the microprocessor sends out a 20-bit memory address whenever it reads or writes
data.
 Because the EPROM has only 11 address pins, there is a mismatch that must be corrected.
 If only 11 of the 8088’s address pins are connected to the memory, the 8088 will see only 2K bytes of
memory instead of the 1M bytes that it “expects” the memory to contain.
 The decoder corrects the mismatch by decoding the address pins that do not connect to the memory
component.

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 Memory Interface – Address Decoding

Simple NAND Gate Decoder

 When the 2K × 8 EPROM is used,
address connections A0 – A10 of the
8088 are connected to address inputs
A0 – A10 of the EPROM.
 The remaining nine address pins (A11 –
A19) are connected to the inputs of a
NAND gate decoder, see this Figure.

 The decoder selects the EPROM from one of the 2K-byte sections of the 1M-byte memory system in
the 8088 microprocessor.

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 Memory Interface – Address Decoding

Simple NAND Gate Decoder

 The output of the NAND gate is a logic
0 whenever the 8088 address pins
attached to its inputs (A11 – A19) are all
logic 1s.
 Logic 0 output of the NAND gate
decoder is connected to the input pin
that selects the EPROM.

 When CE is logic 0, data will be read from the EPROM only if OE (Output Enable) is also a logic 0.
 The OE pin is activated by the 8088 RD signal.

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 Memory Interface – Address Decoding

Simple NAND Gate Decoder

 If the 20-bit binary address, decoded by
the NAND gate, is written so that the
leftmost nine bits are 1s and the
rightmost 11 bits are don’t cares (X),
the actual address range of the EPROM
can be determined.
 A don’t care is a logic 1 or a logic 0,
whichever is appropriate.

 The next Example shows how the address range for this EPROM is determined.

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 Memory Interface – Address Decoding

Simple NAND Gate Decoder

Example:
1111 1111 1XXX XXXX XXXX
or
1111 1111 1000 0000 0000 = FF800H (Start)
to
1111 1111 1111 1111 1111 = FFFFFH (End)

 This Example also shows the 2K EPROM is decoded at memory address locations FF800H – FFFFFH.
 Although this example serves to illustrate decoding, NAND gates are rarely used to decode memory
because each memory device requires its own NAND gate decoder.
 Because of the excessive cost of the NAND gate decoder and inverters that are often required, this
option requires that an alternate be found.

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 Memory Interface – Address Decoding

The 3 – to - 8 Line Decoder (74LS138)

 This Figure shows this decoder and its truth table.
 The truth table shows that only one of the eight outputs is low at any time.
 For any of the decoder’s outputs is low, the three enable inputs (G2A, G2B, and G1) must all be
active.
 To be active, the
G2A and G2B
inputs must both
be low (logic 0),
and G1 must be
high (logic 1).

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 Memory Interface – Address Decoding

The 3 – to - 8 Line Decoder (74LS138)

 Once the 74LS138 is enabled, the address inputs (A, B, and C) select which output pin goes low.
 Imagine eight EPROM CE inputs connected to the eight outputs of the decoder!
 This is a very powerful device because it selects eight different memory devices at the same time.

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 Memory Interface – Address Decoding
Sample Decoder Circuit
 This Figure shows that the outputs of the decoder are connected to eight different 2764 EPROM
memory devices.
 The decoder selects eight 8Kbyte
blocks of memory for a total memory
capacity of 64K bytes.
 This figure also shows the address
range of each memory device and the
common connections to the memory
devices.

 Notice that all of the address connections from the 8088 are connected to this circuit.

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 Memory Interface – Address Decoding
Sample Decoder Circuit
 Also, notice that the decoder’s outputs are connected to the CE inputs of the EPROMs, and the RD
signal from the 8088 is connected to the OE inputs of the EPROMs.
 This allows only the selected EPROM to
be enabled and to send its data to the
microprocessor through the data bus
whenever RD becomes a logic 0.
 In this circuit, a three - input NAND gate
is connected to address bits A17 – A19.
 When all three address inputs are high,
the output of this NAND gate goes low
and enables input G2B of the 74LS138.

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 Memory Interface – Address Decoding
Sample Decoder Circuit
 Input G1 is connected directly to A16. In other words, in order to enable this decoder, the first four
address connections (A16 – A19) must all be high.
 The address inputs A, B, and C connect
to microprocessor address pins A13 –
A15.
 These three address inputs determine
which output pin goes low and which
EPROM is selected whenever the 8088
outputs a memory address within this
range to the memory system.

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 Memory Interface – Address Decoding
Sample Decoder Circuit
 This Example shows how the address range of the entire decoder is determined. Notice that the
range is location F0000H – FFFFFH. This is a 64K-byte span of the memory.
 EXAMPLE
1111 XXXX XXXX XXXX XXXX
or
1111 0000 0000 0000 0000 = F0000H
to
1111 1111 1111 1111 1111 = FFFFFH

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 Memory Interface – Address Decoding

 The Dual 2-to-4 Line Decoder (74LS139)

 Another decoder 74LS139 contains two
separate 2 – to - 4 line decoders — each
with its own address, enable, and output
connections.
 A more complicated decoder using the
74LS139 decoder appears in Figure 10 –
17, please see chapter 10 (Textbook).
 This circuit uses a 128K × 8 EPROM
(271000) and a 128K × 8 SRAM (621000).

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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Memory interfacing divide to four types according to data buses:

1) 8088 and 80188 with their 8-bit data buses
2) 8086, 80186, 80286, and 80386SX with their 16-bit data buses
3) 80386DX and 80486 with their 32-bit data buses
4) Pentium–Core2 with their 64-bit data buses.
 We will discuss only the first type only with RAM and ROM

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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Basic 8088/80188 Memory Interface

 The 8088 and 80188 microprocessors have an 8-bit data bus, which makes them ideal to connect to
the common 8-bit memory devices available today.
 The 8-bit memory size makes the 8088, and especially the 80188, ideal as a simple controller.
 The memory system must decode the address to select a memory component.
 It must also use the RD, WR, and IO/M control signals provided by the 8088/80188 to control the
memory system.
 In this section, the minimum mode configuration is used.

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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Basic 8088/80188 Memory Interface (Interfacing EPROM to the 8088)

 Next Figure shows an 8088/80188 microprocessor connected to three 27256 EPROMs, 32K × 8
memory devices.

 The 74HCT138
decoder decodes
three 32K × 8
blocks of memory
for a total of 96K ×
8 bits of the
physical address
space for the
8088/80188.
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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Basic 8088/80188 Memory Interface (Interfacing EPROM to the 8088)

 Notice that the decoder is selected for a memory address range that begins at location E8000H and
continues through location FFFFFH—the upper 96K bytes of memory.
 In this circuit, U1 is decoded at addresses E8000H–EFFFFH, U2 is decoded at F0000H–F7FFFH, and U3
is decoded at F8000H–FFFFFH.

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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Basic 8088/80188 Memory Interface (Interfacing RAM to the 8088)

 An ideal section of the memory for the RAM is the very bottom,
which contains vectors for interrupts.
 Interrupt vectors (discussed in more detail in Chapter 12) are often
modified by software packages.
 Next Figure shows sixteen 62256, 32K × 8 static RAMs interfaced to
the 8088, beginning at memory location 00000H.
 This circuit board uses two decoders to select the 16 different RAM
memory components and a third to select the other decoders for
the appropriate memory sections.
 Sixteen 32K RAMs fill memory from location 00000H through
location 7FFFFH, for 512K bytes of memory.

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 Memory Interface – 8088 and 80188 (8-Bit) Memory Interface

 Basic 8088/80188 Memory Interface (Interfacing RAM to the 8088)

 The first decoder (U4) in this circuit selects the other two decoders.
An address beginning with 00 selects decoder U3 and an address
that begins with 01 selects decoder U9.
 Notice that extra pins remain at the output of decoder U4 for
future expansion.
 Also, all the address inputs to this section of memory are buffered,
as are the data bus connections and control signals RD and WR.
 Buffering is important when many devices appear on a single
board or in a single system.

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