NXP Semiconductors Document Number MC56F80XXX

Data Sheet: Technical Data Rev. 2, 11/2022

MC56F80XXX
MC56F80xxx
Supports MC56F807xx and
MC56F806xx
Features • Communication interfaces
– Up to two high-speed queued SCI (QSCI) modules
• This family of digital signal controllers (DSCs) is
with LIN slave functionality
based on the 32-bit 56800EF core. On a single chip,
– One queued SPI (QSPI) module (in MC56F807xx
each device combines the processing power of a DSP
only)
and the functionality of an MCU, with a flexible set of
– One LPI2C module (supports Full PMBus)
peripherals to support many target applications:
– Industrial control • Timers
– Motion control – One 16-bit quad timer (1 x 4Ch)
– Home appliances – Three 32-bit Periodic Interval Timers (PITs)
– General-purpose inverters – One enhanced Quadrature Decoder (eQDC) (in
– Smart sensors, fire and security systems MC56F807xx only)
– Switched-mode power supply and power
• Security and integrity
management
– Cyclic Redundancy Check (CRC) generator
– Uninterruptible power supplies (UPS)
– Windowed Computer operating properly (COP)
– Solar inverter
watchdog
– Medical monitoring applications
– External Watchdog Monitor (EWM)
• DSC based on 32-bit 56800EF core
• Clocks
– Up to 100 MIPS at 100 MHz core frequency
– On-chip oscillators: 200 kHz, and 8/2MHz IRC
– DSP and MCU functionality in a unified, C-efficient
– Crystal / resonator oscillator
architecture
– Enhanced single-precision Floating Point math Unit • System
(eFPU) – 4-channel enhanced DMA controller, supporting up
– COordinate Rotation DIgital Compute (CORDIC) to 63 request sources
engine – Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
• On-chip memory
– Inter-Module Crossbar and Event Generator
– Up to 64 KB flash memory
– JTAG/enhanced on-chip emulation (EOnCE) for
– 8 KB data/program RAM
unobtrusive, real-time debugging
– Both on-chip flash memory and RAM can be
mapped into both program and data memory spaces • Operating characteristics
– Single supply: 2.7 V to 3.6 V
• Analog
– Operation ambient temperature (V grade
– Two high-speed, 12-bit ADCs with dynamic x1, x2,
temperature): -40℃ to 105℃
and x4 programmable amplifier
– Operation ambient temperature (M grade
– Up to two operational amplifiers, programmable
temperature): -40℃ to 125℃
gain up to x16
– Three analog comparators with integrated 8-bit DAC • 64-pin LQFP, 48-pin LQFP packages (32-pin LQFP
references and QFN optional)
– On-chip temperature sensors
• One high resolution eFlexPWM module with up to 12
PWM outputs, including up to 8 channels with 312ps
resolution NanoEdge placement

NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
 MC56F80xxx, Rev. 2, 11/2022
2 NXP Semiconductors
 Table of Contents
1 Overview................................................................................................. 4 7.8 Definition: Typical value........................................................... 36

1.1 Product Family............................................................................. 4 7.9 Typical value conditions............................................................ 37

1.2 56800EF 32-bit Digital Signal Controller (DSC) core.................5 8 Ratings...................................................................................................38

1.3 Operation Parameters................................................................... 6 8.1 Thermal handling ratings........................................................... 38

1.4 Interrupt Controller...................................................................... 6 8.2 Moisture handling ratings...........................................................38

1.5 Peripheral highlights.................................................................... 7 8.3 ESD and latch-up ratings............................................................38

1.6 System Block Diagram...............................................................14 8.4 Voltage and current operating ratings........................................ 39

2 Signal and pin descriptions................................................................... 16 9 General.................................................................................................. 39

3 Signal groups.........................................................................................26 9.1 General characteristics............................................................... 39

4 Pinout.................................................................................................... 26 9.2 AC electrical characteristics.......................................................40

4.1 Signal Multiplexing and Pin Assignments................................. 26 9.3 Nonswitching electrical specifications.......................................40
4.2 Pinout diagrams..........................................................................28 9.4 Switching specifications.............................................................46

5 Ordering parts........................................................................................31 9.5 Thermal specifications............................................................... 47

5.1 Determining valid orderable parts..............................................31 10 Peripheral operating requirements and behaviors................................. 48

5.2 Part number list.......................................................................... 31 10.1 Core modules..............................................................................48

6 Part identification.................................................................................. 32 10.2 System modules..........................................................................49

6.1 Description................................................................................. 32 10.3 Clock modules............................................................................50

6.2 Format........................................................................................ 32 10.4 Memories and memory interfaces.............................................. 52

6.3 Fields.......................................................................................... 32 10.5 Analog........................................................................................ 54

6.4 Example......................................................................................33 10.6 PWMs and timers....................................................................... 59

7 Terminology and guidelines..................................................................33 10.7 Communication interfaces..........................................................60

7.1 Definition: Operating requirement............................................. 33 11 Design Considerations.......................................................................... 65

7.2 Definition: Operating behavior.................................................. 34 11.1 Thermal design considerations...................................................65

7.3 Definition: Attribute...................................................................34 11.2 Electrical design considerations................................................. 67

7.4 Definition: Rating.......................................................................34 11.3 Power-on Reset design considerations.......................................68

7.5 Result of exceeding a rating....................................................... 35 12 Obtaining package dimensions............................................................. 69

7.6 Relationship between ratings and operating requirements.........35 13 Revision history.................................................................................... 70

7.7 Guidelines for ratings and operating requirements.................... 36

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Overview

1 Overview

1.1 Product Family

Table 1. MC56F80xxx Family
Feature MC56F80
748 738 746 736 726 743 733 723 648 646 626 643 623
Core frequency (MHz) 100
Flash memory (KB) 64 48 64 48 32 64 48 32 64 64 32 64 32
RAM (KB) 8 8 8 8 6 8 8 6 8 8 6 8 6
Inter Module Xbar Yes
Event Generator 4
Windowed Watchdog 1
External Watchdog Monitor 1
eDMA 4CH
Internal OSC 8 MHz / 200 KHz
External Crystal Oscillator Yes (4 MHz ~ 16 MHz)
Comparator + 8-bit DAC 3
Operational Amplifier 2 1 2 1
12-bit Cyclic ADC channels 2 × 14-ch
High-resolution PWM 8-ch 6-ch 1 —
Standard PWM 4-ch 2-ch — 8-ch 6-ch 1 6-ch 1
Input Capture in PWM pin
QTimers 4 × 16-bit
Enhanced Quadrature Decoder 1 —
Periodic Interval Timers 3 × 32-bit 2 × 32-bit
LPI2C (supports Full PMBus) 1
QSCI 2 1 2 1
QSPI 1 —
GPIO 54 39 26 54 39 26
Operating Temperature -40℃ to 105℃ (V grade -40℃ to 105℃ (V grade temperature)
temperature)
-40℃ to 125℃ (M grade
temperature)
Package 64 LQFP 48 LQFP 32 LQFP/QFN 2 64 48 LQFP 32 LQFP2
LQF
P

1. Only include the PWM channels with output pins. All internal 8 channels PWM are available through the on-chip inter-
module crossbar.

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 Overview

2. The 32 LQFP and 32 QFN packages for this product are not yet available. However, the pin-out and pricing information of
these packages are readily available. These devices are then committed for sampling and production based on customer
demand.

1.2 56800EF 32-bit Digital Signal Controller (DSC) core

• 100 MHz CPU frequency
• Efficient 32-bit 56800EF Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• Enhanced single-precision Floating Point math Unit (eFPU):
• Supports floating-point instruction acceleration based on the IEEE 754-2008
standard
• Beside normal operations (add, subtract, multiply and divide), it also supports
operations such as: min, max, square root, as well as a rich set of data format
conversions
• COordinate Rotation DIgital Compute (CORDIC) engine:
• Uses 32-bit fixed-point signed fractional numbers in Q5.27 format
• Trigonometric Math:
Supports calculations of selected trigonometric, inverse trig, hyperbolic and
exponentiation functions using circular and hyperbolic coordinates in both
rotation and vector modes
Calculates trigonometric and hyperbolic functions using simple, small
iterative hardware structure
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Fast integer and fraction 32/16 and 32/32 divide instructions
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
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Overview

• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
that is independent of processor speed

1.3 Operation Parameters

• Operation ambient temperature:
V grade temperature: -40 oC to 105oC
M grade temperature: -40 oC to 125oC
• Single power supply
Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V

1.4 Interrupt Controller

• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnCE interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EF core
• Two programmable fast interrupts that can be assigned to any interrupt source

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 Peripheral highlights

• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table

1.5 Peripheral highlights

1.5.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)

• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• 6 bit addition for high resolution PWM
• Fractional delay for enhanced resolution of the PWM period and edge placement
• Arbitrary PWM edge placement
• 312 ps PWM frequency and duty-cycle and deadtime resolution when NanoEdge
functionality is enabled.
• PWM outputs can be configured as complementary output pairs or independent
outputs
• Dedicated time-base counter with period and frequency control per submodule
• Independent top and bottom deadtime insertion for each complementary pair
• Independent control of both edges of each PWM output
• Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
• Synchronization of submodule to external hardware (or other PWM) is supported.
• Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
• Multiple output trigger events can be generated per PWM cycle via hardware.
• Support for double-switching PWM outputs
• Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Individual software control of each PWM output
• All outputs can be programmed to change simultaneously via a FORCE_OUT event.
• PWMX pin can optionally output a third PWM signal from each submodule
• Option to supply the source for each complementary PWM signal pair from any of
the following:

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Peripheral highlights

• Crossbar module outputs

• External ADC input, taking into account values set in ADC high and low limit
registers
• Direct phase shift controls among each submodule
• Trigger signal can share the same load frequency as reload signal in each submodule

1.5.2 12-bit Analog-to-Digital Converter (Cyclic type)

• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 14-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency up to 12.5 MHz, having period as low as 80 ns
• Single conversion time of 10 ADC clock cycles
• Additional conversion time of 8 ADC clock cycles
• Support of analog inputs for single-ended and differential (including unipolar
differential) conversions
• Sequential and parallel scan modes. Parallel mode includes simultaneous and
independent scan modes.
• Samples of each ADC have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for hardware-triggering and software-triggering conversions
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 10 conversion results.
• Current injection protection

1.5.3 Operational Amplifier (OPAMP)

• Capability of being configured as various types of amplifier:
• standalone operational amplifier
• unity gain follower (voltage follower)
• x2, x4, x8, x16 programmable gain amplifier (PGA)
• differential amplifier
• low-pass filter
• 4-to-1 input multiplexer on inverting and non-inverting input
• 4 set configurations including multiplexer inputs can be managed by internal
modules and synchronized with ADCs, PWMs and timers
• Operation modes: high speed mode and low power mode

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 Peripheral highlights

1.5.4 Comparator
• Full rail-to-rail comparison range
• Support for high and low speed modes
• Selectable input source includes external pins and internal DACs
• Programmable output polarity
• 8-bit programmable DAC as a voltage reference per comparator
• Three programmable hysteresis levels
• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output

1.5.5 Periodic Interrupt Timer (PIT)

• 32-bit counter with programmable count modulo
• PIT0/1 can be master and PIT2 is slave mode only (if synchronizing with other PITs)
• The output signals of both PIT0 and PIT1 are internally connected to a peripheral
crossbar module
• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from
Wait/Stop modes.
• In addition to System Bus Clock (IPBus Clock), alternate clock sources for the
counter clock are also available:
• Crystal oscillator output
• 8 MHz / 2 MHz internal RC output
• On-chip low-power 200 kHz oscillator

1.5.6 Quadrature Decoder (QDC)

• Includes logic to decode quadrature signals
• Inputs can be connected to a general purpose timer to make low speed velocity
measurements
• Configurable digital filter for inputs
• Quadrature decoder filter can be bypassed
• 32-bit position counter capable of modulo counting
• Position counter can be initialized by software or external events
• 16-bit position difference register
• Compare function can indicate when shaft has reached a defined position
• A watchdog timer can detect a non-rotating shaft condition
• Preloadable 16-bit revolution counter
• Maximum count frequency equals the peripheral clock rate
• Optional interrupt when both PHASEA and PHASEB inputs change in the same
cycle

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Peripheral highlights

1.5.7 Inter-Module Crossbar and Event Generator (EVTG) logic

• Provides generalized connections between and among on-chip peripherals: ADCs,
comparators, quad-timers, eFlexPWMs, EWM, quadrature decoder, and select I/O
pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• The EVTG module mainly includes two parts: Two AND/OR/INVERT (known
simply as the AOI) modules and one configurable Flip-Flop. It supports the
generation of a configurable number of EVENT signals. The inputs are from crossbar
(XBAR) outputs, and the outputs feed to XBAR inputs.

1.5.8 Quad Timer

• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters

1.5.9 Queued Serial Communications Interface (QSCI) modules with

LIN Slave Functionality
• Operating clock can be up to two times the CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
• 16-bit integer and 3-bit fractional baud rate selection
• Full-duplex or single-wire operation
• Programmable 8-bit or 9-bit data format
• Error detection capability
• Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
• Support for Local Interconnect Network (LIN) slave operation

1.5.10 Queued Serial Peripheral Interface (QSPI) modules

• Maximum 25 Mbit/s baud rate
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 Peripheral highlights

• Selectable baud rate clock sources for low baud rate communication
• Baud rate as low as the maximum Baud rate / 4096
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four-word-deep FIFOs available on transmit and receive buffers
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB or LSB as first bit transmitted)

1.5.11 Low Power Inter-Integrated Circuit (LPI2C)

The LPI2C supports:
• Standard, Fast, Fast+ and Ultra Fast modes are supported
• High speed mode (HS) in slave mode
• High speed mode (HS) in master mode, if SCL pin implements current source pull-
up (device-specific)
• Multi-master support, including synchronization and arbitration. Multi-master means
any number of master nodes can be present. Additionally, master and slave roles may
be changed between messages (after a STOP is sent).
• Clock stretching: Sometimes multiple I2C nodes may be driving the lines at the same
time. If any I2C node is driving a line low, then that line will be low. I2C nodes that
are starting to transmit a logical one (by letting the line float high) can detect that the
line is low, and thereby know that another I2C node is active at the same time.
• When node detection is used on the SCL line, it is called clock stretching, and
clock stretching is used as a I2C flow control mechanism for multiple laves.
• When node detection is used on the SDA line, it is called arbitration, and
arbitration ensures that there is only one I2C node transmitter at a time.
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID (also require software support)
The LPI2C master supports:
• Command/transmit FIFO of 4words.
• Receive FIFO of 4words.
• Command FIFO will wait for idle I2C bus before initiating transfer
• Command FIFO can initiate (repeated) START and STOP conditions and one or
more master-receiver transfers
• STOP condition can be generated from command FIFO, or generated automatically
when the transmit FIFO is empty
• Host request input to control the start time of an I2C bus transfer

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NXP Semiconductors 11
Peripheral highlights

• Flexible receive data match can generate interrupt on data match and/or discard
unwanted data
• Flag and optional interrupt to signal Repeated START condition, STOP condition,
loss of arbitration, unexpected NACK, and command word errors
• Supports configurable bus idle timeout and pin-stuck-low timeout
The LPI2C slave supports:
• Separate I2C slave registers to minimize software overhead because of master/slave
switching
• Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call
address
• Transmit data register that supports interrupt or DMA requests
• Receive data register that supports interrupt or DMA requests
• Software-controllable ACK or NACK, with optional clock stretching on ACK/
NACK bit
• Configurable clock stretching, to avoid transmit FIFO underrun and receive FIFO
overrun errors
• Flag and optional interrupt at end of packet, STOP condition, or bit error detection

1.5.12 Windowed Computer Operating Properly (COP) watchdog

• Programmable windowed timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
• System bus clock (IPBus clock)
• 8 MHz / 2 MHz IRC
• Support for interrupt generation

1.5.13 External Watchdog Monitor (EWM)

• Monitors external circuit as well as the software flow
• Programmable timeout period
• Interrupt capability prior to timeout
• Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs

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 Clock sources

• Selectable reference clock source in support of EN60730 and IEC61508

• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
• System bus clock (IPBus clock)
• 8 MHz / 2 MHz IRC

1.5.14 Power supervisor (PMC)

• Power-on reset (POR) is released after VDD is greater than the Low-Voltage
Warning threshold during supply is ramped up; CPU, peripherals, and JTAG/EOnCE
controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical low-voltage alarm interrupt (LVI_2p2)
• Peripheral low-voltage warning interrupt (LVI_2p65)

1.5.15 Phase-locked loop

• Output frequency range is optimized from 200 MHz to 550 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
• Detection of loss of lock and loss of reference clock
• Ability to power down

1.5.16 Clock sources

1.5.16.1 On-chip oscillators

• Tunable 8 MHz RC oscillator with 2 MHz at standby mode
• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT

1.5.16.2 Crystal oscillator

• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz

1.5.17 Cyclic Redundancy Check (CRC) generator

• Hardware 16/32-bit CRC generator
• High-speed hardware CRC calculation
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Clock sources

• Programmable initial seed value

• Programmable 16/32-bit polynomial
• Error detection for all single, double, odd, and most multi-bit errors
• Option to transpose input data or output data (CRC result) bitwise or bytewise,1
which is required for certain CRC standards
• Option for inversion of final CRC result

1.5.18 General Purpose I/O (GPIO)

• Individual control of peripheral mode or GPIO mode for each pin
• Programmable push-pull or open drain output
• Configurable pullup or pulldown on all input pins
• All pins (except JTAG, RESET_B ) default to be GPIO inputs
• Controllable output slew rate

1.6 System Block Diagram

NOTE
The following figure shows the maximum memory
configurations supported.

1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user
software must perform the bytewise transposition.

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14 NXP Semiconductors
 Clock sources

JTAG EOnCE 56800EF

Flash Controller
and Cache
Program Address Program Bus

Memory Resource
M0 S0 Program/Data Flash
Controller

Protection Unit
Generation
Up to 64KB

Crossbar Switch
4 (PC) Unit (AGU) Core Data Bus

Platform Bus
Bit Arithmetic M1
Manipulation Logic Unit Secondary Data Bus
Unit (ALU) M2 P-Port (Primary)
S1
Single Data/Program RAM
COordinate Rotation
Precision DIgital Compute
M3 Up to 8KB
FPU engine (CORDIC) S2 S-Port (Secondary)
S3

Crystal OSC
eDMA Controller Interrupt Controller
Internal IRC
Clock MUX

2Mhz / 8Mhz Power Management

Watchdog (COP)
Internal IRC Controller (PMC)
200Khz System Integration
Periodic Interrupt
CRC PLL Timer (PIT) 0,1,2 Module (SIM)

Peripheral Bus

QSCI eFlexPWM Quad Timer Enhanced Quadrature

LPI2C QSPI
0,1 NanoEdge 4ch Decoder (eQDC)

Inter Module Crossbar Inputs Inter Module connection

Peripheral Bus
Inter Module Crossbar Outputs

Event
Generator

GPIO & Peripheral MUX Inter-Module

Crossbar

Inter Module Crossbar Outputs

Inter Module Crossbar Inputs

Package 12-bit 12-bit OPAMP CMPs with 8-bit DAC

EWM
Pins ADCA ADCB A,B A,B,C

Peripheral Bus

Figure 1. System block diagram

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Signal and pin descriptions

2 Signal and pin descriptions

After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
For the MC56F80xxx products, which use 64-pin LQFP, 48-pin LQFP and 32-pin LQFP
packages:
Table 2. Signal descriptions
Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
VDD 29 — — Supply Supply I/O Power — Supplies 3.3 V power to the chip I/O
interface.
44 32 —
60 44 28
VSS 30 22 14 Supply Supply I/O Ground — Provide ground for the device I/O
interface.
43 31 —
61 45 29
VDDA 22 15 9 Supply Supply Analog Power — Supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power
supply.
VSSA 23 16 10 Supply Supply Analog Ground — Supplies an analog ground to the
analog modules. It must be connected to a clean power
supply.
VCAP 26 19 — On-chip On-chip Connect a 2.2 µF or greater bypass capacitor between
regulator regulator this pin and VSS to stabilize the core voltage regulator
57 43 27
output output output required for proper device operation.
NOTE: The total bypass capacitor value between all
VCAP pins and VSS recommends between
4.0uF ~ 5.0uF.
TDI 64 48 32 Input, Input Test Data Input — Provides a serial input data stream
internal to the JTAG/EOnCE port. It is sampled on the rising
pullup edge of TCK and has an internal pullup resistor. After
enabled reset, the default state is TDI.
(GPIOD0) Input/ GPIO Port D0.
Output
TDO 62 46 30 Output Output Test Data Output — This tri-state-able pin provides a
serial output data stream from the JTAG/EOnCE port. It
is driven in the shift-IR and shift-DR controller states,
and it changes on the falling edge of TCK. After reset,
the default state is TDO.
(GPIOD1) Input/ GPIO Port D1.
Output

Table continues on the next page...

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 Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
TCK 1 1 1 Input, Input Test Clock Input — This input pin provides a gated
internal clock to synchronize the test logic and shift serial data
pulldown to the JTAG/EOnCE port.The pin is connected
enabled internally to a pulldown resistor. A Schmitt-trigger input
is used for noise immunity. After reset, the default state
is TCK.
(GPIOD2) Input/ GPIO Port D2.
Output
TMS 63 47 31 Input, Input Test Mode Select Input — Used to sequence the JTAG
internal TAP controller state machine. It is sampled on the
pullup rising edge of TCK and has an internal pullup resistor.
enabled After reset, the default state is TMS.
NOTE: Always tie the TMS pin to VDD through a 2.2
kΩ resistor if need to keep on-board debug
capability. Otherwise, directly tie to VDD.
Except being configured as GPIO.
(GPIOD3) Input/ GPIO Port D3.
Output
RESET_B 2 2 2 Input, Input Reset — A direct hardware reset on the processor.
internal When RESET_B is asserted low, the device is
pullup initialized and placed in the reset state. A Schmitt-
enabled trigger input is used for noise immunity. The internal
reset signal is deasserted synchronously with the
internal clocks after a fixed number of internal clocks.
After reset, the default state is RESET_B.
Recommended a capacitor of 0.1 µF for filtering noise
and up to 22 µF for time delay if required.
(GPIOD4) Input/ GPIO Port D4 — Can be individually programmed as
Open- an input or open-drain output pin. RESET_B
drain functionality is disabled in this mode and the device
Output can be reset only through Power-On Reset (POR),
COP reset, or software reset.
GPIOA0 13 9 6 Input Input/ GPIO Port A0 — After reset, the default state is
Output GPIOA0.
(ANA0 Input ANA0 — ADCA channel 0 input.
& CMPA_IN3 — Analog comparator A input 3
CMPA_IN3 OPAMPA_IN3 — Operational amplifier A input 3
& When used as an analog input, the signal goes to
ANA0 and CMPA_IN3 and OPAMPA_IN3. 1
OPAMPA_IN3)
(CMPC_O) Output Analog comparator C output.
GPIOA1 14 10 7 Input Input/ GPIO Port A1 — After reset, the default state is
Output GPIOA1.
(ANA1 Input ANA1 — ADCA channel 1 input.
& CMPA_IN0 — Analog comparator A input 0.
CMPA_IN0 OPAMPA_IN0 — Operational amplifier A input 0.
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Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
& When used as an analog input, the signal goes to
ANA1 and CMPA_IN0 and OPAMPA_IN0.1
OPAMPA_IN0)
GPIOA2 15 11 8 Input Input/ GPIO Port A2 — After reset, the default state is
Output GPIOA2.
(ANA2 Input ANA2 — ADCA channel 2 input.
& VREFHA — ADCA analog reference high.
VREFHA CMPA_IN1 — Analog comparator A input 1.
& When used as an analog input, the signal goes to
ANA2 (or VREFHA) and CMPA_IN1. 1
CMPA_IN1)
NOTE: ADC input can be configured as either ANA2
or VREFHA in the ADC Calibration Register.
GPIOA3 16 12 — Input Input/ GPIO Port A3 — After reset, the default state is
Output GPIOA3.
(ANA3 Input ANA3 — ADCA channel 3 input.
& VREFLA — ADCA analog reference low.
VREFLA CMPA_IN2 — Analog comparator A input 2.
& When used as an analog input, the signal goes to
ANA3 (or VREFLA) and CMPA_IN2.1
CMPA_IN2)
NOTE: ADC input can be configured as either ANA3
or VREFLA in the ADC Calibration Register.
GPIOA4 12 8 — Input Input/ GPIO Port A4 — After reset, the default state is
Output GPIOA4.
(ANA40 Input ANA40 — ADCA channel 4 expansion MUX input 40.
& CMPA_IN4 — Analog comparator A input 4.
CMPA_IN4) When used as an analog input, the signal goes to
ANA40 and CMPA_IN4.1
GPIOA5 11 — — Input Input/ GPIO Port A5 — After reset, the default state is
Output GPIOA5.
(ANA5 Input ANA5 — ADCA channel 5 input.
& CMPB_IN4 — Analog comparator B input 4.
CMPB_IN4) When used as an analog input, the signal goes to
ANA5 and CMPB_IN4.1
GPIOA6 10 — — Input Input/ GPIO Port A6 — After reset, the default state is
Output GPIOA6.
(ANA6 Input ANA6 — ADCA channel 6 input.
& CMPC_IN4 — Analog comparator C input 4.
CMPC_IN4 OPAMPA_IN1 — Operational amplifier A input 1.
& When used as an analog input, the signal goes to
ANA6 and CMPC_IN4 and OPAMPA_IN1.1
OPAMPA_IN1)
GPIOA7 9 — — Input Input/ GPIO Port A7 — After reset, the default state is
Output GPIOA7.

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 Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
(ANA7 Input ANA7 — ADCA channel 7 input.
& OPAMPA_IN2 — Operational amplifier A input 2.
OPAMPA_IN2) When used as an analog input, the signal goes to
ANA7 and OPAMPA_IN2.1
GPIOB0 24 17 11 Input Input/ GPIO Port B0 — After reset, the default state is
Output GPIOB0.
(ANB0 Input ANB0 — ADCB channel 0 input.
& CMPB_IN3 — Analog comparator B input 3.
CMPB_IN3 OPAMPB_IN3 — Operational amplifier B input 3.
& When used as an analog input, the signal goes to
ANB0 and CMPB_IN3 and OPAMPB_IN3.1
OPAMPB_IN3)
GPIOB1 25 18 12 Input Input/ GPIO Port B1 — After reset, the default state is
Output GPIOB1.
(ANB1 Input ANB1 — ADCB channel 1 input.
& CMPB_IN0 —Analog comparator B input 0.
CMPB_IN0 OPAMPB_IN0 — Operational amplifier B input 0.
& When used as an analog input, the signal goes to
ANB1 and CMPB_IN0 and OPAMPB_IN0.1
OPAMPB_IN0)
GPIOB2 27 20 13 Input Input/ GPIO Port B2 — After reset, the default state is
Output GPIOB2.
(ANB2 Input ANB2 — ADCB channel 2 input.
& VREFHB — ADCB analog reference high.
VREFHB CMPC_IN3 — Analog comparator C input 3.
& When used as an analog input, the signal goes to
ANB2 (or VREFHB) and CMPC_IN3.1
CMPC_IN3)
NOTE: ADC input can be configured as either ANB2
or VREFHB in the ADC Calibration Register.
GPIOB3 28 21 — Input Input/ GPIO Port B3 — After reset, the default state is
Output GPIOB3.
(ANB3 Input ANB3 — ADCB channel 3 input.
& VREFLB — ADCB analog reference low.
VREFLB CMPC_IN0 _ Analog comparator C input 0.
& When used as an analog input, the signal goes to
ANB3 (or VREFHB) and CMPC_IN0.1
CMPC_IN0)
NOTE: ADC input can be configured as either ANB3
or VREFLB in the ADC Calibration Register.
GPIOB4 21 14 — Input Input/ GPIO Port B4 — After reset, the default state is
Output GPIOB4.
(ANB40 Input ANB40 — ADCB channel 4 expansion MUX input 40.
& CMPC_IN1 — Analog comparator C input 1.
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NXP Semiconductors 19
Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
CMPC_IN1) When used as an analog input, the signal goes to
ANB40 and CMPC_IN1.1
GPIOB5 20 — — Input Input/ GPIO Port B5 — After reset, the default state is
Output GPIOB5.
(ANB5 Input ANB5 — ADCB channel 5 input.
& CMPC_IN2 — Analog comparator C input 2.
CMPC_IN2) When used as an analog input, the signal goes to
ANB5 and CMPC_IN2.1
GPIOB6 19 — — Input Input/ GPIO Port B6 — After reset, the default state is
Output GPIOB6.
(ANB6 Input ANB6 — ADCB channel 6 input.
& CMPB_IN1 — Analog comparator B input 1.
CMPB_IN1 OPAMPB_IN1 — Operational amplifier B input 1.
& When used as an analog input, the signal goes to
ANB6 and CMPB_IN1 and OPAMPB_IN1. 1
OPAMPB_IN1)
GPIOB7 17 — — Input Input/ GPIO Port B7 — After reset, the default state is
Output GPIOB7.
(ANB7 Input ANB7 — ADCB channel 7 input.
& CMPB_IN2 — Analog comparator B input 2.
CMPB_IN2 OPAMPB_IN2 — Operational amplifier B input 2.
& When used as an analog input, the signal goes to
ANB7 and CMPB_IN2 and OPAMPB_IN2.1
OPAMPB_IN2)
GPIOC0 3 3 — Input Input/ GPIO Port C0 — After reset, the default state is
Output GPIOC0.
(EXTAL) Input External crystal oscillator input (EXTAL) connects the
internal crystal oscillator input to an external crystal or
ceramic resonator.
(CLKIN0) Input External clock input 0 to OCCS.

NOTE: If this pin is selected as the device’s external

clock input, then both SIM_GPSCL[C0] bit in
SIM and OSCTL1[EXT_SEL] bit in OCCS
must be set. The crystal oscillator should be
powered down.
GPIOC1 4 4 — Input Input/ GPIO Port C1 — After reset, the default state is
Output GPIOC1.
(XTAL) Output External crystal oscillator output (XTAL) connects the
internal crystal oscillator output to an external crystal or
ceramic resonator.
GPIOC2 5 5 3 Input Input/ GPIO Port C2 — After reset, the default state is
Output GPIOC2.
(TXD0) Output SCI0 transmit data output or transmit/receive in single
wire operation.

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20 NXP Semiconductors
 Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
(XB_OUT11) Output Crossbar module output 11.
(XB_IN2) Input Crossbar module input 2.
(CLKO0) Output Buffered clock output 0.

NOTE: The clock source is selected by

SIM_CLKOUT[CLKOSEL0] bits in SIM.
GPIOC3 7 6 4 Input Input/ GPIO Port C3 — After reset, the default state is
Output GPIOC3.
(TA0) Input/ Quad timer channel 0 input/output.
Output
(CMPA_O) Output Analog comparator A output.
(RXD0) Input SCI0 receive data input.
(CLKIN1) Input External clock input 1 to OCCS.

NOTE: If this pin is selected as device's external clock

input, then both SIM_GPSCL[C3] bits in SIM
and OSCTL1[EXT_SEL] bit in OCCS must be
set.
GPIOC4 8 7 5 Input Input/ GPIO Port C4 — After reset, the default state is
Output GPIOC4.
(TA1) Input/ Quad timer channel 1 input/output.
Output
(CMPB_O) Output Analog comparator B output.
(XB_IN8) Input Crossbar module input 8.
(OPAMPA_OUT) Output Operational amplifier A output.
GPIOC5 18 13 — Input Input/ GPIO Port C5 — After reset, the default state is
Output GPIOC5.
(ANB4d) Input ADCB channel 4 expansion MUX input 4d.
(XB_IN7) Input Crossbar module input 7.
GPIOC6 31 23 15 Input Input/ GPIO Port C6 — After reset, the default state is
Output GPIOC6.
(TA2) Input/ Quad timer channel 2 input/output.
Output
(XB_IN3) Input Crossbar module input 3.
(CMP_REF) Input Input 5 of analog comparator A and B and C.
(SS0_B) Input/ SPI0 slave select.
Output
GPIOC7 32 24 — Input Input/ GPIO Port C7 — After reset, the default state is
Output GPIOC7.
(SS0_B) Input/ SPI0 slave select.
Output
(TXD0) Output SCI0 transmit data output or transmit/receive in single
wire operation.
(XB_IN8) Input Crossbar module input 8.

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NXP Semiconductors 21
Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
(XB_OUT6) Output Crossbar module output 6.
GPIOC8 33 25 16 Input Input/ GPIO Port C8 — After reset, the default state is
Output GPIOC8.
(MISO0) Input/ SPI0 master in/slave out.
Output
(RXD0) Input SCI0 receive data input.
(XB_IN9) Input Crossbar module input 9.
GPIOC9 34 26 17 Input Input/ GPIO Port C9 — After reset, the default state is
Output GPIOC9.
(SCLK0) Input/ SPI0 serial clock.
Output
(XB_IN4) Input Crossbar module input 4.
(TXD0) Output SCI0 transmit data output or transmit/receive in single
wire operation.
(XB_OUT8) Output Crossbar module output 8.
GPIOC10 35 27 18 Input Input/ GPIO Port C10 — After reset, the default state is
Output GPIOC10.
(MOSI0) Input/ SPI0 master out/slave.
Output
(XB_IN5) Input Crossbar module input 5.
(MISO0) Input/ SPI0 master in/slave out.
Output
(XB_OUT9) Output Crossbar module output 9.
GPIOC11 37 29 — Input Input/ GPIO Port C11 — After reset, the default state is
Output GPIOC11.
(LP_SCLS0) Output I2C0 secondary serial clock line.
NOTE: In 4-wire mode, this is the I2C slave SCL
output for voltage level shift.
(ANB4b) Input ADCB channel 4 expansion MUX input 4b.
(TXD1) Output SCI1 transmit data output or transmit/receive in single
wire operation.
(PWMA_0X) Output PWM submodule 0, output X or input capture X.
GPIOC12 38 30 — Input Input/ GPIO Port C12 — After reset, the default state is
Output GPIOC12.
(LP_SDAS0) Output I2C0 secondary serial data line.
NOTE: In 4-wire mode, this is the I2C slave SDA
output for voltage level shift.
(ANA4b) Input ADCA channel 4 expansion MUX input 4b.
(RXD1) Input SCI1 receive data input
(PWMA_1X) Output PWM submodule 1, output X or input capture X.
GPIOC13 49 37 — Input Input/ GPIO Port C13 — After reset, the default state is
Output GPIOC13.

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22 NXP Semiconductors
 Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
(TA3) Input/ Quad timer channel 3 input/output.
Output
(XB_IN6) Input Crossbar module input 6.
(EWM_OUT_B) Output External Watchdog Module output.
GPIOC14 55 41 — Input Input/ GPIO Port C14 — After reset, the default state is
Output GPIOC14.
(LP_SDA0) Input/ I2C0 serial data line
Open-
NOTE: In 4-wire mode, this is the I2C slave SDA
drain
input.
Output
(XB_OUT4) Output Crossbar module output 4.
(PWMA_FAULT4) Input PWM Fault input 4 for disabling selected PWM outputs.
(ANB4c) Input ADCB channel 4 expansion MUX input 4c.
GPIOC15 56 42 — Input Input/ GPIO Port C15: After reset, the default state is
Output GPIOC15.
(LP_SCL0) Input/ I2C0 serial clock line
Open-
NOTE: In 4-wire mode, this is the I2C slave SCL input.
drain
Output
(XB_OUT5) Output Crossbar module output 5.
(PWMA_FAULT5) Input PWM Fault input 5 for disabling selected PWM outputs.
ANA4c Input ADCA channel 4 expansion MUX input 4c.
GPIOE0 45 33 21 Input Input/ GPIO Port E0 — After reset, the default state is
Output GPIOE0.
(PWMA_0B) Input/ PWM submodule 0, high resolution output B or input
Output capture B.
XB_OUT4 Output Crossbar module output 4.
GPIOE1 46 34 22 Input Input/ GPIO Port E1 — After reset, the default state is
Output GPIOE1.
(PWMA_0A) Input/ PWM submodule 0, high resolution output A or input
Output capture A.
(XB_OUT5) Output Crossbar module output 5.
GPIOE2 47 35 23 Input Input/ GPIO Port E2 — After reset, the default state is
Output GPIOE2.
(PWMA_1B) Input/ PWM submodule 1, high resolution output B or input
Output capture B.
XB_OUT6 Output Crossbar module output 6.
GPIOE3 48 36 24 Input Input/ GPIO Port E3 — After reset, the default state is
Output GPIOE3.
(PWMA_1A) Input/ PWM submodule 1, high resolution output A or input
Output capture A.
(XB_OUT7) Output Crossbar module output 7.

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NXP Semiconductors 23
Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
GPIOE4 51 39 25 Input Input/ GPIO Port E4 — After reset, the default state is
Output GPIOE4.
(PWMA_2B) Input/ PWM submodule 2, high resolution output B or input
Output capture B.
(XB_IN2) Input Crossbar module input 2
(XB_OUT8) Output Crossbar module output 8.
GPIOE5 52 40 26 Input Input/ GPIO Port E5 — After reset, the default state is
Output GPIOE5.
(PWMA_2A) Input/ PWM submodule 2, high resolution output A or input
Output capture A
(XB_IN3) Input Crossbar module input 3.
(XB_OUT9) Output Crossbar module output 9.
GPIOE6 53 — — Input Input/ GPIO Port E6 — After reset, the default state is
Output GPIOE6.
(PWMA_3B) Input/ PWM submodule 3, high resolution output B or input
Output capture B.
(XB_IN4) Input Crossbar module input 4
(ANB4e) Input ADCB channel 4 expansion MUX input 4e.
(XB_OUT10) Output Crossbar module output 10.
GPIOE7 54 — — Input Input/ GPIO Port E7 — After reset, the default state is
Output GPIOE7.
(PWMA_3A) Input/ PWM ,submodule 3, high resolution output A or input
Output capture A.
(XB_IN5) Input Crossbar module input 5.
(ANA4e) Input ADCA channel 4 expansion MUX input 4e.
(XB_OUT11) Output Crossbar module output 11.
GPIOF0 36 28 — Input Input/ GPIO Port F0 — After reset, the default state is
Output GPIOF0.
(XB_IN6) Input Crossbar module input 6
(OPAMPB_OUT) Output Operational amplifier B output.
GPIOF1 50 38 — Input Input/ GPIO Port F1 — After reset, the default state is
Output GPIOF1.
(CLKO1) Output Buffered clock output 1.

NOTE: The clock source is selected by

SIM_CLKOUT[CLKOSEL1] bits in SIM.
(XB_IN7) Input Crossbar module input 7.
(ANA4d) Input ADCA channel 4 expansion MUX input 4d.
GPIOF2 39 — 19 Input Input/ GPIO Port F2 — After reset, the default state is
Output GPIOF2.
(ANA4a) Input ADCA channel 4 expansion MUX input 4a.
(XB_OUT6) Output Crossbar module output 6

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24 NXP Semiconductors
 Signal and pin descriptions

Table 2. Signal descriptions (continued)

Signal Name 64 48 32 State Type Signal Description
LQFP LQFP LQFP/ During
QFN Reset
(LP_SDA0) Input/ I2C0 serial data line.
Open-
NOTE: In 4-wire mode, this is the I2C slave SDA
drain
input.
Output
GPIOF3 40 — 20 Input Input/ GPIO Port F3 — After reset, the default state is
Output GPIOF3.
(ANB4a) Input ADCB channel 4 expansion MUX input 4a.
(XB_OUT7) Output Crossbar module output 7
(LP_SCL0) Input/ I2C0 serial clock line
Output
NOTE: In 4-wire mode, this is the I2C slave SCL input.
GPIOF4 41 — — Input Input/ GPIO Port F4 — After reset, the default state is
Output GPIOF4.
(TXD1) Output SCI1 transmit data output or transmit/receive in single
wire operation
(XB_OUT8) Output Crossbar module output 8
(PWMA_0X) Input/ PWM submodule 0, output X or input capture X.
Output
(PWMA_FAULT6) Input PWM Fault input 6 for disabling selected PWM outputs.
GPIOF5 42 — — Input Input/ GPIO Port F5 — After reset, the default state is
Output GPIOF5.
(RXD1) Input SCI1 receive data input.
(XB_OUT9) Output Crossbar module output 9.
(PWMA_1X) Input/ PWM submodule 1, output X or input capture X.
Output
(PWMA_FAULT7) Input PWM Fault input 7 for disabling selected PWM outputs.
GPIOF6 58 — — Input Input/ GPIO Port F6 — After reset, the default state is
Output GPIOF6.
(ANB4f) Input ADCB channel 4 expansion MUX input 4f.
(PWMA_3X) Input/ PWM submodule 3, output X or input capture X.
Output
(XB_IN2) Input Crossbar module input 2.
GPIOF7 59 — — Input Input/ GPIO Port F7 — After reset, the default state is
Output GPIOF7.
(ANA4f) Input ADCA channel 4 expansion MUX input 4f.
(CMPC_O) Output Analog comparator C output.
(XB_IN3) Input Crossbar module input 3.
GPIOF8 6 — — Input Input/ GPIO Port F8 — After reset, the default state is
Output GPIOF8.
(RXD0) Input SCI0 receive data input.
(XB_OUT10) Output Crossbar module output 10.
(CMPD_O) Output Analog comparator D output.
(PWMA_2X) Output PWM submodule 2, output X or input capture X.

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NXP Semiconductors 25
Signal groups

1. The glitch on this pin during ADC sampling may interfere with other analog inputs shared on this pin.

3 Signal groups
The input and output signals of this device are organized into functional groups, as
detailed in the following table.
Table 3. Functional Group Pin Allocations
Functional Group Number of Pins
32LQFP 48LQFP 64LQFP
Power Inputs (VDD, VDDA), Power output( VCAP) 3 5 6
Ground (VSS, VSSA) 3 4 4
Reset 1 1 1
eFlexPWM outputs high resolution PWM 6 6 8
eFlexPWM outputs without high resolution PWM 0 2 6
Queued Serial Peripheral Interface (QSPI0) ports 4 5 5
Queued Serial Communications Interface (QSCI0 and QSCI1 1) ports 4 7 10
Inter-Integrated Circuit Interface (LPI2C0) ports 2 2 4 3 6
12-bit Analog-to-Digital Converter (ADC) inputs 8 16 28
Analog Comparator inputs/outputs 7/3 11/3 16/4
Analog Operational Amplifier inputs/outputs 4/1 4/2 8/2
Quad Timer Module (TMR) ports 3 4 4
Inter-Module Crossbar inputs/outputs 8/11 13/12 17/19
Clock inputs/outputs 1/1 2/2 2/2
JTAG / Enhanced On-Chip Emulation (EOnCE) 4 4 4

1. QSCI1 is not available in the 32-pin package.

2. 4-wire mode is not supported.
3. Only LPI2C0 supports 4-wire mode.

4 Pinout

4.1 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3
LQFP LQFP LQFP
1 1 1 TCK TCK GPIOD2

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26 NXP Semiconductors
 Pinout

64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3

LQFP LQFP LQFP
2 2 2 RESET_B RESET_B GPIOD4
3 3 — GPIOC0 GPIOC0 EXTAL CLKIN0
4 4 — GPIOC1 GPIOC1 XTAL
5 5 3 GPIOC2 GPIOC2 TXD0 XB_OUT11 XB_IN2 CLKO0
6 — — GPIOF8 GPIOF8 RXD0 XB_OUT10 PWMA_2X
7 6 4 GPIOC3 GPIOC3 TA0 CMPA_O RXD0 CLKIN1
8 7 5 GPIOC4 GPIOC4 TA1 CMPB_O XB_IN8 OPAMPA_OUT
9 — — GPIOA7 GPIOA7 ANA7+OPAMPA_IN2
10 — — GPIOA6 GPIOA6 ANA6+OPAMPA_
IN1+CMPC_IN4
11 — — GPIOA5 GPIOA5 ANA5+CMPB_IN4
12 8 — GPIOA4 GPIOA4 ANA40+CMPA_IN4
13 9 6 GPIOA0 GPIOA0 ANA0+CMPA_ CMPC_O
IN3+OPAMPA_IN3
14 10 7 GPIOA1 GPIOA1 ANA1+CMPA_
IN0+OPAMPA_IN0
15 11 8 GPIOA2 GPIOA2 ANA2+VREFHA+CMPA_
IN1
16 12 — GPIOA3 GPIOA3 ANA3+VREFLA+CMPA_
IN2
17 — — GPIOB7 GPIOB7 ANB7+CMPB_
IN2+OPAMPB_IN2
18 13 — GPIOC5 GPIOC5 ANB4d XB_IN7
19 — — GPIOB6 GPIOB6 ANB6+CMPB_
IN1+OPAMPB_IN1
20 — — GPIOB5 GPIOB5 ANB5+CMPC_IN2
21 14 — GPIOB4 GPIOB4 ANB40+CMPC_IN1
22 15 9 VDDA VDDA
23 16 10 VSSA VSSA
24 17 11 GPIOB0 GPIOB0 ANB0+CMPB_
IN3+OPAMPB_IN3
25 18 12 GPIOB1 GPIOB1 ANB1+CMPB_
IN0+OPAMPB_IN0
26 19 — VCAP VCAP
27 20 13 GPIOB2 GPIOB2 ANB2+VREFHB+CMPC_
IN3
28 21 — GPIOB3 GPIOB3 ANB3+VREFLB+CMPC_
IN0
29 — — VDD VDD
30 22 14 VSS VSS
31 23 15 GPIOC6 GPIOC6 TA2 XB_IN3 CMP_REF SS0_B
32 24 — GPIOC7 GPIOC7 SS0_B TXD0 XB_IN8 XB_OUT6
33 25 16 GPIOC8 GPIOC8 MISO0 RXD0 XB_IN9
34 26 17 GPIOC9 GPIOC9 SCLK0 XB_IN4 TXD0 XB_OUT8

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NXP Semiconductors 27
Pinout

64 48 32 Pin Name Default ALT0 ALT1 ALT2 ALT3

LQFP LQFP LQFP
35 27 18 GPIOC10 GPIOC10 MOSI0 XB_IN5 MISO0 XB_OUT9
36 28 — GPIOF0 GPIOF0 XB_IN6 OPAMPB_OUT
37 29 — GPIOC11 GPIOC11 LP_SCLS0 ANB4b TXD1 PWMA_0X
38 30 — GPIOC12 GPIOC12 LP_SDAS0 ANA4b RXD1 PWMA_1X
39 — 19 GPIOF2 GPIOF2 ANA4a XB_OUT6 LP_SDA0
40 — 20 GPIOF3 GPIOF3 ANB4a XB_OUT7 LP_SCL0
41 — — GPIOF4 GPIOF4 TXD1 XB_OUT8 PWMA_0X PWMA_FAULT6
42 — — GPIOF5 GPIOF5 RXD1 XB_OUT9 PWMA_1X PWMA_FAULT7
43 31 — VSS VSS
44 32 — VDD VDD
45 33 21 GPIOE0 GPIOE0 PWMA_0B XB_OUT4
46 34 22 GPIOE1 GPIOE1 PWMA_0A XB_OUT5
47 35 23 GPIOE2 GPIOE2 PWMA_1B XB_OUT6
48 36 24 GPIOE3 GPIOE3 PWMA_1A XB_OUT7
49 37 — GPIOC13 GPIOC13 TA3 XB_IN6 EWM_OUT_B
50 38 — GPIOF1 GPIOF1 CLKO1 XB_IN7 ANA4d
51 39 25 GPIOE4 GPIOE4 PWMA_2B XB_IN2 XB_OUT8
52 40 26 GPIOE5 GPIOE5 PWMA_2A XB_IN3 XB_OUT9
53 — — GPIOE6 GPIOE6 PWMA_3B XB_IN4 ANB4e XB_OUT10
54 — — GPIOE7 GPIOE7 PWMA_3A XB_IN5 ANA4e XB_OUT11
55 41 — GPIOC14 GPIOC14 LP_SDA0 XB_OUT4 PWMA_FAULT4 ANB4c
56 42 — GPIOC15 GPIOC15 LP_SCL0 XB_OUT5 PWMA_FAULT5 ANA4c
57 43 27 VCAP VCAP
58 — — GPIOF6 GPIOF6 ANB4f PWMA_3X XB_IN2
59 — — GPIOF7 GPIOF7 ANA4f CMPC_O XB_IN3
60 44 28 VDD VDD
61 45 29 VSS VSS
62 46 30 TDO TDO GPIOD1
63 47 31 TMS TMS GPIOD3
64 48 32 TDI TDI GPIOD0

4.2 Pinout diagrams

The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.

MC56F80xxx, Rev. 2, 11/2022

28 NXP Semiconductors
 Pinout

GPIOC15

GPIOC14

GPIOC13
GPIOE4
GPIOE5
GPIOE7

GPIOE6
GPIOF7

GPIOF6

GPIOF1
VCAP
TDO

VDD
TMS

VSS
TDI

61

51
62

52
59

55

49
58

56
60

50
64

63

57

54

53
TCK 1 48 GPIOE3

RESET_B 2 47 GPIOE2

GPIOC0 3 46 GPIOE1

GPIOC1 4 45 GPIOE0

GPIOC2 5 44 VDD

GPIOF8 6 43 VSS

GPIOC3 7 42 GPIOF5

GPIOC4 8 41 GPIOF4

GPIOA7 9 40 GPIOF3

GPIOA6 10 39 GPIOF2

GPIOA5 11 38 GPIOC12

GPIOA4 12 37 GPIOC11

GPIOA0 13 36 GPIOF0

GPIOA1 14 35 GPIOC10

GPIOA2 15 34 GPIOC9

GPIOA3 16 33 GPIOC8
21

31
22

25

26

28

29
23

24

27

32
30
20
19
18
17

GPIOB6
GPIOC5

GPIOB5
GPIOB7

GPIOB4

GPIOC6
VDDA

GPIOB1

VCAP

VDD
GPIOB3
VSSA

GPIOB0

GPIOB2

GPIOC7
VSS

Figure 2. 64-pin LQFP

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 29
Pinout

GPIOC15

GPIOC14

GPIOC13
GPIOE5

GPIOE4

GPIOF1
VCAP
TMS

TDO

VDD
VSS
TDI

41
42
45
48

46
47

44

43

39
40

38

37
TCK 1 36 GPIOE3

RESET_B 2 35 GPIOE2

GPIOC0 3 34 GPIOE1

GPIOC1 4 33 GPIOE0

GPIOC2 5 32 VDD

GPIOC3 6 31 VSS

GPIOC4 7 30 GPIOC12

GPIOA4 8 29 GPIOC11

GPIOA0 9 28 GPIOF0

GPIOA1 10 27 GPIOC10

GPIOA2 11 26 GPIOC9

GPIOA3 12 25 GPIOC8
21

22

23

24
20
13

14

15

16

18

19
17
VDDA

VCAP
VSSA

GPIOB1

GPIOB2
GPIOC5

GPIOB4

GPIOB0

GPIOB3

VSS

GPIOC6

GPIOC7

Figure 3. 48-pin LQFP

MC56F80xxx, Rev. 2, 11/2022

30 NXP Semiconductors
 Ordering parts

GPIOE5

GPIOE4
VCAP
TMS

TDO

VDD
VSS
TDI

31
32

29

25
30

28

26
27
TCK 1 24 GPIOE3

RESET_B 2 23 GPIOE2

GPIOC2 3 22 GPIOE1

GPIOC3 4 21 GPIOE0

GPIOC4 5 20 GPIOF3

GPIOA0 6 19 GPIOF2

GPIOA1 7 18 GPIOC10

GPIOA2 8 17 GPIOC9
12

13

14

15

16
10

11
9

GPIOB0

GPIOB1
VDDA

GPIOC6
VSSA

GPIOC8
GPIOB2

VSS

Figure 4. 32-pin LQFP

5 Ordering parts

5.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F80

5.2 Part number list

The following table shows a part number list for this device.

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 31
Part identification

Table 4. Part numbers

Part Number Flash RAM High-resolution Operating Package 1
PWM Temperature
MC56F80748VLH 64 KB 8 KB Yes -40 to 105℃ 64 LQFP
MC56F80738VLH 48 KB 8 KB Yes -40 to 105℃ 64 LQFP
MC56F80746VLF 64 KB 8 KB Yes -40 to 105℃ 48 LQFP
MC56F80736VLF 48 KB 8 KB Yes -40 to 105℃ 48 LQFP
MC56F80726VLF 32 KB 6 KB Yes -40 to 105℃ 48 LQFP
MC56F80743VLC 64 KB 8 KB Yes -40 to 105℃ 32 LQFP
MC56F80723VLC 32 KB 6 KB Yes -40 to 105℃ 32 LQFP
MC56F80743VFM 64 KB 8 KB Yes -40 to 105℃ 32 QFN
MC56F80733VFM 48 KB 8 KB Yes -40 to 105℃ 32 QFN
MC56F80648VLH 64 KB 8 KB — -40 to 105℃ 64 LQFP
MC56F80646VLF 64 KB 8 KB — -40 to 105℃ 48 LQFP
MC56F80626VLF 32 KB 6 KB — -40 to 105℃ 48 LQFP
MC56F80643VLC 64 KB 8 KB — -40 to 105℃ 32 LQFP
MC56F80623VLC 32 KB 6 KB — -40 to 105℃ 32 LQFP
MC56F80748MLH 64 KB 8 KB Yes -40 to 125℃ 64 LQFP
MC56F80746MLF 64 KB 8 KB Yes -40 to 125℃ 48 LQFP

1. The 32 LQFP and 32 QFN packages for this product are not yet available. However, the pin-out and pricing information of
these packages are readily available. These devices are then committed for sampling and production based on customer
demand.

6 Part identification

6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.

6.2 Format
Part numbers for this device have the following format: Q 56F8 0 C F P T PP N

6.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
MC56F80xxx, Rev. 2, 11/2022
32 NXP Semiconductors
 Terminology and guidelines

Field Description Values

Q Qualification status • MC = Fully qualified, general market flow
• PC = Prequalification
56F8 DSC family with flash memory and DSP56800/ • 56F8
DSP56800E/DSP56800EX/DSP56800EF core
0 DSC subfamily • 0
C Maximum CPU frequency (MHz) • 6 = 100 MHz
• 7 = 100 MHz
F Primary program flash memory size • 2 = 32 KB
• 3 = 48 KB
• 4 = 64 KB
P Pin count • 3 = 32
• 6 = 48
• 8 = 64
T Temperature range (℃) • V = –40 to 105
• M = –40 to 125
PP Package identifier • LC = 32LQFP
• FM = 32QFN
• LF = 48LQFP
• LH = 64LQFP
N Packaging type • R = Tape and reel
• (Blank) = Trays

6.4 Example
This is an example part number: MC56F80748VLH

7 Terminology and guidelines

7.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.

7.1.1 Example
This is an example of an operating requirement:

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 33
Terminology and guidelines

Symbol Description Min. Max. Unit

VDD 1.0 V core supply 0.9 1.1 V
voltage

7.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.

7.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/ 10 130 µA
pulldown current

7.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.

7.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance: — 7 pF
digital pins

7.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:

MC56F80xxx, Rev. 2, 11/2022

34 NXP Semiconductors
 Terminology and guidelines

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

7.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply –0.3 1.2 V
voltage

7.5 Result of exceeding a rating

40

30
Failures in time (ppm)

20 The likelihood of permanent chip failure increases rapidly as

soon as a characteristic begins to exceed one of its operating ratings.

10

0
Operating rating
Measured characteristic

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 35
Terminology and guidelines

7.6 Relationship between ratings and operating requirements

) .)
in. ax
n. ) nt (m nt (m .)
mi me me ax
( ire ire (m
ng qu qu ng
r ati re re rati
ing ing ing ing
e rat erat erat e rat
Op Op Op Op

Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range

Expected permanent failure - No permanent failure - No permanent failure - No permanent failure Expected permanent failure
- Possible decreased life - Correct operation - Possible decreased life
- Possible incorrect operation - Possible incorrect operation

–∞ ∞
Operating (power on)

n.) x.)
mi ma
in g( ing(
rat rat
ng ng
ndli ndli
Ha Ha

Fatal range Handling range Fatal range

Expected permanent failure No permanent failure Expected permanent failure

–∞ ∞
Handling (power off)

7.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.

7.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.

MC56F80xxx, Rev. 2, 11/2022

36 NXP Semiconductors
 Terminology and guidelines

7.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak 10 70 130 µA
pullup/pulldown
current

7.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000

4500

4000
TJ
3500
150 °C
3000
IDD_STOP (μA)

105 °C
2500
25 °C
2000
–40 °C
1500

1000

500

0
0.90 0.95 1.00 1.05 1.10

VDD (V)

7.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TA Ambient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 37
Ratings

8 Ratings

8.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.

8.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.

8.3 ESD and latch-up ratings

Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD and latch-up ratings
Characteristic Description 1 Rating Notes
Electrostatic discharge voltage, human body model ±2000 V 2
Electrostatic discharge voltage, charged device model ±500 V 3
Latch-up immunity level (Class II at 135 ℃ junction temperature) Immunity Level A 4

MC56F80xxx, Rev. 2, 11/2022

38 NXP Semiconductors
 General

1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
2. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2017, For Electrostatic Discharge Sensitivity Testing,
Human Body Model (HBM) - Component Level.
3. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2018, For Electrostatic Discharge Sensitivity Testing,
Charged Device Model (CDM) - Device Level.
4. Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.

8.4 Voltage and current operating ratings

Table 6. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
ID Instantaneous maximum current single pin limit (applies to all –25 25 mA
port pins)
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

9 General

9.1 General characteristics

Absolute maximum ratings in the table of "Voltage and current operating ratings" section
are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond these ratings may affect device reliability or cause permanent damage to the
device.
Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in the table of "Voltage and current operating ratings" section over the
following supply ranges: VSS = VSSA = 0 V, VDD = VDDA = 3.0 V to 3.6 V, CL ≤ 50 pF,
fOP = 50 MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-
impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 39
General

9.2 AC electrical characteristics

Tests are conducted using the input levels specified in the section "Voltage and current
operating behaviors". Unless otherwise specified, propagation delays are measured from
the 50% to the 50% point, and rise and fall times are measured between the 20% and 80%
points, as shown in Figure 5.

Low High
VIH
80%
Input Signal Midpoint1 50%
20%
VIL
Fall Time Rise Time

The midpoint is VIL + (VIH - VIL) / 2

Figure 5. Input signal measurement references

All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
Figure 6 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data2 Valid Data3 Valid

Data1 Data2 Data3

Data
Data Invalid State Tri-stated
Data Active Data Active

Figure 6. Signal states

9.3 Nonswitching electrical specifications

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40 NXP Semiconductors
 General

9.3.1 Voltage and current operating requirements

This section includes information about recommended operating conditions.
Table 7. Voltage and current operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 2.7 3.3 3.6 V —
VDDA Analog supply voltage 2.7 3.3 3.6 V —
VDD – VDD-to-VDDA differential voltage –0.1 0.1 V —
VDDA
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V —
VIH Input high voltage —
• 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V

VIL Input low voltage —

• 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V

VHYS Input hysteresis 0.06 × VDD — V —

VIHOSC Oscillator Input Voltage High 2.0 VDD + 0.3 V —
XTAL driven by an external clock source
VILOSC Oscillator Input Voltage Low -0.3 0.8 V —
IICIO IO pin negative DC injection current—single pin 1
–3 — mA
• VIN < VSS–0.3V

IICcont Contiguous pin DC injection current —regional —

limit, includes sum of negative injection currents
of 16 contiguous pins
–25 — mA
• Negative current injection

1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this
limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R = (VIO_MIN - VIN)/|IICIO|.

9.3.2 LVD and POR operating requirements

Table 8. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic Symbol Min Typ Max Unit
POR Assert Voltage1 POR 2.0 V
POR Release Voltage2 POR 2.7 V
Low-Voltage Warning Interrupt LVI_2p65 2.65 V
Low-Voltage Alarm Interrupt LVI_2p2 2.18 V

1. During 3.3-volt VDD power supply ramp down

2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p65)

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 41
General

9.3.3 Voltage and current operating behaviors

Table 9. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except 1
RESET)
VDD – 0.5 — V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA

VOH Output high voltage — High drive pad (except RESET) 2, 1

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
VDD – 0.5 — V
IOHT Output high current total for all ports — 100 mA —
VOL Output low voltage — Normal drive pad (except 1
RESET)
— 0.5 V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA

VOL Output low voltage — High drive pad (except RESET) 2, 1

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
— 0.5 V
IOLT Output low current total for all ports — 100 mA —
IIN Input leakage current (per pin) for full temperature — 1 μA 3
range
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3
IIN Input leakage current (total all pins) for full temperature — 41 μA 3
range
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA —
RPU Internal pullup resistors 20 50 kΩ 4
RPD Internal pulldown resistors 20 50 kΩ 5

1. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
2. GPIOC2, GPIOC7~12, GPIOF2~3 and GPIOC14~15 support high drive strength mode.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD

9.3.4 Power mode transition operating behaviors

Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.

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42 NXP Semiconductors
 General

Table 10. Reset, stop, wait, and interrupt timing

Characteristic Symbol Typical Min Typical Unit See
Max Figure
Minimum RESET Assertion Duration tRA 16 1 — ns —
RESET deassertion to First Address Fetch tRDA 865 × TOSC + 8 × T ns —
Delay from Interrupt Assertion to Fetch of first tIF 361.3 570.9 ns —
instruction (exiting Stop)

1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns. Recommended a capacitor of up to 0.1 µF on RESET.

NOTE
In Table 10, T = system clock cycle and TOSC = oscillator clock
cycle. For an operating frequency of 50MHz, T=20 ns. At 4
MHz (used coming out of reset and stop modes), T=250 ns.

Table 11. Power mode transition behavior

Symbol Description Typical Max Unit Notes1
TPOR After a POR event, the amount of delay from when VDD reaches 300 345 µs
2.7 V to when the first instruction executes (over the operating
temperature range).
STOP mode to RUN mode 7.30 8.40 µs 2
LPS mode to LPRUN mode 290 334 µs 3
VLPS mode to VLPRUN mode 900 1035 µs 4
WAIT mode to RUN mode 0.305 0.351 µs 5
LPWAIT mode to LPRUN mode 290 334 µs 3
VLPWAIT mode to VLPRUN mode 900 1035 µs 4

1. Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from
respective stop/wait mode.
2. Clock configuration: CPU clock=4 MHz. System clock source is 8 MHz IRC in normal mode.
3. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit by an interrupt on PORTA GPIO.
4. Using 64 kHz external clock; CPU Clock = 32 kHz. Exit by an interrupt on PORTA GPIO.
5. Clock configuration: CPU and system clocks = 100 MHz. Bus Clock = 100 MHz. Exit by interrupt on PORTA GPIO

9.3.5 Power consumption operating behaviors

Table 12. Current Consumption (Unit: mA)
Mode Maximum Conditions 1 Typical at Maximum at Maximum at
Frequenc 3.3 V, 25°C 3.6 V, 105°C 3.6V, 125°C
y
IDD1 IDDA IDD1 IDDA IDD1 IDDA
RUN 100 MHz • 100 MHz Core and Peripheral clock 26.9 6.9 32.5 14.2 33.0 14.9
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
Table continues on the next page...

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NXP Semiconductors 43
General

Table 12. Current Consumption (Unit: mA) (continued)

Mode Maximum Conditions 1 Typical at Maximum at Maximum at
Frequenc 3.3 V, 25°C 3.6 V, 105°C 3.6V, 125°C
y
IDD1 IDDA IDD1 IDDA IDD1 IDDA
• Continuous MAC instructions with fetches from
Program Flash
• All peripheral modules enabled. SCIs using 1X
bus clock
• NanoEdge within eFlexPWM using 2X
peripheral clock
• ADC/DAC (all 8-bit DACs) powered on and
clocked
• Comparator powered on
WAIT 100 MHz • 50 MHz Core and Peripheral clock 21.2 0.033 28.4 0.193 2 28.9 0.193 2
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
• Processor Core in WAIT state
• All Peripheral modules enabled. SCIs using 1X
bus clock
• NanoEdge within PWMA using 2X peripheral
clock
• ADC/DAC (all 8-bit DACs), Comparator
powered off
STOP 4 MHz • 4 MHz Device Clock 4.4 0.033 9.0 0.192 2 9.5 0.192 2
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered off
• Processor Core in STOP state
• All peripheral module and core clocks are off
• ADC/DAC/Comparator powered off
LPRUN 2 MHz • 200 kHz Device Clock from Relaxation 1.1 0.002 5.2 0.066 2 5.7 0.066 2
(LsRUN) Oscillator's (ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except
NanoEdge and cyclic ADCs. All 8-bit DACs
enabled. 3
• Simple loop with running from platform
instruction buffer
LPWAIT 2 MHz • 200 kHz Device Clock from Relaxation 1.0 0.002 5.2 0.065 2 5.7 0.065 2
(LsWAIT) Oscillator's (ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except
NanoEdge and cyclic ADCs. All 8-bit DACs
enabled.3
• Processor core in wait mode
LPSTOP 2 MHz • 200 kHz Device Clock from Relaxation 1.0 0.002 4.2 0.065 2 4.5 0.065 2
(LsSTOP) Oscillator's (ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
Table continues on the next page...

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44 NXP Semiconductors
 General

Table 12. Current Consumption (Unit: mA) (continued)

Mode Maximum Conditions 1 Typical at Maximum at Maximum at
Frequenc 3.3 V, 25°C 3.6 V, 105°C 3.6V, 125°C
y
IDD1 IDDA IDD1 IDDA IDD1 IDDA
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off3
• Processor core in stop mode
VLPRUN 200 kHz • 32 kHz Device Clock 0.4 0.002 4.0 0.065 2 4.3 0.065 2
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• Repeat NOP instructions
• All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction
buffer
VLPWAIT 200 kHz • 32 kHz Device Clock 0.4 0.002 4.0 0.064 2 4.3 0.064 2
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled
and clocks gated off
• Processor core in wait mode
VLPSTOP 200 kHz • 32 kHz Device Clock 0.4 0.002 4.0 0.062 2 4.3 0.062 2
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby.
• Small regulator is disabled.
• PLL disabled
• All peripheral modules, except COP, disabled
and clocks gated off
• Processor core in stop mode

1. No output switching, all ports configured as inputs, all inputs low, no DC loads.
2. Parameter value is achieved by design characterization by measuring a statistically relevant sample size across process
variations.
3. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 250 kHz due to
the fixed frequency ratio of 1:4 between the CPU clock and the flash clock when running with 2 MHz external clock input
and CPU running at 1 MHz.

9.3.6 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
MC56F80xxx, Rev. 2, 11/2022
NXP Semiconductors 45
General

2. Perform a keyword search for “EMC design.”

9.3.7 Capacitance attributes

Table 13. Capacitance attributes
Description Symbol Min. Typ. Max. Unit
Input capacitance CIN — 10 — pF
Output capacitance COUT — 10 — pF

9.4 Switching specifications

9.4.1 Device clock specifications

Table 14. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYSCLK Device (system and core) clock frequency
• using relaxation oscillator
0.001 100 MHz
• using external clock source
0 100
fBUS Bus clock — 50 MHz

9.4.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO signals.
Table 15. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) — 1.5 — Bus clock 1
Synchronous path cycles
External RESET and NMI pin interrupt pulse width — 100 — ns 2
Asynchronous path
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3

1. The synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load

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 General

9.5 Thermal specifications

9.5.1 Thermal operating requirements

Table 16. Thermal operating requirements
Symbol Description Grade Min Max Unit
TJ Die junction temperature V –40 125 °C
M –40 135 °C
TA Ambient temperature V –40 105 °C
M –40 125 °C

9.5.2 Thermal attributes

This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type 1 Symbol Description 48 LQFP 64 LQFP Unit Notes
Four-layer RθJA Thermal 55 52 °C/W 2
(2s2p) resistance,
junction to
ambient (natural
convection)
Single-layer RθJC Thermal 23 20 °C/W 3
(1s) resistance,
junction to case
— ΨJT Thermal 3 3 °C/W 2
characterization
parameter,
junction to
package top
outside center
(natural
convection)

1. Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p and JESD51-3, 1s).

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Peripheral operating requirements and behaviors

2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
3. Junction-to-Case (Top) thermal resistance is determined using an isothermal cold plate attached to the package top. Case
(Top) temperature refers to the mold surface temperature at the center.

10 Peripheral operating requirements and behaviors

10.1 Core modules

10.1.1 JTAG timing

Table 17. JTAG timing
Characteristic Symbol Min Max Unit See
Figure
TCK frequency of operation fOP DC SYS_CLK/ 8 MHz Figure 7
TCK clock pulse width tPW 50 — ns Figure 7
TMS, TDI data set-up time tDS 5 — ns Figure 8
TMS, TDI data hold time tDH 5 — ns Figure 8
TCK low to TDO data valid tDV — 30 ns Figure 8
TCK low to TDO tri-state tTS — 30 ns Figure 8

1/fOP
tPW tPW
VIH
VM VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2

Figure 7. Test clock input timing diagram

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 System modules

TCK
(Input)
tDS tDH

TDI
TMS Input Data Valid
(Input) tDV

TDO
(Output) Output Data Valid

tTS

TDO
(Output)

Figure 8. Test access port timing diagram

10.2 System modules

10.2.1 Voltage regulator specifications

The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper
operations, the voltage regulator requires a minimum external 2.2 µF capacitor on each
VCAP pin with total capacitors on all VCAP pins at a minimum of 4.4 µF. Ceramic and
tantalum capacitors tend to provide better performance tolerances. The output voltage can
be measured directly on the VCAP pin. The specifications for this regulator are shown in
Table 18.
Table 18. Regulator 1.2 V parameters
Characteristic Symbol Min Typ Max Unit
Output Voltage 1 VCAP — 1.26 — V
Short Circuit Current 2 ISS — 600 — mA
Short Circuit Tolerance (VCAP shorted to ground) TRSC — — 1 minute

1. Value is after trim

2. Guaranteed by design

Table 19. Bandgap electrical specifications

Characteristic Symbol Min Typ Max Unit
Reference Voltage (after trim) VREF — 1.221 — V

1. Typical value is trimmed at 25℃. There could be ±50 mV variation due to temperature change.

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System modules

10.3 Clock modules

10.3.1 External clock operation timing

Parameters listed are guaranteed by design.
Table 20. External clock operation timing requirements
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)1 fosc — — 50 MHz
Clock pulse width2 tPW 8 ns
External clock input rise time3 trise — 1.9 2.5 ns
External clock input fall time4 tfall — 1.9 2.5 ns
Input high voltage overdrive by an external clock Vih 0.85×VDD — — V
Input low voltage overdrive by an external clock Vil — — 0.3×VDD V

1. See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.

VIH
External 90% 90%
Clock 50% 50%
10% 10%
tfall trise VIL
tPW tPW

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 9. External clock timing

10.3.2 Phase-Locked Loop timing

Table 21. Phase-Locked Loop timing
Characteristic Symbol Min Typ Max Unit
PLL input reference frequency1 fref 8 8 16 MHz
PLL output frequency2 fop 200 — 550 MHz
PLL lock time3 tplls — — 100 µs
Allowed Duty Cycle of input reference tdc 40 50 60 %

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is designed for 8 MHz ~ 16 MHz input, but optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must
be set to 400 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.

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10.3.3 External crystal or resonator requirement

Table 22. Crystal or resonator requirement
Characteristic Symbol Min Typ Max Unit
Frequency of operation fXOSC 4 8 16 MHz

10.3.4 RC Oscillator Timing

Table 23. RC Oscillator Electrical Specifications
Characteristic Symbol Min Typ Max Unit
8 MHz Output Frequency1
Run Mode 0°C to 105°C 7.84 8 8.16 MHz
-40°C to 105°C 7.76 8 8.24 MHz
-40°C to 125°C 7.76 8 8.24 MHz
2M Mode (IRC trimmed @ -40°C to 105°C 1.9 2.0 2.1 MHz
8 MHz) -40°C to 125°C 1.9 2.0 2.1 MHz
8 MHz Frequency Variation over 25°C
RUN Mode 0°C to 105°C ±1.5 ±2 %
-40°C to 105°C ±1.5 ±3 %
-40°C to 125°C ±1.5 -3 to +3 %
200 kHz Output Frequency2
RUN Mode -40°C to 105°C 194 200 206 kHz
-40°C to 125°C 192 200 208 kHz
200 kHz Output Frequency Variation over 25°C
RUN Mode 0°C to 85°C ±1.5 ±2 %
-40°C to 105°C ±1.5 ±3 %
-40°C to 125°C ±1.5 ±4 %
Stabilization Time 8 MHz output3 tstab 1 - 15 µs
200 kHz output3 - 125 375 µs
Output Duty Cycle 45 50 55 %

1. Frequency after factory trim

2. Frequency after factory trim
3. Power down to run mode transition

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System modules

Figure 10. RC Oscillator Temperature Variation (Typical) After Trim (Preliminary)

10.4 Memories and memory interfaces

10.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

10.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 24. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —

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Table 24. NVM program/erase timing specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 52 452 ms 1

1. Maximum time based on expectations at cycling end-of-life.

10.4.1.2 Flash timing specifications — commands

Table 25. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 1.8 ms 1
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs —
tersall Erase All Blocks execution time — 88 650 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
tersallu Erase All Blocks Unsecure execution time — 88 650 ms 2

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

10.4.1.3 Flash high voltage current behaviors

Table 26. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage — 2.5 6.0 mA
flash programming operation
IDD_ERS Average current adder during high voltage — 1.5 4.0 mA
flash erase operation

10.4.1.4 Reliability specifications

Table 27. NVM reliability specifications
Symbol Description Min. Typ.1 Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —

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System modules

Table 27. NVM reliability specifications (continued)

Symbol Description Min. Typ.1 Max. Unit Notes
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
nnvmcycp Cycling endurance 1K — — cycles 3

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 135 °C. If the product application is
exposed to Tj > 125 °C, the reduced W/E spec applies independent of the number of W/E cycles in the high Tj band.

10.5 Analog

10.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters

Table 28. 12-bit ADC Electrical Specifications
Characteristic Symbol Min Typ Max Unit
Recommended Operating Conditions
Supply Voltage1 VDDA 3 3.3 3.6 V
VREFH (in external reference mode) Vrefhx VDDA-0.6 VDDA V
ADC Conversion Clock2 fADCCLK 0.1 12.5 MHz
Conversion Range3 RAD V
VREFH – VREFL
Fully Differential – (VREFH – VREFL)
VREFH
Single Ended/Unipolar VREFL
Input Voltage Range (per input)4 VADIN V
VREFL VREFH
External Reference
0 VDDA
Internal Reference
Timing and Power
Conversion Time5 tADC 8 ADC Clock
Cycles
ADC Power-Up Time (from adc_pdn) tADPU 13 ADC Clock
Cycles
ADC RUN Current (per ADC block) IADRUN 2.5 mA
ADC Powerdown Current (adc_pdn IADPWRDWN 0.1 µA
enabled)
VREFH Current (in external mode) IVREFH 190 225 µA
Accuracy (DC or Absolute)
Integral non-Linearity6 INL +/- 1.5 +/- 2.2 LSB7
Differential non-Linearity6 DNL +/- 0.5 +/- 0.8 LSB7
Monotonicity GUARANTEED
Offset8 VOFFSET mV
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Table 28. 12-bit ADC Electrical Specifications (continued)

Characteristic Symbol Min Typ Max Unit
Fully Differential +/- 8
Single Ended/Unipolar +/- 12
Gain Error EGAIN 0.996 to 0.990 to 1.010
1.004
AC Specifications9
Signal to Noise Ratio SNR 66 dB
Total Harmonic Distortion THD 75 dB
Spurious Free Dynamic Range SFDR 77 dB
Signal to Noise plus Distortion SINAD 66 dB
Effective Number of Bits ENOB — bits
Gain = 1x (Fully Differential/Unipolar) 10.6
Gain = 2x (Fully Differential/Unipolar) —
Gain = 4x (Fully Differential/Unipolar) 10.3
Gain = 1x (Single Ended) 10.6
Gain = 2x (Single Ended) 10.4
Gain = 4x (Single Ended) 10.2
Variation across channels10 0.1
ADC Inputs
Input Leakage Current IIN 1 nA
Temperature sensor slope TSLOPE 1.3 mV/°C
Temperature sensor voltage at 25 °C VTEMP25 0.82 V
Disturbance
Input Injection Current 11 IINJ +/-3 mA
Channel to Channel Crosstalk12 ISOXTLK -82 dB
Memory Crosstalk13 MEMXTLK -71 dB
Input Capacitance CADI pF
4.8
Sampling Capacitor

1. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed
2. ADC clock duty cycle is 45% ~ 55%
3. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
4. In unipolar mode, positive input must be ensured to be always greater than negative input.
5. First conversion takes 10 clock cycles.
6. INL/DNL is measured from VIN = VREFL to VIN = VREFH using Histogram method at x1 gain setting
7. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain Setting
8. Offset measured at 2048 code
9. Measured converting a 1 kHz input full scale sine wave
10. When code runs from internal RAM
11. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
12. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk)
13. From a previously sampled channel with 50 kHz full-scale input to the channel being sampled with DC input (memory
crosstalk).

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System modules

10.5.1.1 Equivalent circuit for ADC inputs

The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, andboth S1 and S2 are dependent on
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
+ 50 ohm +Resistor
(ADC ClockRate) x CADI

NOTE
Resistor=1200 ohm@gain1×, or 730 ohm@gain2×, or 500
ohm@gain4× 

C1

Channel Mux
S1
Analog Input 50  ESD equivalent resistance
C1
Resistor Resistor(value see the note) S1

S/H
S1
1 2
C1
S1
S2 S2
(VREFHx - VREFLx ) / 2

C1


1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock
frequency
S1

S2

32 Freescale Semicond
Figure 11. Equivalent circuit for A/D loading

10.5.2 OPAMP electrical specifications

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 System modules

Table 29. OPAMP electrical specifications

Symbol Description Min. Typ. Max. Unit
VCC Power supply 3.0 — 3.6 V
ICC Supply current — 500 — μA
• high-speed mode
— 100 —
• low-power mode
VOS Input offset voltage — ±1.5 ±5 mV
• high-speed mode
— ±2 ±6.5
• low-power mode
VIN Common input voltage VSSA — VDDA - 1.2 V
VOUT Output voltage range 0.15 — VDDA - 0.15 V
CMRR Input common mode rejection ratio 60 80 — dB
PSRR Power supply rejection ratio 60 80 — dB
SR Slew rate 1 4 8 — V/μs
• high-speed mode
— 1 —
• low-power mode
GBW Unity gain bandwidth 1 — 8 — MHz
• high-speed mode
1.5
• low-power mode

1. RL = 5 ~ 10 kΩ, CL = 30 ~ 50 pf

10.5.3 CMP and 8-bit DAC electrical specifications

Table 30. Comparator and 8-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 3.0 — 3.6 V
IDDHS Supply current, high-speed mode (EN=1, PMODE=1) — 300 — μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — 36 — μA
VAIN Analog input voltage VSS — VDD V
VAIO Analog input offset voltage 1 — — 20 mV
VH Analog comparator hysteresis
• CR0[HYSTCTR] = 002 — 5 13 mV
• CR0[HYSTCTR] = 011 — 25 48 mV
• CR0[HYSTCTR] = 101 — 55 105 mV
• CR0[HYSTCTR] = 111 — 80 148 mV

VCMPOh Output high VDD – 0.5 — — V

VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, — 25 70 ns
PMODE=1)3
tDLS Propagation delay, low-speed mode (EN=1, — 60 200 ns
PMODE=0)3
Analog comparator initialization delay4 — 40 — μs

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 System modules

Table 30. Comparator and 8-bit DAC electrical specifications (continued)

Symbol Description Min. Typ. Max. Unit
IDAC8b 8-bit DAC current adder (enabled) — 7 — μA
Vreference 8-bit DAC reference inputs, Vin1 and Vin2 — VDD — V
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL 8-bit DAC integral non-linearity –1 — 1 LSB5
DNL 8-bit DAC differential non-linearity –1 — 1 LSB

1. Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8

2. Measured with input voltage range limited to 0 to VDD
3. Input voltage range: 0.1VDD≤Vin≤0.9VDD, step = ±100mV, across all temperature. Does not include PCB and PAD delay.
4. Comparator initialization delay is defined as the time of switching the comparator from the disabled state to the enabled
state, with the comparator output settling to a stable level.
5. 1 LSB = Vreference/256

250.00E-03
hystCR

200.00E-03
0
CMP Hysteresis (V)

150.00E-03
1

100.00E-03

2
50.00E-03

3
000.00E+00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

Vin Level (V)

Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
400.00E-03 hystCR
350.00E-03
0
300.00E-03
CMP Hysteresis (V)

250.00E-03
1
200.00E-03

150.00E-03
2
100.00E-03

50.00E-03
3
000.00E+00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

Vin Level (V)

Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

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 PWMs and timers

10.6 PWMs and timers

10.6.1 Enhanced NanoEdge PWM characteristics

Table 31. NanoEdge PWM timing parameters
Characteristic Symbol Min Typ Max Unit
PWM clock frequency 100 MHz
NanoEdge Placement (NEP) Step Size1, 2 pwmp 312 ps
Delay for fault input activating to PWM output deactivated 1 33 ns
Power-up Time3 tpu 25 µs
Resolution of Deadtime 312 ps

1. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.

2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.

10.6.2 Quad Timer timing

Parameters listed are guaranteed by design.
Table 32. Timer timing
Characteristic Symbol Min1 Max Unit See Figure
Timer input period PIN 2T + 6 — ns Figure 14
Timer input high/low period PINHL 1T + 3 — ns Figure 14
Timer output period POUT 20 — ns Figure 14
Timer output high/low period POUTHL 10 — ns Figure 14

1. T = clock cycle. For 100 MHz operation, T = 10 ns.

Timer Inputs

PIN PINHL PINHL

Timer Outputs

POUT POUTHL POUTHL

Figure 14. Timer timing

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PWMs and timers

10.6.3 QDC Timing Specifications

Parameters listed are guaranteed by design.
Table 33. Quadrature Decoder Timing
Characteristic Symbol Min1 Max Unit
Quadrature input period PIN 4T + 12 — ns
Quadrature input high/low period PHL 2T + 6 — ns
Quadrature phase period PPH 1T + 3 — ns

1. In the formulas listed, T equals the system clock cycle. For 50 MHz operation, T = 20 ns. For 100 MHz operation,
T = 10 ns.

PPH PPH PPH PPH

Phase A
Input

PIN PHL PHL

Phase B
Input

PIN PHL PHL

PIN Input period

PPH Phase period
PHL Input high/low period

Figure 15. Quadrature Decoder Timing

10.7 Communication interfaces

10.7.1 Queued Serial Peripheral Interface (SPI) timing

Parameters listed are guaranteed by design.
Table 34. SPI timing
Characteristic Symbol Min Max Unit See Figure
Cycle time tC Figure 16
60 — ns
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Table 34. SPI timing (continued)

Characteristic Symbol Min Max Unit See Figure
Master 60 — ns Figure 17
Slave Figure 18
Figure 19
Enable lead time tELD Figure 19
— — ns
Master
20 — ns
Slave
Enable lag time tELG Figure 19
— — ns
Master
20 — ns
Slave
Clock (SCK) high time tCH Figure 16
— ns
Master Figure 17
— ns
Slave Figure 18
Figure 19
Clock (SCK) low time tCL Figure 19
28 — ns
Master
28 — ns
Slave
Data set-up time required for inputs tDS Figure 16
20 — ns
Master Figure 17
1 — ns
Slave Figure 18
Figure 19
Data hold time required for inputs tDH Figure 16
1 — ns
Master Figure 17
3 — ns
Slave Figure 18
Figure 19
Access time (time to data active tA Figure 19
5 — ns
from high-impedance state)
Slave
Disable time (hold time to high- tD Figure 19
5 — ns
impedance state)
Slave
Data valid for outputs tDV Figure 16
— ns
Master Figure 17
— ns
Slave (after enable edge) Figure 18
Figure 19
Data invalid tDI Figure 16
0 — ns
Master Figure 17
0 — ns
Slave Figure 18
Figure 19
Rise time tR Figure 16
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Table 34. SPI timing (continued)

Characteristic Symbol Min Max Unit See Figure
Master — 1 ns Figure 17
Slave — 1 ns Figure 18
Figure 19
Fall time tF Figure 16
— 1 ns
Master Figure 17
— 1 ns
Slave Figure 18
Figure 19

SS SS is held high on master

(Input)
tC
tR
tF
SCLK (CPOL = 0) tCL
(Output) tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH tCH
tDS
MISO
(Input) MSB in Bits 14–1 LSB in

tDI tDI(ref)
tDV

MOSI Master MSB out Bits 14–1 Master LSB out

(Output)
tF tR

Figure 16. SPI master timing (CPHA = 0)

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SS SS is held High on master

(Input) tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output) tCH
tF

tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR tDH
MISO
(Input) MSB in Bits 14–1 LSB in

tDV(ref) tDI tDV tDI(ref)

MOSI Master MSB out Bits 14– 1 Master LSB out

(Output)
tF tR

Figure 17. SPI master timing (CPHA = 1)

SS
(Input)
tC
tF tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH

tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH tF
tA tR tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI tDI
tDH
MOSI MSB in Bits 14–1 LSB in
(Input)

Figure 18. SPI slave timing (CPHA = 0)

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SS
(Input)
tF
tC
tR
SCLK (CPOL = 0) tCL
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV tCH tR
tA tF tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI
tDH
MOSI MSB in Bits 14–1 LSB in
(Input)

Figure 19. SPI slave timing (CPHA = 1)

10.7.2 Queued Serial Communication Interface (SCI) timing

Parameters listed are guaranteed by design.
Table 35. SCI timing
Characteristic Symbol Min Max Unit See Figure
Baud rate1 BR — (fMAX/16) Mbit/s —
RXD pulse width RXDPW 0.965/BR 1.04/BR μs Figure 20
TXD pulse width TXDPW 0.965/BR 1.04/BR μs Figure 21
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH -14 14 % —
clock rate before synchronization
Deviation of slave node clock relative to FTOL_SYNCH -2 2 % —
the master node clock after
synchronization
Minimum break character length TBREAK 13 — Master —
node bit
periods
11 — Slave node —
bit periods

1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.50 MHz
depending on part number) or 2x bus clock (max. 100 MHz) for the devices.

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64 NXP Semiconductors
 Design Considerations
RXD
SCI receive
data pin
(Input) RXDPW

Figure 20. RXD pulse width

TXD
SCI transmit
data pin
(output) TXDPW

Figure 21. TXD pulse width

10.7.3 LPI2C
Table 36. LPI2C specifications
Symbol Description Min. Max. Unit Notes
fSCL SCL clock frequency Standard mode (Sm) 0 100 kHz 1, 2, 3
Fast mode (Fm) 0 400
Fast mode Plus (Fm+) 0 1000
Ultra Fast mode (UFm) 0 5000
High speed mode (Hs-mode) 0 3400

1. Hs-mode is only supported in slave mode.

2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with
appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The
maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up
devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus
loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can
support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more
information on the required pull-up devices, see I2C Bus Specification.
3. See the section "General switching specifications".

11 Design Considerations

11.1 Thermal design considerations

An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA × PD)

where
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)

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NXP Semiconductors 65
Design Considerations

PD = Power dissipation in the package (W).

The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-
case thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA

where
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W).
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (ΨJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT × PD)

where
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = Thermal characterization parameter (°C/W)
PD = Power dissipation in package (W).

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66 NXP Semiconductors
 Design Considerations

The thermal characterization parameter is measured per JESD51–2 specification using a

40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-to-
case thermal resistance.

11.2 Electrical design considerations

CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA.
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.

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NXP Semiconductors 67
Design Considerations

• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.1 µF–4.7 µF.
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
reset state during normal operation if JTAG converter is not present. Furthermore,
configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.
• During reset and after reset but before I/O initialization, all the GPIO pins are at tri-
state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.

11.3 Power-on Reset design considerations

11.3.1 Improper power-up sequence between VDD/VSS and VDDA/

VSSA:
It is recommended that VDD be kept within 100 mV of VDDA at all times, including
power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may
cause a leakage current through the substrate, between the VDD and VDDA pad cells.
This leakage current could prevent operation of the device after it powers up. The voltage

MC56F80xxx, Rev. 2, 11/2022

68 NXP Semiconductors
 Obtaining package dimensions

difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid
permanent damage to the part (See the table in "Voltage and current operating ratings"
section). Also see the table in "Voltage and current operating requirements" section.

11.3.2 Heavy capacitive load on power supply output:

In some applications, the low cost DC/DC converter may not regulate the output voltage
well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.
However, the device might exit power-on reset at around 2.3V. If the initialization code
enables the PLL to run the DSC at full speed right after reset, then the high current will
be pulled by DSC from the supply, which can cause the supply voltage to drop below the
operation voltage; see the captured graph (Figure 22). This can cause the DSC fail to start
up.

Figure 22. Supply Voltage Drop

A recommended initialization sequence during power-up is:

1. After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
2. Configure the peripherals (except the ADC) to the desired settings; the ADC should
stay in low power mode.
3. Power up the PLL.
4. After the PLL locks, switch the clock from PLL prescale to postscale.
5. Configure the ADC.

12 Obtaining package dimensions

Package dimensions are provided in package drawings.

MC56F80xxx, Rev. 2, 11/2022

NXP Semiconductors 69
Revision history

To find a package drawing, go to nxp.com and perform a keyword search for the
drawing's document number:
Drawing for package Document number to be used
32LQFP 98ASH70029A
32QFN 98ASA00473D
48-pin LQFP 98ASH00962A
64-pin LQFP 98ASS23234W

13 Revision history
The following table provides a revision history for this document.
Table 37. Revision history
Rev. Date Substantial Changes
2 11/2022 Initial public release

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70 NXP Semiconductors
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Document Number MC56F80XXX

Revision 2, 11/2022