Release Notes For ModelSim Intel FPGA 10.

7c

Aug 17 2018
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_______________________________________________________________________

* How to Get Support

ModelSim Intel FPGA is supported by Intel
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 10.7c
* [4]Base Product Specifications in 10.7c
* [5]Compatibility Issues with Release 10.7c
* [6]User Interface Defects Repaired in 10.7c
* [7]SystemVerilog Defects Repaired in 10.7c
* [8]VHDL Defects Repaired in 10.7c
* [9]User Interface Enhancements in 10.7c
* [10]SystemVerilog Enhancements in 10.7c
* [11]Document Revision History in 10.7c
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows 7, Windows 8.1, Windows 10
+ linuxaloem - RedHat Enterprise Linux 6,7 SUSE Linux Enterprise
 Server 11,12
_______________________________________________________________________

Release Announcements in 10.7c

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* We regularly review our OS/Platform support for Questa/ModelSim and
related functional verification products to add new platforms and
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That process normally takes a number of years from decision to
action. Customer notifications are typically only one year in an
advance through our Release Notes and Install Guide.
We plan to make a change in our Windows support, 1 year from now.
We began notifications of this change back in January 2017 with the
10.5d and 10.6a releases
As our existing Windows machines breakdown or are discontinued,
replacement hardware can only support Windows 10. So say Microsoft
and our hardware vendors, HP & Lenovo. That will limit our capacity
and ability to support Windows 7 & 8.1 in the future.
Therefore, starting with 10.8 (FCS Dec 2018) we plan to discontinue
supporting Windows 7 & 8.1 Thus the only Windows version for 10.8
will be for Windows 10. However we will continue to support Windows
7 & 8.1 with our 10.6 and 10.7 release series until their planned
EOL (10.6 EOL - mid 2019, 10.7 EOL - mid 2020) to coincide with
Microsoft's EOL for Windows 7.
_______________________________________________________________________

Base Product Specifications in 10.7c

*
[Supported Platforms]
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 11 x86/x86-64
Linux SLES 12 x86/x86-64
Windows 7 x86/x64
Windows 8.1 x86/x64
Windows 10 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.2.1-mingw32vc12
[OVL (shipped with product)]
 v2.8.1
[VHDL OSVVM (shipped with product)]
v2014.07
[Licensing]
FLEXnet v11.14.1.3
MSL v2017_1_patch2
MGLS v9.17_10.2.4
PCLS v9.17.10.2.0
_______________________________________________________________________

Compatibility Issues with Release 10.7c

Key Information Compatibility

* QSIM-140 - (results) The compiler +protect flow is in process of
deprecation. This affects the vlog and vcom compilers. The
recommended flow is to use vencrypt (Verilog/SV) or vhencrypt
(VHDL) followed by vlog or vcom compilation. The deprecation
process starts with a warning if this option is used, which will
become an error in later releases. The reason for this change is to
remove the source ambiguities referenced by the compilation
libraries. An encrypted compilation is a compilation of the
post-encryption sources and must not retain any association with
pre-encryption sources. This principle is reinforced by maintaining
a two-step flow.

SystemVerilog Compatibility
* QSIM-17634 - (results) Optimized cell path delays could be
incorrectly shortened when used with negative timing checks.
* QSIM-8147 - (results) Restart with designs having negative timing
check limits could effect simulation timing checks and functional
evaluation behavior.
_______________________________________________________________________

User Interface Defects Repaired in 10.7c

* QSIM-21724 - The logging of nets or registers of types containing
SV unions has several issues which would lead to crashes or the
display of incorrect data. These issues have been resolved.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.7c

* QSIM-50272 - The vencrypt feature "-auto3protect" could not
properly handle macro call syntax in the port list of a module.
* QSIM-17634 - (results) Optimized cell path delays could be
incorrectly shortened when used with negative timing checks.
* QSIM-8147 - (results) Restart with designs having negative timing
check limits could effect simulation timing checks and functional
evaluation behavior.
_______________________________________________________________________

VHDL Defects Repaired in 10.7c

* QSIM-43580 - A port association that is an aggregate with an OTHERS
choice, for a constrained port that is an array-of-array, and where
those constraints are globally static, could result in either a
compiler internal error or a run-time simulator error about
mismatched array lengths.
* QSIM-50516 - In some case vopt generate an internal error or bad
code for a configuration. This would occur if a generic or port of
a component being configuration was used anywhere other than the
port/generic map.
_______________________________________________________________________

User Interface Enhancements in 10.7c

* QSIM-35477 - The SourceDir variable has improved the remapping
behavior for finding source files. Instead of having to define each
source directory location, defining a single root source directory
should be sufficient to find any source file within the directory
sub-tree, as long as the sub-tree path is the same as the original.
_______________________________________________________________________

SystemVerilog Enhancements in 10.7c

* [nodvtid] - Verilog design units' library signatures have changed
from previous versions of 10.7. This requires a refresh when using
previous 10.7 libraries in 10.7c.
_______________________________________________________________________

Document Revision History in 10.7c

* Revision - Changes - Status/Date
+ 3.3 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/August 2017
+ 3.2 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/May 2018
+ 3.1 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/March 2018
* Author: In-house procedures and working practices require multiple
authors for documents. All associated authors for each topic within
this document are tracked within the document source.
* Revision History: Released documents maintain a revision history of
up to four revisions. For earlier revision history, refer to
earlier releases of documentation which are available on Support
Center (http://support.mentor.com).