21EC71:Advanced VLSI

Module1: An Introduction to
ASICs

Prof. Manjunath E
Dept. of Electronics & Communication Engineering,
Dr. T Thimmaiah Institute of Technology,
Kolar Gold Fields

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Objectives:
This course provide the students, the knowledge about

1) Physical design flow of IC

-Floor-planning, Placement and Routing

2) Verification Guidelines (Test Bench Functionality)

3) Connecting Test Bench & Separating Test Bench

4) Randomization in System Verilog

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5) Application Specific Integrated Circuit

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At the end of the course the student will be able to:

COs Course Outcomes

CO1 Understand VLSI Design Flow
CO2 Describe the Concepts of ASIC Design methodology
CO3 Create Floor Plan including partition & routing with
the use of CAD Algorithms
CO4 Will have better insights into VLSI Back-end design
flow
CO5 Learn verification basics and system Verilog

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 Assessment Details (CIE &
SEE)

Continuous Assessment Assignments Quiz CIE Scaled

Evaluation Total down
to
1 2 3 1 2
20 M 20M 20M 10M 10M 20M 100M 50M

Total CIE SEE Total

50M 50M 100M

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 ASIC Cell Libraries
1. For a programmable ASIC the FPGA company supplies you with a library of
logic cells in the form of a design Kit
2. For MGAs and CBICs you have three choices: the ASIC vendor (the company
that will build your ASIC) will supply a cell library, or you can buy a cell library
from a third-party library vendor , or you can build your own cell library.
3. The first choice, using an ASIC-vendor library , requires you to use a set of
design tools approved by the ASIC vendor to enter and simulate your design
4. An ASIC vendor library is normally a phantom library the cells are empty
boxes, or also called phantoms
5. After you complete layout you hand off a netlist to the ASIC vendor, who fills
in the empty boxes ( phantom instantiation ) before manufacturing your chip.
6. The second and third choices require you to make a buy-or-build decision . If
you complete an ASIC design using a cell library that you bought, you also own
the masks (the tooling ) that are used to manufacture your ASIC. This is called

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customer-owned tooling ( COT).

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7. The third choice is to develop a cell library in-house (The process of
library
development is complex and very expensive)
8. However created, each cell in an ASIC cell library must contain the
following:
• Physical Layout: This is the actual geometric representation of the cell
at the physical level. It includes the precise positioning of transistors,
metal layers, and vias that will be used during fabrication.
• Behavioral Model: This is an abstract model that describes how the
cell behaves functionally without detailing the internal structure. It helps
simulate the cell's logic and functionality early in the design process.
• Verilog/VHDL Model: These are hardware description language
(HDL) models that describe the cell in terms of logic gates and behavior.

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Verilog and VHDL are two common HDLs used to model and simulate
digital circuits A detailed timing model
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Detailed Timing Model: This provides the precise timing characteristics of the cell,
including delay times, setup times, hold times, etc. It is essential for timing analysis to
ensure the circuit meets speed and performance requirements.
Test Strategy: This defines how the cell will be tested during manufacturing to
ensure it is functioning correctly. This may include test vectors or methodologies like
built-in self-test (BIST) or scan chains.
Circuit Schematic: This is the electrical representation of the cell, showing how
components like transistors, resistors, and capacitors are connected. It is a crucial step
in verifying the logic and design correctness.
Cell Icon: A graphical representation of the cell used in design tools for easy
identification and placement during circuit design.
Wire-Load Model: This predicts the capacitance and resistance of the interconnect
wires connected to the cell based on its size and placement in the chip. It helps in
estimating the performance impact due to wiring.
Routing Model: This provides information about how the cell will connect to other

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cells during the routing phase of the design. It specifies how signals will be passed
between cells through metal layers on the chip.

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 Data Path Logic Cells
• Suppose we wish to build an n -bit adder (that adds two n -bit numbers) and to
exploit the regularity of this function in the layout. We can do so using a data path
structure.

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Fig. No: 2.20

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Data Path Element:

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 Conventional Ripple
Adders: Carry Adder.
•The delay of an n -bit RCA is
proportional to n and is limited by
the propagation of the carry signal
through all of the stages.

•We can reduce delay by using pairs

of go-faster bubbles to change AND
and OR gates to fast two-input
NAND gates

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 Adders:
Ripple Carry Adder (RCA): Method 2

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A B C CARRY
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 Generate= A B
Propagate= A xor
1 0 0 0
B
1 0 1 1
1 1 0 1
1 1 1 1

Generalized Carry Equation: Ci+1=Gi+(Pi .

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Ci)

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• Carry Lookahead Adder

Carry Chain using 2-input Nand

Gates, one/cell

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C2[i-1]

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C4[i-1]

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Brunt
Kung
CLA

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 Adders:
Carry Save Adder (CSA):

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1) In a CSA the carries are “saved” at each stage and shifted left
onto the bus S1
2) There is thus no carry propagation and the delay of a CSA is
constant
3) At the output stage of a CSA we still need to add the S1 bus (all
the saved carries) and the S2 bus (all the sums) to get the an n-
bit result using a final stage.

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 Carry Bypass Adder
1) The Problem of RCA is that every stage has to wait to make its carry
decision until the previous stage is calculated
2) If we examine the propagate signals we can bypass this critical path

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 Carry Skip Adder
1) Instead of checking the propagate signals we can check the
inputs
2) Using MUX through input we decide to Propagate or to SKIP
A B Cin CARRY Generate= A B
0 0 0 0 Propagate= A xor
B
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1

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1 1 1 1

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Carry Select Adder

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Conditional Sum Adder

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Multiplier (Booth Encoding)

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Tree Based Multiplication:

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Other Datapath Elements:

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I/O Cell:

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 Cell Compliers:

• The process of hand crafting circuits and layout for a full-

custom IC is a tedious, time-consuming, and error-prone task.
There are two types of automated layout assembly tools, often
known as a silicon compilers.
1. RAM compliers- It generates the hardware description
(often in HDL like Verilog or VHDL) for (RAM) blocks based on
user-defined specifications.
2. Programming language Compliers-software tool that
translates source code written in a high-level programming
language
3. Model Complier- Model compiler so that we can verify the
circuit at the behavioral level
4. Netlist Complier- Simulate the circuit and verify that it
works correctly at the structural level
5. Silicon Complier- Silicon compiler will produce working

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silicon even if every configuration has not been tested.

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